sync: SHANGHAI-U9 2026-08-26 fpga_update/gen_update_mcs.py 的 REPO 改读 skills_env.md 的 SMOD_REPO_ROOT(0819 遗漏的第三个文件)
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@@ -26,16 +26,6 @@ import subprocess
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import sys
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import tempfile
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REPO = r"E:\Xilinx_design\smod\SMOD_ATSC\my_exciter"
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TCL_DIR = os.path.join(REPO, "my_exciter.srcs", "tcl_1")
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BITSTREAM = os.path.join(REPO, "bitstream")
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IMPL = os.path.join(REPO, "my_exciter.runs", "impl_1")
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POST_BITSTREAM = os.path.join(TCL_DIR, "post_bitstream.tcl")
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GEN_RU = os.path.join(TCL_DIR, "runScript_GenRu.tcl")
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PERL_SCRIPT = os.path.join(TCL_DIR, "MakeSpiFlashProgrammerMcsFiles_backup.pl")
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def _env_lookup(key, default=None):
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"""Machine-local values (paths, IPs) live in ~/skills_env.md, never in git.
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An OS environment variable of the same name overrides the file."""
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@@ -56,6 +46,18 @@ def _env_lookup(key, default=None):
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return default
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# The my_exciter checkout root differs per machine; default keeps this machine's
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# historical path so behaviour is unchanged when the key is absent.
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REPO = _env_lookup("SMOD_REPO_ROOT", r"E:\Xilinx_design\smod\SMOD_ATSC\my_exciter")
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TCL_DIR = os.path.join(REPO, "my_exciter.srcs", "tcl_1")
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BITSTREAM = os.path.join(REPO, "bitstream")
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IMPL = os.path.join(REPO, "my_exciter.runs", "impl_1")
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POST_BITSTREAM = os.path.join(TCL_DIR, "post_bitstream.tcl")
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GEN_RU = os.path.join(TCL_DIR, "runScript_GenRu.tcl")
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PERL_SCRIPT = os.path.join(TCL_DIR, "MakeSpiFlashProgrammerMcsFiles_backup.pl")
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def resolve_vivado():
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"""Vivado's install path differs per machine -- never hardcode it."""
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exe = _env_lookup("VIVADO_PATH")
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