sync: HP_BOWEI 2026-09-09
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Myfro9
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"""fix_pcb.py — 导入后 PCB 修复（阶段 1.5 的两个硬骨头）。必须用 KiCad 自带 python 跑。
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A) BGA / 平面焊盘丢网络回填
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Altium 用负片内电层隐式连接电源地，KiCad 导入时这些焊盘拿不到网络，
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表现为成百上千个 "GND vs 空网络" 假短路。用阶段 0 导出的 Altium 网表真值
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(component,pin,net) 把空网络焊盘重新指派回去。
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B) 覆铜 zone 的本地 clearance
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Altium 导入器把【每块 zone 的本地 Clearance 写成 KiCad 默认 0.5mm】
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((zone ... (connect_pads (clearance 0.5))))，而本地值会盖过网络类 clearance
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—— 这就是导入后异 net 避让间隔明显偏大的根因。只改 .kicad_pro 的网络类
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或板级规则没有用，必须逐块 zone 改。目标值取 Altium 的 InPolygon 规则
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（XMOD/GQ 两个工程实测都是 0.254mm，但别照抄，去基线 pcb_design_rules.json 里查）。
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热焊盘 thermal_gap 通常已经对上 Altium PolygonConnect AirGap(0.165mm)，不要动。
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本脚本改完不 refill。大板上 SWIG refill 容易超时甚至段错误，去 KiCad GUI 里按 B
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填充，或走 IPC 后端。
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用法（KICAD_PYTHON 见 ~\\skills_env.md）:
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# 先干跑看看要动多少
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D:\\KiCad\\10.0\\bin\\python.exe fix_pcb.py --board X.kicad_pcb --netlist-csv t.csv \\
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--zone-clearance-mm 0.254 --dry-run
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# 确认后真改（会先备份 .kicad_pcb 到 <board>.bak_fixpcb）
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D:\\KiCad\\10.0\\bin\\python.exe fix_pcb.py --board X.kicad_pcb --netlist-csv t.csv \\
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--zone-clearance-mm 0.254
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"""
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from __future__ import annotations
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import argparse
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import csv
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import json
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import shutil
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import sys
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from pathlib import Path
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COMP_KEYS = ("component", "designator", "ref", "reference")
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PIN_KEYS = ("pin", "pin_number", "pad", "pin designator")
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NET_KEYS = ("net", "netname", "net name")
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def pick(fieldnames, candidates) -> str | None:
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lowered = {(f or "").strip().lower(): f for f in fieldnames}
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for c in candidates:
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if c in lowered:
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return lowered[c]
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return None
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def load_truth(csv_path: Path) -> dict[tuple[str, str], str]:
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"""Altium 网表真值 (component, pin) -> net。
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Altium 的 tabular 导出会把隐藏的电源/平面引脚重复列成 net='?' 的行，
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这些行没有信息量，直接丢掉。
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"""
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with csv_path.open(newline="", encoding="utf-8-sig") as f:
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reader = csv.DictReader(f)
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c_key = pick(reader.fieldnames or [], COMP_KEYS)
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p_key = pick(reader.fieldnames or [], PIN_KEYS)
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n_key = pick(reader.fieldnames or [], NET_KEYS)
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if not (c_key and p_key and n_key):
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raise SystemExit(
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f"[ERROR] 认不出 CSV 的列名：{reader.fieldnames}\n"
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f" 需要 component / pin / net 三列（大小写和别名可容忍）。")
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truth: dict[tuple[str, str], str] = {}
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dropped = 0
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for row in reader:
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comp = (row.get(c_key) or "").strip()
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pin = (row.get(p_key) or "").strip()
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net = (row.get(n_key) or "").strip()
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if not (comp and pin):
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continue
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if not net or net == "?":
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dropped += 1
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continue
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truth[(comp, pin)] = net
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print(f"[csv] 真值引脚 {len(truth)} 条（丢弃 net='?'/空 的重复行 {dropped} 条）")
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return truth
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def main() -> int:
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ap = argparse.ArgumentParser(description="Post-import KiCad PCB repair (nets + zone clearance)")
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ap.add_argument("--board", required=True, help=".kicad_pcb 路径")
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ap.add_argument("--netlist-csv", required=True,
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help="Altium 侧网表真值 CSV（阶段0 proj_export_netlist tabular）")
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ap.add_argument("--zone-clearance-mm", type=float, required=True,
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help="Altium InPolygon 规则的 polygon clearance，去基线 pcb_design_rules.json 查")
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ap.add_argument("--dry-run", action="store_true", help="只统计不落盘")
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ap.add_argument("--report", help="把统计写成 JSON")
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ap.add_argument("--skip-nets", action="store_true", help="只改 zone clearance，不动焊盘网络")
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ap.add_argument("--skip-zones", action="store_true", help="只回填焊盘网络，不动 zone clearance")
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args = ap.parse_args()
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try:
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import pcbnew
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except ImportError:
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print("[ERROR] 导不到 pcbnew —— 本脚本必须用 KiCad 自带的 python 跑，"
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"例如 D:\\KiCad\\10.0\\bin\\python.exe（见 ~\\skills_env.md 的 KICAD_PYTHON）。")
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return 1
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board_path = Path(args.board)
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if not board_path.is_file():
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print(f"[ERROR] 板文件不存在：{board_path}")
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return 1
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truth = load_truth(Path(args.netlist_csv)) if not args.skip_nets else {}
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board = pcbnew.LoadBoard(str(board_path))
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stats = {"assigned": 0, "no_truth": 0, "no_ref": 0, "already": 0,
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"zones_fixed": 0, "zones_skipped": 0}
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missing_examples: list[str] = []
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# ---- A) 焊盘网络回填 ----
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if not args.skip_nets:
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def get_net(name):
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ni = board.FindNet(name)
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if ni is None:
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ni = pcbnew.NETINFO_ITEM(board, name)
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board.Add(ni)
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return ni
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for fp in board.GetFootprints():
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ref = fp.GetReference()
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for pad in fp.Pads():
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if pad.GetNetCode() != 0 and pad.GetNetname() != "":
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stats["already"] += 1
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continue
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if not ref:
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stats["no_ref"] += 1
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continue
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net = truth.get((ref, pad.GetNumber()))
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if not net:
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stats["no_truth"] += 1
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if len(missing_examples) < 20:
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missing_examples.append(f"{ref}.{pad.GetNumber()}")
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continue
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if not args.dry_run:
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pad.SetNet(get_net(net))
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stats["assigned"] += 1
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print(f"[nets] 待回填={stats['assigned']} 真值里查不到={stats['no_truth']} "
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f"无位号={stats['no_ref']} 本来就有网络={stats['already']}")
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if missing_examples:
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print(f"[nets] 查不到真值的空网络焊盘举例：{', '.join(missing_examples)}")
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print(" 多为机械/屏蔽/安装孔焊盘。确认属实的话，按需单独指派 GND。")
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# ---- B) zone 本地 clearance ----
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if not args.skip_zones:
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clr = pcbnew.FromMM(args.zone_clearance_mm)
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for z in board.Zones():
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if z.GetIsRuleArea() or not z.IsOnCopperLayer():
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stats["zones_skipped"] += 1
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continue
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if not args.dry_run:
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z.SetLocalClearance(clr)
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stats["zones_fixed"] += 1
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print(f"[zones] 铺铜 zone 本地 clearance -> {args.zone_clearance_mm}mm "
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f"共 {stats['zones_fixed']} 块；跳过 {stats['zones_skipped']} 块（规则区/非铜层）")
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if args.dry_run:
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print("[dry-run] 没有写盘。去掉 --dry-run 才会真正修改。")
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else:
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backup = board_path.with_suffix(board_path.suffix + ".bak_fixpcb")
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shutil.copy2(board_path, backup)
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board.Save(str(board_path))
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print(f"[save] 已写回 {board_path}（原文件备份为 {backup.name}）")
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print("[next] 还要重填铺铜：KiCad GUI 里按 B，或走 IPC 后端。"
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"大板不要用 SWIG refill，会超时/段错误。")
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if args.report:
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Path(args.report).write_text(
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json.dumps({**stats, "zone_clearance_mm": args.zone_clearance_mm,
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"dry_run": args.dry_run,
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"no_truth_examples": missing_examples},
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ensure_ascii=False, indent=2), encoding="utf-8")
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print(f"[report] {args.report}")
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return 0
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if __name__ == "__main__":
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try:
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sys.stdout.reconfigure(encoding="utf-8")
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except Exception:
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pass
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sys.exit(main())
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