同步了 fpga_flash, vivado-prj-create 两个skill

2026-05-09 01:37:44 -05:00
parent 9e700d10b7
commit 17fb1b213d
13 changed files with 4467 additions and 0 deletions
@@ -0,0 +1,16 @@
+# Template: Step 3 - Generate .mcs configuration memory file
+# Called by gen_mcs.py via: vivado -mode batch -source step3_write_mcs.tcl -tclargs <bit_file> <mcs_file>
+#
+# Arguments (passed via -tclargs):
+#   argv[0] = BIT_FILE_PATH  - Full path to the .bit file (forward slashes)
+#   argv[1] = MCS_FILE_PATH  - Full path for the output .mcs file (forward slashes)
+#
+# Success indicator: output contains "write_cfgmem completed successfully" and "0 Errors"
+
+set bit_file [lindex $argv 0]
+set mcs_file [lindex $argv 1]
+
+write_cfgmem -format mcs -size 16 -interface SPIx1 \
+  -loadbit [list up 0x00000000 $bit_file] \
+  -checksum -force \
+  -file $mcs_file