同步了 fpga_flash, vivado-prj-create 两个skill

.stfolder/syncthing-folder-594de7.txt

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+# This directory is a Syncthing folder marker.
+# Do not delete.
+
+folderID: ggxeg-zoyv2
+created: 2026-05-09T01:23:05-05:00

fpga_flash/SKILL.md

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+---
+name: fpga_flash
+description: |
+  烧写 Artix-7 系列 FPGA 的外部 Flash（SPI NOR Flash）。适用于 EMV7.1 等 Artix-7 板卡，支持 Micron mt25ql128 和 Winbond w25q128bv 两种 Flash 型号。
+  当用户提到"烧写 flash"、"flash 编程"、"固化 bit 文件"、"下载到 flash"、"program flash"、"write flash"、"burn flash"、"Vivado flash"、"SPI flash 烧写"时，必须触发此 skill。
+---
+
+# FPGA Flash 烧写流程（Artix-7 / EMV7.1）
+
+本 skill 由 Claude **全自动执行**完整的 Flash 烧写流程。除了向用户确认必要信息外，所有操作（文件检查、CSV 修改、Vivado 命令执行、硬件编程）均由 Claude 直接完成，不要求用户手动执行任何命令。
+
+---
+
+## 执行规范
+
+**自动执行原则：**
+- 每个需要调用 Vivado 的步骤，Claude 通过 Bash 工具调用 skill `scripts/` 目录下的 Python 脚本
+- **禁止**在用户工程目录或系统临时目录（`%TEMP%`、`/tmp`）下创建任何脚本文件
+- 所有可执行脚本已预置在 skill 目录的 `scripts/` 子目录中，Claude 只需传入正确的参数调用
+
+**定位 skill 脚本目录：**
+
+Claude 在执行前需先确认脚本的完整路径。使用 Glob 工具查找：
+```
+C:/Users/<当前用户>/.claude/skills/fpga_flash/scripts/gen_mcs.py
+```
+或直接使用默认路径：`C:/Users/bowei/.claude/skills/fpga_flash/scripts/`
+
+**scripts/ 目录内容：**
+```
+scripts/
+  check_flash_csv.py     # 第一步：检查/更新 Vivado Flash 器件表
+  gen_mcs.py             # 第三步：生成 .mcs 文件
+  program_flash.py       # 第四、五步：连接目标板并烧写 Flash
+  step3_write_mcs.tcl    # gen_mcs.py 使用的 Tcl 模板（勿手动修改）
+  step4_5_program.tcl    # program_flash.py 使用的 Tcl 模板（勿手动修改）
+```
+
+**调用方式（Bash 工具）：**
+```bash
+python "C:/Users/bowei/.claude/skills/fpga_flash/scripts/<script>.py" [参数...]
+```
+
+各脚本通过命令行参数接受变量（Vivado 安装目录、工程名、bit 文件路径、mcs 文件路径等），内部调用 Vivado `-mode batch -source <tcl模板> -tclargs <参数>` 完成执行，全程不产生临时文件。
+
+---
+
+## 第一步：检查并修复 Vivado Flash 器件表
+
+**Claude 自动执行：**
+
+调用 `check_flash_csv.py`，检查 `xicom_cfgmem_part_table.csv` 中是否已包含 `w25q128bv-spi-x1_x2_x4`：
+
+```bash
+python "C:/Users/bowei/.claude/skills/fpga_flash/scripts/check_flash_csv.py" \
+    --vivado-dir "D:/Xilinx/Vivado/2018.1"
+```
+
+**返回值含义：**
+- 退出码 `0`：器件已存在，直接进入第二步
+- 退出码 `2`：已成功添加器件行，需提示用户**重启 Vivado** 后才能识别
+- 退出码 `1`：CSV 未找到，询问用户提供正确的 Vivado 安装目录后重试
+
+若 Vivado 不在默认路径 `D:/Xilinx/Vivado/2018.1`，询问用户后替换 `--vivado-dir` 的值。
+
+---
+
+## 第二步：选择 Flash 型号
+
+询问用户板卡上焊接的 Flash 芯片型号，仅支持以下两种：
+
+| 选项 | 厂商 | `--flash-part` 值 |
+|------|------|-----------------|
+| 1 | Micron | `mt25ql128-spi-x1_x2_x4` |
+| 2 | Winbond | `w25q128bv-spi-x1_x2_x4` |
+
+记录用户选择，后续步骤中作为 `--flash-part` 参数传入。如果用户不确定，提示查看板卡丝印或原理图中 Flash 芯片的位号。
+
+---
+
+## 第三步：确认文件路径并自动生成 .mcs
+
+**需向用户确认：**
+1. **.bit 文件**的完整路径（通常在工程 `runs/impl_1/` 目录下）
+2. **输出 .mcs 文件**的保存路径和文件名（建议与 .bit 文件同目录）
+
+用户确认后，**Claude 自动调用**：
+
+```bash
+python "C:/Users/bowei/.claude/skills/fpga_flash/scripts/gen_mcs.py" \
+    --vivado-dir "D:/Xilinx/Vivado/2018.1" \
+    --bit-file   "E:/Xilinx_design/smod/SMOD_DTMB_CG/RU_golden/RU_golden.runs/impl_1/RU_golden_top.bit" \
+    --mcs-file   "E:/Xilinx_design/smod/SMOD_DTMB_CG/RU_golden/RU_golden.runs/impl_1/RU_golden_smod.mcs"
+```
+
+将示例路径替换为用户实际的 Vivado 安装路径、.bit 文件路径、.mcs 输出路径。
+
+**验证成功的标志：** 输出中包含 `write_cfgmem completed successfully` 且显示 `0 Errors`。
+
+---
+
+## 第四步 + 第五步：连接目标板、配置存储器并烧写
+
+确认板卡已上电并连接 JTAG 后，**Claude 自动调用**：
+
+```bash
+python "C:/Users/bowei/.claude/skills/fpga_flash/scripts/program_flash.py" \
+    --vivado-dir  "D:/Xilinx/Vivado/2018.1" \
+    --flash-part  "w25q128bv-spi-x1_x2_x4" \
+    --bit-file    "E:/Xilinx_design/smod/SMOD_DTMB_CG/RU_golden/RU_golden.runs/impl_1/RU_golden_top.bit" \
+    --mcs-file    "E:/Xilinx_design/smod/SMOD_DTMB_CG/RU_golden/RU_golden.runs/impl_1/RU_golden_smod.mcs" \
+    --ltx-file    "E:/Xilinx_design/smod/SMOD_DTMB_CG/RU_golden/RU_golden.runs/impl_1/RU_golden_top.ltx"
+```
+
+**参数说明：**
+- `--flash-part`：第二步用户选择的型号
+- `--bit-file`：第三步确认的 .bit 路径
+- `--mcs-file`：第三步生成的 .mcs 路径
+- `--ltx-file`：若设计无 ILA，省略此参数（脚本自动跳过 PROBES.FILE 配置）
+
+此脚本在同一个 Vivado batch 会话中完成：硬件连接 → cfgmem 器件创建 → 擦除/编程/验证。
+
+**验证成功的标志：** 输出包含 `End of startup status: HIGH` 且无 `ERROR` 行。
+
+ILA core 的 `Dropping logic core` WARNING 是正常现象（golden 镜像不含 ILA core），不影响烧写结果。
+
+---
+
+## 第六步：上电验证
+
+烧写完成后，提示用户：
+1. **断开 JTAG**，给板卡重新上电（或按复位键）
+2. 观察 FPGA 是否从 Flash 正常加载（DONE 灯亮起）
+3. 如果 DONE 灯不亮，检查：
+   - BOOT_MODE 跳线是否选择 SPI Flash 启动模式
+   - MCS 生成时起始地址是否为 `0x0`
+   - 板卡电源是否满足 Flash 的 VCC 要求（3.3V / 1.8V）
+
+---
+
+## 常见错误排查
+
+| 现象 | 可能原因 | 解决方法 |
+|------|----------|----------|
+| `check_flash_csv.py` 退出码 1 | Vivado 不在默认路径 | 询问用户，更换 `--vivado-dir` 参数 |
+| Vivado 中找不到 w25q128bv | CSV 已修改但 Vivado 未重启 | 提示用户重启 Vivado 后重新执行 |
+| `No hardware target` 错误 | JTAG 未连接或板卡未上电 | 检查连接后重新执行第四步 |
+| DONE 灯不亮 | 启动模式跳线错误 | 检查 MODE 引脚电平，确认为 SPI 启动模式 |
+| 烧写后板卡跑旧程序 | Flash 未完全擦除 | 确认 `PROGRAM.ERASE 1` 已设置后重新执行 |
+| `PermissionError` 写 CSV | 权限不足 | 提示用户以管理员身份运行 Claude Code |

fpga_flash/Task01.md

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+# OpenClaw 平台 FPGA Flash 烧写 Skill 改造方案
+
+## 1. 背景与改造难点
+
+目前 `fpga_flash` 这个 skill 是为原版 Claude Code（运行在 Windows 主机上）设计的，脚本中直接调用了 `python` 并使用 Windows 风格的路径（如 `D:/Xilinx/...`、`C:/Users/...`）。
+
+由于 **OpenClaw 是安装在 WSL (Linux) 环境下**的，直接将现有 `SKILL.md` 迁移过去会面临以下跨系统环境问题：
+1. **Python 解释器环境错位**：在 WSL 的 Bash 中执行 `python` 会调用 Linux 版的 Python，而不是 Windows 环境下的 Python，这可能导致调用 Windows 版 Vivado 时遇到各种环境变量和子进程调用的兼容性问题。
+2. **文件路径格式不兼容**：WSL 中的文件路径是 `/mnt/c/...` 或 `/mnt/e/...` 的形式，而原 Python 脚本（如 `check_flash_csv.py`、`program_flash.py`）预期的是 Windows 路径（`C:/...`、`E:/...`）。直接传入 Linux 路径会导致脚本中的 `os.path.isfile()` 等检查失败。
+3. **硬件连接限制**：FPGA 的 JTAG 烧写器通常连接在 Windows 主机的 USB 端口。虽然 WSL 支持 USB 透传，但最稳定可靠的方式是直接在 Windows 端发起 `vivado -mode batch` 调用，以直接使用 Windows 的 Hardware Server。
+
+## 2. 核心改造方案
+
+利用 WSL 优秀的**互操作性（Interop）**，我们不需要对 `scripts/` 目录下的 Python 脚本和 Tcl 脚本做任何修改，只需修改 `SKILL.md` 中的 Prompt，指导 OpenClaw agent 跨环境调用。
+
+**核心机制：**
+- **通过 `python.exe` 越界调用**：在 WSL 中可以直接执行 Windows 命令。我们将原 `SKILL.md` 中的 `python` 替换为 `python.exe`。这样执行时会自动启动 Windows Python 解释器，完全在 Windows 上下文中运行脚本。
+- **强制要求路径转换**：在 `SKILL.md` 中增加明确的提示词（Prompt），要求 OpenClaw 在提取文件路径（可能由于它在 WSL 中浏览文件，拿到的是 `/mnt/e/...`）后，**必须先将其转换为 Windows 盘符格式**再作为参数传递。
+
+## 3. 具体实施步骤
+
+### 步骤 1：修改 `SKILL.md` 提示词
+
+需要在 `SKILL.md` 中的“执行规范”或相关步骤的命令示例中进行如下调整（在后续实施时可直接修改）：
+
+1. **更改执行命令**：将所有示例中的 `python` 更改为 `python.exe`。
+   *原版：* `python "C:/Users/bowei/.claude/skills/fpga_flash/scripts/gen_mcs.py" ...`
+   *修改后：* `python.exe "C:/Users/bowei/.claude/skills/fpga_flash/scripts/gen_mcs.py" ...`
+
+2. **增加跨环境路径转换指令**：在 `SKILL.md` 头部或执行规范中增加一条针对 WSL 环境的强调说明：
+   > **【WSL 跨环境执行重点约束】**
+   > 由于你当前运行在 WSL 环境中，而脚本、Vivado 及硬件都在 Windows 主机上，因此在执行调用前：
+   > 1. 必须使用 `python.exe`（而非 `python`）来调用脚本。
+   > 2. 所有传递给 `--vivado-dir`、`--bit-file`、`--mcs-file` 和 `--ltx-file` 的参数，**必须转换为 Windows 路径格式**（例如：将 `/mnt/e/Xilinx_design/...` 替换为 `E:/Xilinx_design/...`）。
+
+### 步骤 2：在 OpenClaw 中安装 Skill
+
+OpenClaw 对 `SKILL.md` 的支持与 Claude Code 兼容。可以通过以下方式将其挂载到 OpenClaw 中：
+
+在 WSL 中执行 OpenClaw 的 skill 安装命令，直接指向包含 `SKILL.md` 的目录。例如：
+```bash
+openclaw skills install /mnt/c/Users/bowei/.claude/skills/fpga_flash
+```
+*(注：根据 OpenClaw `skills --help` 的提示，`install` 指令支持本地路径安装。)*
+
+### 步骤 3：验证与测试
+
+在 OpenClaw 中对话输入：“请帮我把 E:/Xilinx_design/... 下的 bit 固化到 flash 中”。
+观察 OpenClaw 的行动轨迹，确认它是否：
+1. 成功识别出此时处于 WSL 环境，并正确生成了 `python.exe` 指令。
+2. 成功将 `/mnt/e/...` 等路径翻译成了 `E:/...` 格式。
+3. 成功连接到 Windows 侧的 Vivado Hardware Manager 并走通流程。
+
+## 4. 可选的鲁棒性优化（Wrapper Script）
+
+如果发现 OpenClaw 在路径转换上经常犯错（比如忘记转换），可以在 `scripts/` 目录下新增一个 WSL 专用的启动脚本 `run_in_win.sh`，其内容如下：
+
+```bash
+#!/bin/bash
+# 自动将传入的 WSL 路径通过 wslpath 转换为 Windows 路径，并调用 Windows python
+SCRIPT_PATH=$(wslpath -w "$1")
+shift
+ARGS=()
+for arg in "$@"; do
+    if [[ "$arg" == /mnt/* ]]; then
+        ARGS+=("$(wslpath -w "$arg")")
+    else
+        ARGS+=("$arg")
+    fi
+done
+python.exe "$SCRIPT_PATH" "${ARGS[@]}"
+```
+此时 `SKILL.md` 中直接指导 OpenClaw 调用 `./run_in_win.sh scripts/gen_mcs.py --bit-file /mnt/e/...` 即可，把环境切换的负担交给 Bash 脚本处理。这是一种更为稳妥的防呆设计。

fpga_flash/scripts/check_flash_csv.py

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+#!/usr/bin/env python3
+"""
+Step 1: Check and update Vivado Flash device CSV to include w25q128bv.
+
+Checks whether 'w25q128bv-spi-x1_x2_x4' is present in Vivado's
+xicom_cfgmem_part_table.csv. If not, appends the correct row.
+
+Usage:
+    python check_flash_csv.py --vivado-dir "D:/Xilinx/Vivado/2018.1"
+
+Exit codes:
+    0 = device already present (no changes made)
+    2 = device was successfully added (Vivado restart required)
+    1 = error (CSV not found or write failure)
+"""
+import argparse
+import os
+import sys
+
+DEVICE_NAME = "w25q128bv-spi-x1_x2_x4"
+# Fields: NAME, MEM_DEVICE, MEM_TYPE, MEM_DENSITY, DATA_WIDTH,
+#         MEM_MANUFACTURER, NUM_CFG_FILES, MEM_DEVICE_ALIAS, MEM_FAMILY
+NEW_ROW = "w25q128bv-spi-x1_x2_x4,w25q128bv,spi,128,x1_x2_x4,Winbond,1,w25q128b,w25q"
+
+
+def main():
+    parser = argparse.ArgumentParser(
+        description="Check/update Vivado Flash CSV for w25q128bv"
+    )
+    parser.add_argument(
+        "--vivado-dir",
+        required=True,
+        help="Vivado install root, e.g. D:/Xilinx/Vivado/2018.1",
+    )
+    args = parser.parse_args()
+
+    csv_path = os.path.join(
+        args.vivado_dir, "data", "xicom", "xicom_cfgmem_part_table.csv"
+    )
+    csv_path = csv_path.replace("\\", "/")
+
+    if not os.path.isfile(csv_path):
+        print(f"ERROR: CSV not found at: {csv_path}", file=sys.stderr)
+        print(
+            "       Please verify --vivado-dir points to a valid Vivado installation.",
+            file=sys.stderr,
+        )
+        sys.exit(1)
+
+    with open(csv_path, "r", encoding="utf-8") as f:
+        content = f.read()
+
+    if DEVICE_NAME in content:
+        print(f"[check_flash_csv] '{DEVICE_NAME}' already present. No changes needed.")
+        sys.exit(0)
+
+    # Append the new row (ensure trailing newline before adding)
+    if not content.endswith("\n"):
+        content += "\n"
+    content += NEW_ROW + "\n"
+
+    try:
+        with open(csv_path, "w", encoding="utf-8") as f:
+            f.write(content)
+    except PermissionError:
+        print(
+            f"ERROR: Cannot write to {csv_path}. Try running as Administrator.",
+            file=sys.stderr,
+        )
+        sys.exit(1)
+
+    print(f"[check_flash_csv] Added '{DEVICE_NAME}' to:")
+    print(f"  {csv_path}")
+    print()
+    print("NOTE: You must restart Vivado for the new Flash device to be recognized.")
+    sys.exit(2)
+
+
+if __name__ == "__main__":
+    main()

fpga_flash/scripts/gen_mcs.py

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+#!/usr/bin/env python3
+"""
+Step 3: Generate .mcs configuration memory file using Vivado batch mode.
+
+Calls Vivado with step3_write_mcs.tcl (located in the same scripts/ directory)
+via -tclargs so no temporary script files are created.
+
+Usage:
+    python gen_mcs.py \
+        --vivado-dir "D:/Xilinx/Vivado/2018.1" \
+        --bit-file   "E:/project/RU_golden/RU_golden.runs/impl_1/RU_golden_top.bit" \
+        --mcs-file   "E:/project/RU_golden/RU_golden.runs/impl_1/RU_golden_smod.mcs"
+
+Exit codes:
+    0 = success ("write_cfgmem completed successfully" in output)
+    1 = failure
+"""
+import argparse
+import os
+import subprocess
+import sys
+
+
+def norm(path: str) -> str:
+    """Normalize path to forward slashes (Vivado on Windows accepts both)."""
+    return path.replace("\\", "/")
+
+
+def main():
+    parser = argparse.ArgumentParser(
+        description="Generate .mcs from .bit via Vivado write_cfgmem"
+    )
+    parser.add_argument(
+        "--vivado-dir",
+        required=True,
+        help="Vivado install root, e.g. D:/Xilinx/Vivado/2018.1",
+    )
+    parser.add_argument(
+        "--bit-file",
+        required=True,
+        help="Full path to the .bit file",
+    )
+    parser.add_argument(
+        "--mcs-file",
+        required=True,
+        help="Full path for the output .mcs file",
+    )
+    args = parser.parse_args()
+
+    vivado_dir = norm(args.vivado_dir)
+    bit_file = norm(args.bit_file)
+    mcs_file = norm(args.mcs_file)
+
+    # Locate the TCL template alongside this script
+    scripts_dir = os.path.dirname(os.path.abspath(__file__))
+    tcl_template = os.path.join(scripts_dir, "step3_write_mcs.tcl").replace("\\", "/")
+
+    # Validate inputs
+    vivado_exe = os.path.join(vivado_dir, "bin", "vivado.bat")
+    if not os.path.isfile(vivado_exe):
+        print(f"ERROR: Vivado not found: {vivado_exe}", file=sys.stderr)
+        sys.exit(1)
+
+    if not os.path.isfile(bit_file):
+        print(f"ERROR: .bit file not found: {bit_file}", file=sys.stderr)
+        sys.exit(1)
+
+    if not os.path.isfile(tcl_template):
+        print(f"ERROR: TCL template not found: {tcl_template}", file=sys.stderr)
+        sys.exit(1)
+
+    cmd = [
+        vivado_exe,
+        "-mode", "batch",
+        "-source", tcl_template,
+        "-tclargs", bit_file, mcs_file,
+    ]
+    print(f"[gen_mcs] Vivado: {vivado_exe}")
+    print(f"[gen_mcs] bit  : {bit_file}")
+    print(f"[gen_mcs] mcs  : {mcs_file}")
+    print()
+
+    result = subprocess.run(cmd)
+    sys.exit(result.returncode)
+
+
+if __name__ == "__main__":
+    main()

fpga_flash/scripts/program_flash.py

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+#!/usr/bin/env python3
+"""
+Steps 4+5: Connect hardware target, configure cfgmem device, and program Flash.
+
+Calls Vivado with step4_5_program.tcl (located in the same scripts/ directory)
+via -tclargs so no temporary script files are created.
+
+Usage:
+    python program_flash.py \
+        --vivado-dir  "D:/Xilinx/Vivado/2018.1" \
+        --flash-part  "w25q128bv-spi-x1_x2_x4" \
+        --bit-file    "E:/project/impl_1/RU_golden_top.bit" \
+        --mcs-file    "E:/project/impl_1/RU_golden_smod.mcs" \
+        [--ltx-file   "E:/project/impl_1/RU_golden_top.ltx"]
+
+    If the design has no ILA (no .ltx file), omit --ltx-file or pass an
+    empty string; the TCL template will skip the PROBES.FILE settings.
+
+Supported flash parts:
+    Micron  : mt25ql128-spi-x1_x2_x4
+    Winbond : w25q128bv-spi-x1_x2_x4
+
+Exit codes:
+    0 = success ("End of startup status: HIGH" in output)
+    1 = failure
+"""
+import argparse
+import os
+import subprocess
+import sys
+
+
+def norm(path: str) -> str:
+    """Normalize path to forward slashes (Vivado on Windows accepts both)."""
+    return path.replace("\\", "/")
+
+
+def main():
+    parser = argparse.ArgumentParser(
+        description="Program FPGA SPI Flash via Vivado Hardware Manager"
+    )
+    parser.add_argument(
+        "--vivado-dir",
+        required=True,
+        help="Vivado install root, e.g. D:/Xilinx/Vivado/2018.1",
+    )
+    parser.add_argument(
+        "--flash-part",
+        required=True,
+        help="Vivado Flash part name, e.g. w25q128bv-spi-x1_x2_x4",
+    )
+    parser.add_argument(
+        "--bit-file",
+        required=True,
+        help="Full path to the .bit file",
+    )
+    parser.add_argument(
+        "--mcs-file",
+        required=True,
+        help="Full path to the .mcs file (from Step 3)",
+    )
+    parser.add_argument(
+        "--ltx-file",
+        default="",
+        help="Full path to the .ltx probes file (optional; omit if no ILA)",
+    )
+    args = parser.parse_args()
+
+    vivado_dir = norm(args.vivado_dir)
+    bit_file = norm(args.bit_file)
+    mcs_file = norm(args.mcs_file)
+    ltx_file = norm(args.ltx_file) if args.ltx_file else ""
+
+    # Locate the TCL template alongside this script
+    scripts_dir = os.path.dirname(os.path.abspath(__file__))
+    tcl_template = os.path.join(scripts_dir, "step4_5_program.tcl").replace("\\", "/")
+
+    # Validate inputs
+    vivado_exe = os.path.join(vivado_dir, "bin", "vivado.bat")
+    if not os.path.isfile(vivado_exe):
+        print(f"ERROR: Vivado not found: {vivado_exe}", file=sys.stderr)
+        sys.exit(1)
+
+    for label, path in [("bit", bit_file), ("mcs", mcs_file)]:
+        if not os.path.isfile(path):
+            print(f"ERROR: .{label} file not found: {path}", file=sys.stderr)
+            sys.exit(1)
+
+    if ltx_file and not os.path.isfile(ltx_file):
+        print(f"ERROR: .ltx file not found: {ltx_file}", file=sys.stderr)
+        sys.exit(1)
+
+    if not os.path.isfile(tcl_template):
+        print(f"ERROR: TCL template not found: {tcl_template}", file=sys.stderr)
+        sys.exit(1)
+
+    cmd = [
+        vivado_exe,
+        "-mode", "batch",
+        "-source", tcl_template,
+        "-tclargs", args.flash_part, bit_file, mcs_file, ltx_file,
+    ]
+    print(f"[program_flash] Vivado    : {vivado_exe}")
+    print(f"[program_flash] Flash part: {args.flash_part}")
+    print(f"[program_flash] bit       : {bit_file}")
+    print(f"[program_flash] mcs       : {mcs_file}")
+    if ltx_file:
+        print(f"[program_flash] ltx       : {ltx_file}")
+    else:
+        print(f"[program_flash] ltx       : (none - no ILA)")
+    print()
+
+    result = subprocess.run(cmd)
+    sys.exit(result.returncode)
+
+
+if __name__ == "__main__":
+    main()

fpga_flash/scripts/step3_write_mcs.tcl

@@ -0,0 +1,16 @@
+# Template: Step 3 - Generate .mcs configuration memory file
+# Called by gen_mcs.py via: vivado -mode batch -source step3_write_mcs.tcl -tclargs <bit_file> <mcs_file>
+#
+# Arguments (passed via -tclargs):
+#   argv[0] = BIT_FILE_PATH  - Full path to the .bit file (forward slashes)
+#   argv[1] = MCS_FILE_PATH  - Full path for the output .mcs file (forward slashes)
+#
+# Success indicator: output contains "write_cfgmem completed successfully" and "0 Errors"
+
+set bit_file [lindex $argv 0]
+set mcs_file [lindex $argv 1]
+
+write_cfgmem -format mcs -size 16 -interface SPIx1 \
+  -loadbit [list up 0x00000000 $bit_file] \
+  -checksum -force \
+  -file $mcs_file

fpga_flash/scripts/step4_5_program.tcl

@@ -0,0 +1,47 @@
+# Template: Steps 4+5 - Connect hardware, configure cfgmem, and program Flash
+# Called by program_flash.py via: vivado -mode batch -source step4_5_program.tcl -tclargs <flash_part> <bit_file> <mcs_file> <ltx_file>
+#
+# Arguments (passed via -tclargs):
+#   argv[0] = FLASH_PART      - Flash part name, e.g. w25q128bv-spi-x1_x2_x4
+#   argv[1] = BIT_FILE_PATH   - Full path to the .bit file
+#   argv[2] = MCS_FILE_PATH   - Full path to the .mcs file
+#   argv[3] = LTX_FILE_PATH   - Full path to .ltx file, or empty string "" if no ILA
+#
+# Success indicator: output contains "End of startup status: HIGH" and no ERROR lines
+
+set flash_part [lindex $argv 0]
+set bit_file   [lindex $argv 1]
+set mcs_file   [lindex $argv 2]
+set ltx_file   [lindex $argv 3]
+set has_ltx    [expr {$ltx_file ne ""}]
+
+open_hw
+connect_hw_server
+open_hw_target
+
+set_property PROGRAM.FILE $bit_file [get_hw_devices xc7a200t_0]
+if {$has_ltx} {
+    set_property PROBES.FILE      $ltx_file [get_hw_devices xc7a200t_0]
+    set_property FULL_PROBES.FILE $ltx_file [get_hw_devices xc7a200t_0]
+}
+current_hw_device [get_hw_devices xc7a200t_0]
+refresh_hw_device [lindex [get_hw_devices xc7a200t_0] 0]
+
+create_hw_cfgmem -hw_device [lindex [get_hw_devices xc7a200t_0] 0] \
+  [lindex [get_cfgmem_parts $flash_part] 0]
+set_property PROGRAM.BLANK_CHECK 0 [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
+set_property PROGRAM.ERASE       1 [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
+set_property PROGRAM.CFG_PROGRAM 1 [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
+set_property PROGRAM.VERIFY      1 [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
+set_property PROGRAM.CHECKSUM    0 [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
+set_property PROGRAM.FILES [list $mcs_file] \
+  [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
+refresh_hw_device [lindex [get_hw_devices xc7a200t_0] 0]
+
+if {$has_ltx} {
+    set_property PROBES.FILE      $ltx_file [get_hw_devices xc7a200t_0]
+    set_property FULL_PROBES.FILE $ltx_file [get_hw_devices xc7a200t_0]
+}
+set_property PROGRAM.FILE $bit_file [get_hw_devices xc7a200t_0]
+program_hw_devices [get_hw_devices xc7a200t_0]
+refresh_hw_device [lindex [get_hw_devices xc7a200t_0] 0]

vivado-prj-create/SKILL.md

@@ -0,0 +1,609 @@
+---
+name: vivado-prj-create
+description: DIRECT EXECUTION - Auto-create Vivado FPGA projects. Triggers: "create Vivado project", "Vivado工程", "FPGA project", "Xilinx project", "setup Vivado". When triggered, IMMEDIATELY execute Step 0 without listing skills or asking for confirmation.
+---
+
+# Vivado Project TCL Generator
+
+## AI ASSISTANT BEHAVIOR RULES (CRITICAL)
+
+**When this skill is triggered, you MUST:**
+1. **DO NOT** list available skills
+2. **DO NOT** ask user "which skill do you want?"
+3. **DO NOT** ask for confirmation before proceeding
+4. **IMMEDIATELY** start with **Step 0: Check Vivado installation**
+5. Follow the complete workflow without interruption
+
+**Trigger Keywords:** "创建Vivado工程", "create Vivado project", "FPGA工程", "setup FPGA project", "Xilinx project", "Vivado TCL"
+
+This skill helps you generate TCL scripts for automatically creating Xilinx Vivado FPGA projects on Windows. The generated TCL script can be sourced directly in Vivado to create a complete project with proper device configuration.
+
+## How it works
+
+1. **Check Vivado installation (Step 0)**
+2. **Collect required information via interactive questions**
+3. Generate a complete TCL script
+4. Save the script to a file
+5. Provide instructions for running it
+
+## IMPORTANT: Vivado Installation Check (Step 0 - REQUIRED)
+
+**Before asking any questions, you MUST first check if Vivado is installed at the default location.**
+
+Use the Bash tool to check if the default Vivado installation path exists:
+
+```bash
+test -d "d:/Xilinx/Vivado/2018.1/bin" && echo "EXISTS" || echo "NOT_FOUND"
+```
+
+- If the result is `EXISTS`: Proceed to Step 1 (interactive questions)
+- If the result is `NOT_FOUND`: **Stop and report error to the user:**
+
+```
+错误 / Error: Vivado 没有正确安装！
+
+请确认 Vivado 已安装在默认路径: d:\Xilinx\Vivado\2018.1\bin\
+
+Please ensure Vivado is installed at: d:\Xilinx\Vivado\2018.1\bin\
+```
+
+## IMPORTANT: Interactive Question Requirements
+
+**After Vivado installation is confirmed, use the `AskUserQuestion` tool to collect the following required information.**
+
+### Step 1: Ask for FPGA Device/Part Number (REQUIRED)
+
+Use `AskUserQuestion` to let the user select their target FPGA device. Only these four devices are supported:
+
+```javascript
+AskUserQuestion({
+  questions: [{
+    question: "请选择你的FPGA器件型号 / Select your target FPGA device:",
+    header: "FPGA Device",
+    options: [
+      { label: "xc7z100ffg900-2", description: "Zynq-7000, 用于3.0激励器 / 3.0 Exciter" },
+      { label: "xc7z035ffg676-2", description: "Zynq-7000, 用于ipots" },
+      { label: "xc7a200tfbg676-2", description: "Artix-7, EMV7.1 / SMOD 激励器" },
+      { label: "xc7z020cfg400-2", description: "Zynq-7000, 用于RFSwitch" }
+    ],
+    multiSelect: false
+  }]
+})
+```
+
+**Note:** If you need other FPGA models, you must modify this skill file to add them.
+
+### Step 2: Ask for Project Name
+
+Ask the user for the project name. This can be done with a simple text prompt (no AskUserQuestion needed unless you want to provide preset options):
+
+**Example prompts:**
+- "请输入项目名称 / What would you like to name your project?"
+- "项目名称 / Enter the project name"
+
+## Zynq PS Configuration
+
+**IMPORTANT**: Determine if the selected device is a Zynq series (device starts with `xc7z`).
+
+- **Zynq devices** (xc7z100ffg900-2, xc7z035ffg676-2, xc7z020cfg400-2): **MUST** configure the Processing System (PS)
+- **Artix-7 devices** (xc7a200tfbg676-2): No PS configuration needed
+
+### Zynq Device PS Configurations
+
+For Zynq devices, use the corresponding PS configuration from the reference TCL files in this skill directory:
+
+| Device | Reference File | DDR Freq | FPGA0 Freq |
+|--------|---------------|----------|------------|
+| xc7z100ffg900-2 | emv9_atsc3_bd.tcl | 533.33 MHz | 250 MHz |
+| xc7z035ffg676-2 | ipots_bd.tcl | 266.67 MHz | 50 MHz |
+| xc7z020cfg400-2 | RF_switch_bd.tcl | 266.67 MHz | 50 MHz |
+
+### PS Configuration Template for Zynq Devices
+
+For Zynq devices, add the following Block Design creation with PS configuration to the TCL script:
+
+```tcl
+# =============================================================================
+# Create Block Design with Zynq PS Configuration
+# =============================================================================
+
+# Create Block Design
+set design_name "design_1"
+create_bd_design $design_name
+
+# Create Processing System instance
+set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
+
+# Apply PS configuration based on device type
+# {{PS_CONFIG_PROPERTIES}}
+
+# Create interface ports
+set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
+set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
+
+# Connect interfaces
+connect_bd_intf_net [get_bd_intf_pins processing_system7_0/DDR] [get_bd_intf_ports DDR]
+connect_bd_intf_net [get_bd_intf_pins processing_system7_0/FIXED_IO] [get_bd_intf_ports FIXED_IO]
+
+# Create and connect reset
+set rst_ps7_0_50M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_50M ]
+connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins rst_ps7_0_50M/slowest_sync_clk]
+connect_bd_net [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_50M/ext_reset_in]
+
+# Save Block Design
+save_bd_design
+
+# Make Block Design available
+make_wrapper -files [get_files ${design_name}.bd] -top
+add_files -norecurse {{PROJECT_NAME}}/{{PROJECT_NAME}}.srcs/sources_1/bd/${design_name}/hdl/${design_name}_wrapper.v
+update_compile_order -fileset sources_1
+```
+
+### PS Configuration Properties by Device
+
+Replace `{{PS_CONFIG_PROPERTIES}}` with the appropriate device configuration:
+
+**For xc7z100ffg900-2 (3.0 Exciter):**
+```tcl
+set_property -dict [list \
+   CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {250} \
+   CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {250} \
+   CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
+   CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333333} \
+   CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-15E} \
+   CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
+   CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
+   CONFIG.PCW_USE_M_AXI_GP0 {1} \
+   CONFIG.PCW_EN_RST0_PORT {1} \
+   CONFIG.PCW_EN_CLK0_PORT {1} \
+] $processing_system7_0
+```
+
+**For xc7z035ffg676-2 (ipots):**
+```tcl
+set_property -dict [list \
+   CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
+   CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
+   CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
+   CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {50.000000} \
+   CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
+   CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
+   CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {100.000000} \
+   CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {166.666672} \
+   CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
+   CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
+   CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
+   CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_CLK0_FREQ {50000000} \
+   CONFIG.PCW_CLK1_FREQ {10000000} \
+   CONFIG.PCW_CLK2_FREQ {10000000} \
+   CONFIG.PCW_CLK3_FREQ {10000000} \
+   CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
+   CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
+   CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
+   CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
+   CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
+   CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
+   CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {4} \
+   CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
+   CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
+   CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
+   CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
+   CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
+   CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
+   CONFIG.PCW_ENET0_RESET_ENABLE {0} \
+   CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_ENET1_RESET_ENABLE {0} \
+   CONFIG.PCW_ENET_RESET_ENABLE {0} \
+   CONFIG.PCW_EN_CLK0_PORT {1} \
+   CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \
+   CONFIG.PCW_EN_EMIO_GPIO {1} \
+   CONFIG.PCW_EN_EMIO_SDIO1 {0} \
+   CONFIG.PCW_EN_EMIO_SPI0 {1} \
+   CONFIG.PCW_EN_EMIO_SPI1 {1} \
+   CONFIG.PCW_EN_EMIO_UART0 {0} \
+   CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \
+   CONFIG.PCW_EN_ENET0 {1} \
+   CONFIG.PCW_EN_QSPI {1} \
+   CONFIG.PCW_EN_RST0_PORT {1} \
+   CONFIG.PCW_EN_SDIO0 {0} \
+   CONFIG.PCW_EN_SDIO1 {1} \
+   CONFIG.PCW_EN_SPI0 {1} \
+   CONFIG.PCW_EN_SPI1 {1} \
+   CONFIG.PCW_EN_UART0 {1} \
+   CONFIG.PCW_EN_UART1 {1} \
+   CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
+   CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {4} \
+   CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \
+   CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
+   CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
+   CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
+   CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
+   CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \
+   CONFIG.PCW_GPIO_EMIO_GPIO_IO {64} \
+   CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \
+   CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
+   CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
+   CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
+   CONFIG.PCW_IRQ_F2P_INTR {0} \
+   CONFIG.PCW_MIO_14_DIRECTION {in} \
+   CONFIG.PCW_MIO_14_IOTYPE {<Select>} \
+   CONFIG.PCW_MIO_14_PULLUP {enabled} \
+   CONFIG.PCW_MIO_14_SLEW {slow} \
+   CONFIG.PCW_MIO_15_DIRECTION {out} \
+   CONFIG.PCW_MIO_15_IOTYPE {<Select>} \
+   CONFIG.PCW_MIO_15_PULLUP {enabled} \
+   CONFIG.PCW_MIO_15_SLEW {slow} \
+   CONFIG.PCW_MIO_16_DIRECTION {out} \
+   CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_16_PULLUP {enabled} \
+   CONFIG.PCW_MIO_16_SLEW {fast} \
+   CONFIG.PCW_MIO_17_DIRECTION {out} \
+   CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_17_PULLUP {enabled} \
+   CONFIG.PCW_MIO_17_SLEW {fast} \
+   CONFIG.PCW_MIO_18_DIRECTION {out} \
+   CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_18_PULLUP {enabled} \
+   CONFIG.PCW_MIO_18_SLEW {fast} \
+   CONFIG.PCW_MIO_19_DIRECTION {out} \
+   CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_19_PULLUP {enabled} \
+   CONFIG.PCW_MIO_19_SLEW {fast} \
+   CONFIG.PCW_MIO_1_DIRECTION {out} \
+   CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_1_PULLUP {enabled} \
+   CONFIG.PCW_MIO_1_SLEW {slow} \
+   CONFIG.PCW_MIO_20_DIRECTION {out} \
+   CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_20_PULLUP {enabled} \
+   CONFIG.PCW_MIO_20_SLEW {fast} \
+   CONFIG.PCW_MIO_21_DIRECTION {out} \
+   CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_21_PULLUP {enabled} \
+   CONFIG.PCW_MIO_21_SLEW {fast} \
+   CONFIG.PCW_MIO_22_DIRECTION {in} \
+   CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_22_PULLUP {enabled} \
+   CONFIG.PCW_MIO_22_SLEW {fast} \
+   CONFIG.PCW_MIO_23_DIRECTION {in} \
+   CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_23_PULLUP {enabled} \
+   CONFIG.PCW_MIO_23_SLEW {fast} \
+   CONFIG.PCW_MIO_24_DIRECTION {in} \
+   CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_24_PULLUP {enabled} \
+   CONFIG.PCW_MIO_24_SLEW {fast} \
+   CONFIG.PCW_MIO_25_DIRECTION {in} \
+   CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_25_PULLUP {enabled} \
+   CONFIG.PCW_MIO_25_SLEW {fast} \
+   CONFIG.PCW_MIO_26_DIRECTION {in} \
+   CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_26_PULLUP {enabled} \
+   CONFIG.PCW_MIO_26_SLEW {fast} \
+   CONFIG.PCW_MIO_27_DIRECTION {in} \
+   CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_27_PULLUP {enabled} \
+   CONFIG.PCW_MIO_27_SLEW {fast} \
+   CONFIG.PCW_MIO_2_DIRECTION {inout} \
+   CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_2_PULLUP {disabled} \
+   CONFIG.PCW_MIO_2_SLEW {slow} \
+   CONFIG.PCW_MIO_3_DIRECTION {inout} \
+   CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_3_PULLUP {disabled} \
+   CONFIG.PCW_MIO_3_SLEW {slow} \
+   CONFIG.PCW_MIO_40_DIRECTION {inout} \
+   CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_40_PULLUP {enabled} \
+   CONFIG.PCW_MIO_40_SLEW {slow} \
+   CONFIG.PCW_MIO_41_DIRECTION {inout} \
+   CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_41_PULLUP {enabled} \
+   CONFIG.PCW_MIO_41_SLEW {slow} \
+   CONFIG.PCW_MIO_42_DIRECTION {in} \
+   CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_42_PULLUP {enabled} \
+   CONFIG.PCW_MIO_42_SLEW {slow} \
+   CONFIG.PCW_MIO_43_DIRECTION {out} \
+   CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_43_PULLUP {enabled} \
+   CONFIG.PCW_MIO_43_SLEW {slow} \
+   CONFIG.PCW_MIO_44_DIRECTION {out} \
+   CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_44_PULLUP {enabled} \
+   CONFIG.PCW_MIO_44_SLEW {slow} \
+   CONFIG.PCW_MIO_45_DIRECTION {in} \
+   CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_45_PULLUP {enabled} \
+   CONFIG.PCW_MIO_45_SLEW {slow} \
+   CONFIG.PCW_MIO_46_DIRECTION {inout} \
+   CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_46_PULLUP {enabled} \
+   CONFIG.PCW_MIO_46_SLEW {slow} \
+   CONFIG.PCW_MIO_47_DIRECTION {inout} \
+   CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_47_PULLUP {enabled} \
+   CONFIG.PCW_MIO_47_SLEW {slow} \
+   CONFIG.PCW_MIO_48_DIRECTION {inout} \
+   CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_48_PULLUP {enabled} \
+   CONFIG.PCW_MIO_48_SLEW {slow} \
+   CONFIG.PCW_MIO_49_DIRECTION {inout} \
+   CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_49_PULLUP {enabled} \
+   CONFIG.PCW_MIO_49_SLEW {slow} \
+   CONFIG.PCW_MIO_4_DIRECTION {inout} \
+   CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_4_PULLUP {disabled} \
+   CONFIG.PCW_MIO_4_SLEW {slow} \
+   CONFIG.PCW_MIO_50_DIRECTION {inout} \
+   CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_50_PULLUP {enabled} \
+   CONFIG.PCW_MIO_50_SLEW {slow} \
+   CONFIG.PCW_MIO_51_DIRECTION {inout} \
+   CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_51_PULLUP {enabled} \
+   CONFIG.PCW_MIO_51_SLEW {slow} \
+   CONFIG.PCW_MIO_52_DIRECTION {out} \
+   CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_52_PULLUP {enabled} \
+   CONFIG.PCW_MIO_52_SLEW {fast} \
+   CONFIG.PCW_MIO_53_DIRECTION {inout} \
+   CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_53_PULLUP {enabled} \
+   CONFIG.PCW_MIO_53_SLEW {fast} \
+   CONFIG.PCW_MIO_5_DIRECTION {inout} \
+   CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_5_PULLUP {disabled} \
+   CONFIG.PCW_MIO_5_SLEW {slow} \
+   CONFIG.PCW_MIO_6_DIRECTION {out} \
+   CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_6_PULLUP {disabled} \
+   CONFIG.PCW_MIO_6_SLEW {slow} \
+   CONFIG.PCW_MIO_TREE_PERIPHERALS {unassigned#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#unassigned#Quad SPI Flash#Quad SPI Flash#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 0#UART 0#UART 1#UART 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#Enet 0#Enet 0} \
+   CONFIG.PCW_MIO_TREE_SIGNALS {unassigned#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#unassigned#qspi0_io[3]/HOLD_B#qspi0_sclk#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#rx#tx#tx#rx#data[0]#cmd#clk#data[1]#data[2]#data[3]#mdc#mdio} \
+   CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
+   CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
+   CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
+   CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V} \
+   CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
+   CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {0} \
+   CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
+   CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
+   CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
+   CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
+   CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \
+   CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
+   CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
+   CONFIG.PCW_SD0_GRP_CD_ENABLE {0} \
+   CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
+   CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
+   CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_SD0_SD0_IO {<Select>} \
+   CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \
+   CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \
+   CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \
+   CONFIG.PCW_SD1_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_SD1_SD1_IO {MIO 46 .. 51} \
+   CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {10} \
+   CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
+   CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x2} \
+   CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_SPI0_GRP_SS0_ENABLE {1} \
+   CONFIG.PCW_SPI0_GRP_SS0_IO {EMIO} \
+   CONFIG.PCW_SPI0_GRP_SS1_ENABLE {1} \
+   CONFIG.PCW_SPI0_GRP_SS1_IO {EMIO} \
+   CONFIG.PCW_SPI0_GRP_SS2_ENABLE {1} \
+   CONFIG.PCW_SPI0_GRP_SS2_IO {EMIO} \
+   CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_SPI0_SPI0_IO {EMIO} \
+   CONFIG.PCW_SPI1_GRP_SS0_ENABLE {1} \
+   CONFIG.PCW_SPI1_GRP_SS0_IO {EMIO} \
+   CONFIG.PCW_SPI1_GRP_SS1_ENABLE {1} \
+   CONFIG.PCW_SPI1_GRP_SS1_IO {EMIO} \
+   CONFIG.PCW_SPI1_GRP_SS2_ENABLE {1} \
+   CONFIG.PCW_SPI1_GRP_SS2_IO {EMIO} \
+   CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_SPI1_SPI1_IO {EMIO} \
+   CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {6} \
+   CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \
+   CONFIG.PCW_SPI_PERIPHERAL_VALID {1} \
+   CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
+   CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_UART0_UART0_IO {MIO 42 .. 43} \
+   CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
+   CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_UART1_UART1_IO {MIO 44 .. 45} \
+   CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
+   CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
+   CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {266.666687} \
+   CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
+   CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \
+   CONFIG.PCW_UIPARAM_DDR_CL {7} \
+   CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
+   CONFIG.PCW_UIPARAM_DDR_CWL {6} \
+   CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
+   CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
+   CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
+   CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {266.6666666} \
+   CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-15E} \
+   CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
+   CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
+   CONFIG.PCW_UIPARAM_DDR_T_FAW {45.0} \
+   CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {36.0} \
+   CONFIG.PCW_UIPARAM_DDR_T_RC {49.5} \
+   CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
+   CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
+   CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {1} \
+   CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \
+   CONFIG.PCW_USE_M_AXI_GP0 {1} \
+   CONFIG.PCW_USE_M_AXI_GP1 {0} \
+   CONFIG.PCW_USE_S_AXI_HP0 {0} \
+] $processing_system7_0
+```
+
+**For xc7z020cfg400-2 (RFSwitch):**
+
+## TCL Script Template
+
+After collecting all required information via `AskUserQuestion`, generate a TCL script using this template structure:
+
+```tcl
+# =============================================================================
+# Vivado Project Auto-Generation Script
+# Project: {{PROJECT_NAME}}
+# Generated: {{TIMESTAMP}}
+# =============================================================================
+
+# Set Vivado installation path
+set vivado_path "{{VIVADO_PATH}}"
+
+# Create project
+create_project {{PROJECT_NAME}} ./{{PROJECT_NAME}} -part {{DEVICE_PART}} -force
+
+# Set project parameters
+set_property target_language Verilog [current_project]
+
+# Check if device is Zynq series (starts with xc7z)
+set device_part "{{DEVICE_PART}}"
+set is_zynq [regexp {^xc7z} $device_part]
+
+# Create Block Design for Zynq devices
+if {$is_zynq} {
+   # Add PS configuration based on device type
+   # See "Zynq PS Configuration" section above for device-specific configs
+   {{ZYNQ_PS_CONFIG_BLOCK}}
+}
+
+# Create default constraint file
+set constraint_file "{{PROJECT_NAME}}_constraints.xdc"
+set constr_file_obj [open ./{{PROJECT_NAME}}/$constraint_file w]
+puts $constr_file_obj "# Timing constraints for {{PROJECT_NAME}}"
+puts $constr_file_obj "# Add your constraints here"
+close $constr_file_obj
+
+add_files -fileset constrs_1 -norecurse ./{{PROJECT_NAME}}/$constraint_file
+
+# Create source directories
+file mkdir ./{{PROJECT_NAME}}/src
+file mkdir ./{{PROJECT_NAME}}/sim
+file mkdir ./{{PROJECT_NAME}}/synth
+
+# Print project info
+puts "=========================================="
+puts "Project '{{PROJECT_NAME}}' created successfully!"
+puts "Device: {{DEVICE_PART}}"
+if {$is_zynq} {
+   puts "PS Configured: Yes"
+} else {
+   puts "PS Configured: No (Pure FPGA device)"
+}
+puts "=========================================="
+
+# Save project
+save_project_as {{PROJECT_NAME}} ./{{PROJECT_NAME}}
+```
+
+## Variable Replacement
+
+Replace the template variables with user-provided values:
+
+| Variable | Description |
+|----------|-------------|
+| `{{VIVADO_PATH}}` | Vivado installation path (always: `D:/Xilinx/Vivado/2018.1`) |
+| `{{PROJECT_NAME}}` | Project name |
+| `{{DEVICE_PART}}` | FPGA part number |
+| `{{TIMESTAMP}}` | Current date/time |
+| `{{ZYNQ_PS_CONFIG_BLOCK}}` | For Zynq devices only: Block Design PS configuration (see above) |
+
+## Output File
+
+Save the generated TCL script as:
+- Default: `create_vivado_project.tcl` in the current working directory
+- Or use the project name: `create_{PROJECT_NAME}_project.tcl`
+
+## Usage Instructions
+
+After generating the script, provide the user with clear instructions:
+
+```
+To run this script in Vivado:
+
+1. Open Vivado:
+   - Start Menu → Xilinx Vivado [version]
+
+2. In the Vivado Tcl Console, run:
+   source /path/to/create_vivado_project.tcl
+
+3. Or from command line:
+   cd /path/to/script/directory
+   vivado -mode tcl -source create_vivado_project.tcl
+```
+
+## Best Practices
+
+1. **Validate the part number**: The TCL script uses the part number directly. Ensure the user enters a valid Xilinx part number format.
+
+2. **Path handling**: Windows paths in TCL use forward slashes `/` even though Windows uses backslashes `\`. Convert backslashes to forward slashes if the user provides them.
+
+3. **Project location**: The script creates the project in a subdirectory named after the project. This keeps the workspace organized.
+
+4. **Force flag**: The `-force` flag in `create_project` overwrites existing projects. Warn users if they already have a project with the same name.
+
+## Error Handling
+
+If the script execution fails, common causes include:
+
+1. **Invalid part number** - Check the part number format matches Xilinx naming convention
+2. **Path issues** - Ensure Vivado path uses forward slashes
+3. **Permissions** - Ensure write permissions in the target directory
+4. **Vivado version** - Some features may vary between Vivado versions
+
+## Optional Extensions
+
+After the basic project is created, you can offer to help with:
+
+- Adding IP integrator blocks
+- Setting up simulation waveforms
+- Creating custom constraints
+- Adding existing source files
+- Configuring synthesis and implementation settings

vivado-prj-create/evals/evals.json

@@ -0,0 +1,35 @@
+{
+  "skill_name": "vivado-project",
+  "evals": [
+    {
+      "id": 1,
+      "prompt": "I need to create a new Vivado project for my Artix-7 FPGA. Can you help me generate a TCL script? My Vivado is installed at C:/Xilinx/Vivado/2023.2 and I'm using xc7a35tcpg236-1 device with Verilog.",
+      "expected_output": "The skill MUST use AskUserQuestion to prompt for Vivado installation path first, then ask for FPGA device selection. After collecting all required info, generate a TCL script that creates a Vivado project with the specified device (xc7a35tcpg236-1), Vivado path (C:/Xilinx/Vivado/2023.2), and Verilog as the target language. The script should be saved to a .tcl file.",
+      "files": []
+    },
+    {
+      "id": 2,
+      "prompt": "帮我创建一个Vivado项目的TCL脚本，使用Zynq-7000系列FPGA，器件型号是xc7z020clg484-1，项目名称叫fpga_design，使用VHDL语言。Vivado安装在D:/Xilinx/Vivado/2024.1",
+      "expected_output": "The skill MUST use AskUserQuestion to prompt for Vivado installation path and FPGA device selection before proceeding. Then generate a TCL script for creating a Vivado project named 'fpga_design' with device xc7z020clg484-1, VHDL as target language, and Vivado path D:/Xilinx/Vivado/2024.1.",
+      "files": []
+    },
+    {
+      "id": 3,
+      "prompt": "I want to set up a Xilinx FPGA project automation. I'm targeting a Kintex-7 device (xc7k70tfbg484-1) and will write in Verilog. Where should I install Vivado and what TCL script do I need?",
+      "expected_output": "The skill MUST use AskUserQuestion to prompt for Vivado installation path first, then ask for FPGA device selection (with options including xc7k70tfbg484-1), ask for project name, and target language. Then generate a TCL script for the specified device and language.",
+      "files": []
+    },
+    {
+      "id": 4,
+      "prompt": "创建一个Vivado工程",
+      "expected_output": "The skill MUST use AskUserQuestion to prompt for: 1) Vivado installation path (with common options like C:/Xilinx/Vivado/2023.2, C:/Xilinx/Vivado/2024.1, etc.), 2) FPGA device selection (with comprehensive list of common devices), 3) Project name, 4) Target language (Verilog/VHDL). After collecting all info, generate and save a TCL script.",
+      "files": []
+    },
+    {
+      "id": 5,
+      "prompt": "I need help with a Vivado TCL script for my FPGA project",
+      "expected_output": "The skill MUST use AskUserQuestion to prompt for: 1) Vivado installation path (with common options), 2) FPGA device selection, 3) Project name, 4) Target language. Then generate a complete TCL script for creating the Vivado project.",
+      "files": []
+    }
+  ]
+}

vivado-prj-create/ipots_bd.tcl

@@ -0,0 +1,596 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2018.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xc7z035ffg676-2
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name design_1
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_bram_ctrl:4.0\
+xilinx.com:ip:smartconnect:1.0\
+xilinx.com:ip:processing_system7:5.5\
+xilinx.com:ip:proc_sys_reset:5.0\
+"
+
+   set list_ips_missing ""
+   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+  set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
+  set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
+  set REG_INF [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:bram_rtl:1.0 REG_INF ]
+  set_property -dict [ list \
+   CONFIG.MASTER_TYPE {BRAM_CTRL} \
+   CONFIG.READ_WRITE_MODE {READ_WRITE} \
+   ] $REG_INF
+  set REG_INF1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:bram_rtl:1.0 REG_INF1 ]
+  set_property -dict [ list \
+   CONFIG.MASTER_TYPE {BRAM_CTRL} \
+   CONFIG.READ_WRITE_MODE {READ_WRITE} \
+   ] $REG_INF1
+  set SPI0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:spi_rtl:1.0 SPI0 ]
+  set SPI1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:spi_rtl:1.0 SPI1 ]
+
+  # Create ports
+  set FCLK_CLK0 [ create_bd_port -dir O -type clk FCLK_CLK0 ]
+  set FCLK_RESET0_N [ create_bd_port -dir O -from 0 -to 0 -type rst FCLK_RESET0_N ]
+  set GPIO_EMIO_gpio_i [ create_bd_port -dir I -from 63 -to 0 GPIO_EMIO_gpio_i ]
+  set GPIO_EMIO_gpio_o [ create_bd_port -dir O -from 63 -to 0 GPIO_EMIO_gpio_o ]
+  set GPIO_EMIO_gpio_t [ create_bd_port -dir O -from 63 -to 0 GPIO_EMIO_gpio_t ]
+
+  # Create instance: axi_bram_ctrl_0, and set properties
+  set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.0 axi_bram_ctrl_0 ]
+  set_property -dict [ list \
+   CONFIG.SINGLE_PORT_BRAM {1} \
+ ] $axi_bram_ctrl_0
+
+  # Create instance: axi_bram_ctrl_1, and set properties
+  set axi_bram_ctrl_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.0 axi_bram_ctrl_1 ]
+  set_property -dict [ list \
+   CONFIG.SINGLE_PORT_BRAM {1} \
+ ] $axi_bram_ctrl_1
+
+  # Create instance: axi_smc, and set properties
+  set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {2} \
+   CONFIG.NUM_SI {1} \
+ ] $axi_smc
+
+  # Create instance: processing_system7_0, and set properties
+  set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
+  set_property -dict [ list \
+   CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
+   CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
+   CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
+   CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {50.000000} \
+   CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
+   CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
+   CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {100.000000} \
+   CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {166.666672} \
+   CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
+   CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
+   CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
+   CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_CLK0_FREQ {50000000} \
+   CONFIG.PCW_CLK1_FREQ {10000000} \
+   CONFIG.PCW_CLK2_FREQ {10000000} \
+   CONFIG.PCW_CLK3_FREQ {10000000} \
+   CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
+   CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
+   CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
+   CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
+   CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
+   CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
+   CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {4} \
+   CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
+   CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
+   CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
+   CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
+   CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
+   CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
+   CONFIG.PCW_ENET0_RESET_ENABLE {0} \
+   CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_ENET1_RESET_ENABLE {0} \
+   CONFIG.PCW_ENET_RESET_ENABLE {0} \
+   CONFIG.PCW_EN_CLK0_PORT {1} \
+   CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \
+   CONFIG.PCW_EN_EMIO_GPIO {1} \
+   CONFIG.PCW_EN_EMIO_SDIO1 {0} \
+   CONFIG.PCW_EN_EMIO_SPI0 {1} \
+   CONFIG.PCW_EN_EMIO_SPI1 {1} \
+   CONFIG.PCW_EN_EMIO_UART0 {0} \
+   CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \
+   CONFIG.PCW_EN_ENET0 {1} \
+   CONFIG.PCW_EN_QSPI {1} \
+   CONFIG.PCW_EN_RST0_PORT {1} \
+   CONFIG.PCW_EN_SDIO0 {0} \
+   CONFIG.PCW_EN_SDIO1 {1} \
+   CONFIG.PCW_EN_SPI0 {1} \
+   CONFIG.PCW_EN_SPI1 {1} \
+   CONFIG.PCW_EN_UART0 {1} \
+   CONFIG.PCW_EN_UART1 {1} \
+   CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
+   CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {4} \
+   CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \
+   CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
+   CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
+   CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
+   CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
+   CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \
+   CONFIG.PCW_GPIO_EMIO_GPIO_IO {64} \
+   CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \
+   CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
+   CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
+   CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
+   CONFIG.PCW_IRQ_F2P_INTR {0} \
+   CONFIG.PCW_MIO_14_DIRECTION {in} \
+   CONFIG.PCW_MIO_14_IOTYPE {<Select>} \
+   CONFIG.PCW_MIO_14_PULLUP {enabled} \
+   CONFIG.PCW_MIO_14_SLEW {slow} \
+   CONFIG.PCW_MIO_15_DIRECTION {out} \
+   CONFIG.PCW_MIO_15_IOTYPE {<Select>} \
+   CONFIG.PCW_MIO_15_PULLUP {enabled} \
+   CONFIG.PCW_MIO_15_SLEW {slow} \
+   CONFIG.PCW_MIO_16_DIRECTION {out} \
+   CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_16_PULLUP {enabled} \
+   CONFIG.PCW_MIO_16_SLEW {fast} \
+   CONFIG.PCW_MIO_17_DIRECTION {out} \
+   CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_17_PULLUP {enabled} \
+   CONFIG.PCW_MIO_17_SLEW {fast} \
+   CONFIG.PCW_MIO_18_DIRECTION {out} \
+   CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_18_PULLUP {enabled} \
+   CONFIG.PCW_MIO_18_SLEW {fast} \
+   CONFIG.PCW_MIO_19_DIRECTION {out} \
+   CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_19_PULLUP {enabled} \
+   CONFIG.PCW_MIO_19_SLEW {fast} \
+   CONFIG.PCW_MIO_1_DIRECTION {out} \
+   CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_1_PULLUP {enabled} \
+   CONFIG.PCW_MIO_1_SLEW {slow} \
+   CONFIG.PCW_MIO_20_DIRECTION {out} \
+   CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_20_PULLUP {enabled} \
+   CONFIG.PCW_MIO_20_SLEW {fast} \
+   CONFIG.PCW_MIO_21_DIRECTION {out} \
+   CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_21_PULLUP {enabled} \
+   CONFIG.PCW_MIO_21_SLEW {fast} \
+   CONFIG.PCW_MIO_22_DIRECTION {in} \
+   CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_22_PULLUP {enabled} \
+   CONFIG.PCW_MIO_22_SLEW {fast} \
+   CONFIG.PCW_MIO_23_DIRECTION {in} \
+   CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_23_PULLUP {enabled} \
+   CONFIG.PCW_MIO_23_SLEW {fast} \
+   CONFIG.PCW_MIO_24_DIRECTION {in} \
+   CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_24_PULLUP {enabled} \
+   CONFIG.PCW_MIO_24_SLEW {fast} \
+   CONFIG.PCW_MIO_25_DIRECTION {in} \
+   CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_25_PULLUP {enabled} \
+   CONFIG.PCW_MIO_25_SLEW {fast} \
+   CONFIG.PCW_MIO_26_DIRECTION {in} \
+   CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_26_PULLUP {enabled} \
+   CONFIG.PCW_MIO_26_SLEW {fast} \
+   CONFIG.PCW_MIO_27_DIRECTION {in} \
+   CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_27_PULLUP {enabled} \
+   CONFIG.PCW_MIO_27_SLEW {fast} \
+   CONFIG.PCW_MIO_2_DIRECTION {inout} \
+   CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_2_PULLUP {disabled} \
+   CONFIG.PCW_MIO_2_SLEW {slow} \
+   CONFIG.PCW_MIO_3_DIRECTION {inout} \
+   CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_3_PULLUP {disabled} \
+   CONFIG.PCW_MIO_3_SLEW {slow} \
+   CONFIG.PCW_MIO_40_DIRECTION {inout} \
+   CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_40_PULLUP {enabled} \
+   CONFIG.PCW_MIO_40_SLEW {slow} \
+   CONFIG.PCW_MIO_41_DIRECTION {inout} \
+   CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_41_PULLUP {enabled} \
+   CONFIG.PCW_MIO_41_SLEW {slow} \
+   CONFIG.PCW_MIO_42_DIRECTION {in} \
+   CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_42_PULLUP {enabled} \
+   CONFIG.PCW_MIO_42_SLEW {slow} \
+   CONFIG.PCW_MIO_43_DIRECTION {out} \
+   CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_43_PULLUP {enabled} \
+   CONFIG.PCW_MIO_43_SLEW {slow} \
+   CONFIG.PCW_MIO_44_DIRECTION {out} \
+   CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_44_PULLUP {enabled} \
+   CONFIG.PCW_MIO_44_SLEW {slow} \
+   CONFIG.PCW_MIO_45_DIRECTION {in} \
+   CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_45_PULLUP {enabled} \
+   CONFIG.PCW_MIO_45_SLEW {slow} \
+   CONFIG.PCW_MIO_46_DIRECTION {inout} \
+   CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_46_PULLUP {enabled} \
+   CONFIG.PCW_MIO_46_SLEW {slow} \
+   CONFIG.PCW_MIO_47_DIRECTION {inout} \
+   CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_47_PULLUP {enabled} \
+   CONFIG.PCW_MIO_47_SLEW {slow} \
+   CONFIG.PCW_MIO_48_DIRECTION {inout} \
+   CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_48_PULLUP {enabled} \
+   CONFIG.PCW_MIO_48_SLEW {slow} \
+   CONFIG.PCW_MIO_49_DIRECTION {inout} \
+   CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_49_PULLUP {enabled} \
+   CONFIG.PCW_MIO_49_SLEW {slow} \
+   CONFIG.PCW_MIO_4_DIRECTION {inout} \
+   CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_4_PULLUP {disabled} \
+   CONFIG.PCW_MIO_4_SLEW {slow} \
+   CONFIG.PCW_MIO_50_DIRECTION {inout} \
+   CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_50_PULLUP {enabled} \
+   CONFIG.PCW_MIO_50_SLEW {slow} \
+   CONFIG.PCW_MIO_51_DIRECTION {inout} \
+   CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_51_PULLUP {enabled} \
+   CONFIG.PCW_MIO_51_SLEW {slow} \
+   CONFIG.PCW_MIO_52_DIRECTION {out} \
+   CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_52_PULLUP {enabled} \
+   CONFIG.PCW_MIO_52_SLEW {fast} \
+   CONFIG.PCW_MIO_53_DIRECTION {inout} \
+   CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_53_PULLUP {enabled} \
+   CONFIG.PCW_MIO_53_SLEW {fast} \
+   CONFIG.PCW_MIO_5_DIRECTION {inout} \
+   CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_5_PULLUP {disabled} \
+   CONFIG.PCW_MIO_5_SLEW {slow} \
+   CONFIG.PCW_MIO_6_DIRECTION {out} \
+   CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_6_PULLUP {disabled} \
+   CONFIG.PCW_MIO_6_SLEW {slow} \
+   CONFIG.PCW_MIO_TREE_PERIPHERALS {unassigned#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#unassigned#Quad SPI Flash#Quad SPI Flash#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 0#UART 0#UART 1#UART 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#Enet 0#Enet 0} \
+   CONFIG.PCW_MIO_TREE_SIGNALS {unassigned#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#unassigned#qspi0_io[3]/HOLD_B#qspi0_sclk#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#rx#tx#tx#rx#data[0]#cmd#clk#data[1]#data[2]#data[3]#mdc#mdio} \
+   CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
+   CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
+   CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
+   CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V} \
+   CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
+   CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {0} \
+   CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
+   CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
+   CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
+   CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
+   CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \
+   CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
+   CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
+   CONFIG.PCW_SD0_GRP_CD_ENABLE {0} \
+   CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
+   CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
+   CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_SD0_SD0_IO {<Select>} \
+   CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \
+   CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \
+   CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \
+   CONFIG.PCW_SD1_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_SD1_SD1_IO {MIO 46 .. 51} \
+   CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {10} \
+   CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
+   CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x2} \
+   CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_SPI0_GRP_SS0_ENABLE {1} \
+   CONFIG.PCW_SPI0_GRP_SS0_IO {EMIO} \
+   CONFIG.PCW_SPI0_GRP_SS1_ENABLE {1} \
+   CONFIG.PCW_SPI0_GRP_SS1_IO {EMIO} \
+   CONFIG.PCW_SPI0_GRP_SS2_ENABLE {1} \
+   CONFIG.PCW_SPI0_GRP_SS2_IO {EMIO} \
+   CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_SPI0_SPI0_IO {EMIO} \
+   CONFIG.PCW_SPI1_GRP_SS0_ENABLE {1} \
+   CONFIG.PCW_SPI1_GRP_SS0_IO {EMIO} \
+   CONFIG.PCW_SPI1_GRP_SS1_ENABLE {1} \
+   CONFIG.PCW_SPI1_GRP_SS1_IO {EMIO} \
+   CONFIG.PCW_SPI1_GRP_SS2_ENABLE {1} \
+   CONFIG.PCW_SPI1_GRP_SS2_IO {EMIO} \
+   CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_SPI1_SPI1_IO {EMIO} \
+   CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {6} \
+   CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \
+   CONFIG.PCW_SPI_PERIPHERAL_VALID {1} \
+   CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
+   CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_UART0_UART0_IO {MIO 42 .. 43} \
+   CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
+   CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_UART1_UART1_IO {MIO 44 .. 45} \
+   CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
+   CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
+   CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {266.666687} \
+   CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
+   CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \
+   CONFIG.PCW_UIPARAM_DDR_CL {7} \
+   CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
+   CONFIG.PCW_UIPARAM_DDR_CWL {6} \
+   CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
+   CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
+   CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
+   CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {266.6666666} \
+   CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-15E} \
+   CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
+   CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
+   CONFIG.PCW_UIPARAM_DDR_T_FAW {45.0} \
+   CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {36.0} \
+   CONFIG.PCW_UIPARAM_DDR_T_RC {49.5} \
+   CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
+   CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
+   CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {1} \
+   CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \
+   CONFIG.PCW_USE_M_AXI_GP0 {1} \
+   CONFIG.PCW_USE_M_AXI_GP1 {0} \
+   CONFIG.PCW_USE_S_AXI_HP0 {0} \
+ ] $processing_system7_0
+
+  # Create instance: rst_ps7_0_50M, and set properties
+  set rst_ps7_0_50M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_50M ]
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_ports REG_INF] [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA]
+  connect_bd_intf_net -intf_net axi_bram_ctrl_1_BRAM_PORTA [get_bd_intf_ports REG_INF1] [get_bd_intf_pins axi_bram_ctrl_1/BRAM_PORTA]
+  connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] [get_bd_intf_pins axi_smc/M00_AXI]
+  connect_bd_intf_net -intf_net axi_smc_M01_AXI [get_bd_intf_pins axi_bram_ctrl_1/S_AXI] [get_bd_intf_pins axi_smc/M01_AXI]
+  connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
+  connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
+  connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins axi_smc/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0]
+  connect_bd_intf_net -intf_net processing_system7_0_SPI_0 [get_bd_intf_ports SPI0] [get_bd_intf_pins processing_system7_0/SPI_0]
+  connect_bd_intf_net -intf_net processing_system7_0_SPI_1 [get_bd_intf_ports SPI1] [get_bd_intf_pins processing_system7_0/SPI_1]
+
+  # Create port connections
+  connect_bd_net -net GPIO_EMIO_gpio_i_1 [get_bd_ports GPIO_EMIO_gpio_i] [get_bd_pins processing_system7_0/GPIO_I]
+  connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FCLK_CLK0] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_bram_ctrl_1/s_axi_aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins rst_ps7_0_50M/slowest_sync_clk]
+  connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_ports FCLK_RESET0_N] [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_50M/ext_reset_in]
+  connect_bd_net -net processing_system7_0_GPIO_O [get_bd_ports GPIO_EMIO_gpio_o] [get_bd_pins processing_system7_0/GPIO_O]
+  connect_bd_net -net processing_system7_0_GPIO_T [get_bd_ports GPIO_EMIO_gpio_t] [get_bd_pins processing_system7_0/GPIO_T]
+  connect_bd_net -net rst_ps7_0_50M_peripheral_aresetn [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_bram_ctrl_1/s_axi_aresetn] [get_bd_pins axi_smc/aresetn] [get_bd_pins rst_ps7_0_50M/peripheral_aresetn]
+
+  # Create address segments
+  create_bd_addr_seg -range 0x00010000 -offset 0x40000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] SEG_axi_bram_ctrl_0_Mem0
+  create_bd_addr_seg -range 0x00002000 -offset 0x42000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_bram_ctrl_1/S_AXI/Mem0] SEG_axi_bram_ctrl_1_Mem0
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+