From 28307b12f6c5ffaf278b079e8af0a8d6aafc390b Mon Sep 17 00:00:00 2001 From: bowei Date: Wed, 19 Aug 2026 12:58:21 +0800 Subject: [PATCH] =?UTF-8?q?sync:=20SHANGHAI-U9=202026-08-19=20skills=5Fenv?= =?UTF-8?q?=20=E6=A8=A1=E6=9D=BF=E8=A1=A5=E5=9B=9E=E6=BC=82=E7=A7=BB?= =?UTF-8?q?=E7=9A=84=2012=20=E4=B8=AA=E9=94=AE=EF=BC=88LangGraph=20flow=20?= =?UTF-8?q?=E6=A0=B9=20/=20SDK=5FROOT=20/=20SMOD+VM=20=E6=AE=B5=EF=BC=8C?= =?UTF-8?q?=E5=87=AD=E6=8D=AE=E4=B8=80=E5=BE=8B=E5=8D=A0=E4=BD=8D=E7=AC=A6?= =?UTF-8?q?=EF=BC=89?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- smod_atsc_dev/SKILL.md | 2 +- tools-sync/references/skills_env_template.md | 24 ++++++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/smod_atsc_dev/SKILL.md b/smod_atsc_dev/SKILL.md index bf1122f..b567b07 100644 --- a/smod_atsc_dev/SKILL.md +++ b/smod_atsc_dev/SKILL.md @@ -26,7 +26,7 @@ FPGA 做 8VSB 调制 / DPD / AGC / TS 前处理，imx6 跑 `atsc_app`（配置 A | 项 | 值 | |---|---| -| 激励器 Vivado 工程 | `E:\Xilinx_design\smod\SMOD_ATSC\my_exciter\my_exciter.xpr`（top = `smod_top`，也是 **git 仓库根**） | +| 激励器 Vivado 工程 | `E:\Xilinx_design\smod\SMOD_ATSC\my_exciter\my_exciter.xpr`（top = `smod_top`，也是 **git 仓库根**；脚本取 `~\skills_env.md` 的 `SMOD_REPO_ROOT`） | | 打底 golden 工程 | `E:\Xilinx_design\smod\SMOD_ATSC\RU_golden\RU_golden.xpr`（top = `RU_golden_top`） | | FPGA / Flash | `xc7a200tfbg676-2` / Winbond **w25q128bv**（128 Mbit = 16 MB，SPIx1） | | Vivado | 见 `~\skills_env.md` 的 `VIVADO_ROOT`（其下 `bin\vivado.bat`）——路径因机器而异，不要写死盘符 | diff --git a/tools-sync/references/skills_env_template.md b/tools-sync/references/skills_env_template.md index b0f2d2d..3578557 100644 --- a/tools-sync/references/skills_env_template.md +++ b/tools-sync/references/skills_env_template.md @@ -24,11 +24,22 @@ CONDA_ROOT = C:\ProgramData\miniconda3 CONDA_LANGGRAPH_PYTHON = C:\Users\\.conda\envs\langgraph\python.exe ``` +## LangGraph 工作流仓库（各 flow skill 的 driver 从这里取项目根） + +``` +LANGGRAPH_DESIGN_ROOT = +SIM_RTL_FLOW_ROOT = {LANGGRAPH_DESIGN_ROOT}\sim-rtl-flow +ZYNQ_IMX6_FLOW_ROOT = {LANGGRAPH_DESIGN_ROOT}\zynq-imx6-flow +FPGA_IMX6_FLOW_ROOT = {LANGGRAPH_DESIGN_ROOT}\FPGA-imx6-flow +FPGA_GOLDENREF_ROOT = {LANGGRAPH_DESIGN_ROOT} pga-goldenref-flow +``` + ## EDA / 硬件工具 ``` VIVADO_ROOT = VIVADO_PATH = <上一行 + \bin\vivado.bat> +SDK_ROOT = KICAD_PYTHONPATH = C:\Program Files\KiCad\10.0\bin\Lib\site-packages MATLAB_ROOT = MATLAB_AGENTIC_ROOT = C:\Users\\.matlab\agentic-toolkits @@ -42,6 +53,19 @@ N9320B_HOST = 192.168.1.147 # Keysight N9320B 频谱仪 SMOD_BOARD_IP = 192.168.1.143 # SMOD 板（ATSC 激励器远程升级） ``` +## SMOD imx6 设备与交叉编译 VM（smod_atsc_dev / fpga_update 使用） + +``` +SMOD_REPO_ROOT = +SMOD_SSH_USER = root # imx6 SSH/网页登录名（老 dropbear） +SMOD_SSH_PASS = <填写> +SMOD_WEB_USER = <网页 Remote Update 账号，与 SSH 不同> +SMOD_WEB_PASS = <填写> +CROSS_VM_HOST = <交叉编译 VM 的 IP —— 随 VMware 网段变化，必须实测> +CROSS_VM_USER = <填写> +CROSS_VM_PASS = <填写> +``` + ## MCP 注册配置（真源：MCP_DESIGN_ROOT\mcp_list.md） ```