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Myfro9
2026-05-09 01:12:34 -05:00
commit 61b4731d06
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{
"eval_id": 1,
"eval_name": "axis-fifo-handshake-sim",
"prompt": "我有一个 AXI-Stream FIFO 模块,接口如下:input clk, input rst_n, input [7:0] s_tdata, input s_tvalid, output s_tready, output [7:0] m_tdata, output m_tvalid, input m_tready, output [3:0] fill_count。请帮我生成 testbench,模拟正常的 tvalid/tready 握手时序,用批处理模式在 Vivado 中运行仿真。",
"assertions": []
}