sync: HP_BOWEI 2026-10-15
This commit is contained in:
Myfro9
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"""原理图验收：ERC + 网表器件数 + 子电路画法检查。
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python -m schgen.check <根图.kicad_sch> [--expect-refs 位号清单文件或逗号串]
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四件事：
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1. kicad-cli ERC（错误/警告条数与分类）；
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2. 网表里的器件数与网络数——判断一页有没有真被 KiCad 读进去**看这个**，
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不要看 ERC 的 0（G-0018：一页解析失败时 ERC 照样 0 条）；位号重名会被静默合并（G-0028），
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给了 --expect-refs 就逐个比对缺了哪些；
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3. 子电路画法（G-0035/G-0037）：
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A 级：两脚件两端都只挂标签、连通域里没有别的元件引脚——看不出它串在哪/退耦谁；
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B 级：连通关系（可穿过其它无源件）到不了任何芯片/连接器引脚，且离最近的芯片/连接器
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引脚也超过 NEAR mm——说明它没画在所服务的子电路里。
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连通性含丁字口（端点落在另一条线中段，G-0036）。引脚坐标取自图纸自带的 lib_symbols，
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不依赖库表。
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C 级：三条以上线端（或线端+引脚）汇于一点却没画接点——电气连通但图面看不出（G-0036 的反面）。
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4. 封装：每个器件的封装文件存在，符号引脚号与焊盘号一一对应。
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"""
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import io
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import math
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import os
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import re
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import subprocess
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import sys
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import tempfile
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import xml.etree.ElementTree as ET
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from .env import kicad_cli
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from .kicad_lib import balanced, rot_pt
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TOL = 0.02
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NEAR = 55.0
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TWO_PIN_PREFIX = ("R", "C", "L", "FB", "JP", "D")
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def sexp(text):
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toks = re.findall(r'\(|\)|"(?:[^"\\]|\\.)*"|[^\s()]+', text)
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stack, cur = [], []
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for tk in toks:
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if tk == '(':
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stack.append(cur); cur = []
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elif tk == ')':
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done = cur; cur = stack.pop(); cur.append(done)
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else:
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cur.append(tk[1:-1].replace('\\"', '"') if tk.startswith('"') else tk)
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return cur
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def find(node, name):
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return [c for c in node if isinstance(c, list) and c and c[0] == name]
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def at(node):
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a = find(node, "at")
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if not a:
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return None
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v = a[0]
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return (float(v[1]), float(v[2]), float(v[3]) if len(v) > 3 else 0.0)
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def embedded_pins(text):
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"""{lib_id: {unit: {pin: (dx, dy)}}}，取自 .kicad_sch 的 lib_symbols。"""
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i = text.find("(lib_symbols")
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if i < 0:
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return {}
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ls = balanced(text, i)
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res = {}
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for m in re.finditer(r'\n\s*\(symbol "([^"]+:[^"]+)"', ls):
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blk = balanced(ls, m.start() + ls[m.start():].find("("))
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lid = m.group(1)
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units = {}
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for sm in re.finditer(r'\(symbol "[^"]*_(\d+)_\d+"', blk):
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u = int(sm.group(1))
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sub = balanced(blk, sm.start())
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for pm in re.finditer(r'\(pin\s+\S+\s+\S+\s*\(at\s+([-\d.]+)\s+([-\d.]+)', sub):
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seg = sub[pm.end():pm.end() + 400]
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nm = re.search(r'\(number "([^"]*)"', seg)
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if nm:
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units.setdefault(u, {})[nm.group(1)] = (float(pm.group(1)), float(pm.group(2)))
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res[lid] = units
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return res
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class DS:
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def __init__(self):
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self.p = {}
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def find(self, k):
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self.p.setdefault(k, k)
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while self.p[k] != k:
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self.p[k] = self.p[self.p[k]]
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k = self.p[k]
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return k
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def union(self, a, b):
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ra, rb = self.find(a), self.find(b)
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if ra != rb:
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self.p[ra] = rb
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def key(x, y):
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return (round(x / TOL), round(y / TOL))
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def on_seg(px, py, x1, y1, x2, y2):
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if abs((x2 - x1) * (py - y1) - (y2 - y1) * (px - x1)) > 0.05:
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return False
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return (min(x1, x2) - TOL <= px <= max(x1, x2) + TOL
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and min(y1, y2) - TOL <= py <= max(y1, y2) + TOL)
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def subckt(path):
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text = io.open(path, encoding="utf-8").read()
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lib = embedded_pins(text)
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root = sexp(text)[0]
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wires = []
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for w in find(root, "wire"):
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xy = [(float(p[1]), float(p[2])) for p in find(find(w, "pts")[0], "xy")]
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if len(xy) == 2:
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wires.append((xy[0][0], xy[0][1], xy[1][0], xy[1][1]))
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labels = []
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for kind in ("global_label", "hierarchical_label", "label"):
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for lb in find(root, kind):
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p = at(lb)
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if p:
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labels.append((p[0], p[1], lb[1]))
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comps = []
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for s in find(root, "symbol"):
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lid = find(s, "lib_id")
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pos = at(s)
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if not lid or pos is None:
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continue
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ref = ""
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for pr in find(s, "property"):
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if len(pr) > 2 and pr[1] == "Reference":
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ref = pr[2]
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un = find(s, "unit")
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u = int(un[0][1]) if un else 1
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units = lib.get(lid[0][1], {})
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pins = dict(units.get(0, {}))
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pins.update(units.get(u, {}))
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ab = {}
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for n, (dx, dy) in pins.items():
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rx, ry = rot_pt(dx, dy, pos[2])
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ab[n] = (pos[0] + rx, pos[1] - ry)
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comps.append(dict(ref=ref, pins=ab))
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ds = DS()
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nodes = [(px, py, "pin", "%s.%s" % (c["ref"], n)) for c in comps for n, (px, py) in c["pins"].items()]
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nodes += [(x, y, "label", nm) for x, y, nm in labels]
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for (x1, y1, x2, y2) in wires:
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ds.union(key(x1, y1), key(x2, y2))
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for w1 in wires:
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for w in wires:
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if w is w1:
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continue
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for (ex, ey) in ((w1[0], w1[1]), (w1[2], w1[3])):
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if on_seg(ex, ey, *w):
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ds.union(key(ex, ey), key(w[0], w[1]))
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for (px, py, _, _) in nodes:
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for w in wires:
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if on_seg(px, py, *w):
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ds.union(key(px, py), key(w[0], w[1]))
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groups = {}
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for (px, py, kind, nm) in nodes:
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groups.setdefault(ds.find(key(px, py)), []).append((kind, nm))
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def is_passive(c):
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r = c["ref"]
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return r and not r.startswith("#") and r.startswith(TWO_PIN_PREFIX) and len(c["pins"]) == 2
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bad_a = []
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for c in comps:
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if not is_passive(c):
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continue
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ends = []
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for n, (px, py) in c["pins"].items():
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g = groups.get(ds.find(key(px, py)), [])
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others = [m for m in g if m[0] == "pin" and not m[1].startswith(c["ref"] + ".")
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and not m[1].startswith("#")]
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ends.append((len(others), any(m[0] == "label" for m in g)))
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if all(n == 0 and lb for n, lb in ends):
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bad_a.append(c["ref"])
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anchors, apts = set(), []
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for c in comps:
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if c["ref"] and not c["ref"].startswith("#") and not is_passive(c):
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for n, pt in c["pins"].items():
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anchors.add("%s.%s" % (c["ref"], n)); apts.append(pt)
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du = DS()
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passives = [c for c in comps if is_passive(c)]
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for c in passives:
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rs = [ds.find(key(px, py)) for px, py in c["pins"].values()]
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du.union(rs[0], rs[1])
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live = {du.find(r) for r, mem in groups.items() if any(k == "pin" and nm in anchors for k, nm in mem)}
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bad_b = []
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for c in passives:
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ok = any(du.find(ds.find(key(px, py))) in live for px, py in c["pins"].values())
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if not ok:
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ok = any(math.hypot(px - ax, py - ay) <= NEAR
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for px, py in c["pins"].values() for ax, ay in apts)
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if not ok:
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bad_b.append(c["ref"])
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# C 级：三条及以上线端（或线端+引脚）汇在一点却没有接点。KiCad 电气上算连通，
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# 但图面上看不出是连上的（DVBS2_dmod 第 3 轮 d20 抓到过两处）
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jset = {key(float(j[1][1]), float(j[1][2])) for j in
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[(x, find(x, "at")[0]) for x in find(root, "junction")]}
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ends = {}
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for (x1, y1, x2, y2) in wires:
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for p in ((x1, y1), (x2, y2)):
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ends.setdefault(key(*p), []).append(p)
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pinpts = {key(px, py) for c in comps for (px, py) in c["pins"].values()}
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bad_c = []
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for k, pts in ends.items():
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n = len(pts) + (1 if k in pinpts else 0)
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mid = sum(1 for w in wires if on_seg(pts[0][0], pts[0][1], *w)
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and key(w[0], w[1]) != k and key(w[2], w[3]) != k)
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if n + 2 * mid >= 3 and k not in jset:
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bad_c.append("(%.2f,%.2f)" % pts[0])
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return len(comps), bad_a, bad_b, bad_c
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def erc(root):
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out = os.path.join(tempfile.mkdtemp(prefix="kf_erc_"), "erc.rpt")
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subprocess.run([kicad_cli(), "sch", "erc", "--severity-error", "--severity-warning",
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"-o", out, root], capture_output=True)
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t = io.open(out, encoding="utf-8", errors="replace").read() if os.path.exists(out) else ""
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kinds = {}
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for m in re.finditer(r'\[(\w+)\]:\s*(.*)', t):
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kinds.setdefault(m.group(1), []).append(m.group(2))
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return t, kinds
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def netlist(root):
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out = os.path.join(tempfile.mkdtemp(prefix="kf_net_"), "n.xml")
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subprocess.run([kicad_cli(), "sch", "export", "netlist", "--format", "kicadxml", "-o", out, root],
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capture_output=True)
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r = ET.parse(out).getroot()
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comps = {c.get("ref"): (c.findtext("value"), c.findtext("footprint")) for c in r.iter("comp")}
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nets = {}
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for n in r.iter("net"):
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nets[n.get("name")] = [(x.get("ref"), x.get("pin")) for x in n.iter("node")]
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return comps, nets, out
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def _fp_dirs(prj_dir):
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"""库名 -> .pretty 目录：工程 fp-lib-table 优先，其余按 KiCad 自带库目录找。"""
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from .env import kicad_footprint_dir
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d = {}
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t = os.path.join(prj_dir, "fp-lib-table")
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if os.path.exists(t):
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for m in re.finditer(r'\(name "([^"]+)"\).*?\(uri "([^"]+)"\)', io.open(t, encoding="utf-8").read()):
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d[m.group(1)] = m.group(2).replace("${KIPRJMOD}", prj_dir)
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return d, kicad_footprint_dir()
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def fpcheck(net_xml, prj_dir):
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"""每个器件：封装文件存在；符号引脚号 ⊆ 焊盘号；有编号的焊盘都有对应引脚（否则它挂不上网）。
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返回问题清单。"""
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r = ET.parse(net_xml).getroot()
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pins = {}
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for lp in r.iter("libpart"):
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k = (lp.get("lib"), lp.get("part"))
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pins[k] = {p.get("num") for p in lp.iter("pin")}
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dirs, share = _fp_dirs(prj_dir)
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bad = []
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for c in r.iter("comp"):
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ref, fp = c.get("ref"), c.findtext("footprint") or ""
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if ref.startswith("#"):
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continue
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if not fp:
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bad.append("%s 没有封装" % ref)
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continue
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lib, name = fp.split(":", 1)
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base = dirs.get(lib) or os.path.join(share, lib + ".pretty")
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f = os.path.join(base, name + ".kicad_mod")
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if not os.path.exists(f):
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bad.append("%s 的封装 %s 找不到（%s）" % (ref, fp, f))
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continue
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pads = set(re.findall(r'\(pad\s+"([^"]+)"', io.open(f, encoding="utf-8").read()))
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ls = c.find("libsource")
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sp = pins.get((ls.get("lib"), ls.get("part")), set()) if ls is not None else set()
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miss = sorted(sp - pads)
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extra = sorted(pads - sp)
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if miss:
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bad.append("%s(%s) 符号引脚在封装里没有：%s" % (ref, name, ",".join(miss)))
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if extra and sp:
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bad.append("%s(%s) 焊盘没有对应符号引脚：%s" % (ref, name, ",".join(extra)))
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return bad
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def main(argv):
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root = argv[0]
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expect = None
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if "--expect-refs" in argv:
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v = argv[argv.index("--expect-refs") + 1]
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expect = set((io.open(v).read() if os.path.exists(v) else v).replace("\n", ",").split(","))
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expect.discard("")
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sys.stdout.reconfigure(encoding="utf-8")
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rc = 0
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rpt, kinds = erc(root)
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print("ERC:", ", ".join("%s x%d" % (k, len(v)) for k, v in sorted(kinds.items())) or "0 条")
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comps, nets, npath = netlist(root)
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real = {k: v for k, v in comps.items() if not k.startswith("#")}
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print("网表: 器件 %d 个，网络 %d 条 (%s)" % (len(real), len(nets), npath))
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fb = fpcheck(npath, os.path.dirname(os.path.abspath(root)))
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print("封装: %s" % ("全部 %d 个器件有封装且引脚/焊盘一一对应" % len(real) if not fb
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else "%d 处问题" % len(fb)))
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for b in fb:
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print(" !! " + b)
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if fb:
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rc = 1
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if expect is not None:
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miss = sorted(expect - set(real))
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if miss:
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rc = 1
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print(" !! 网表里缺: %s" % " ".join(miss))
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d = os.path.dirname(os.path.abspath(root))
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files = sorted(set(re.findall(r'\(property "Sheetfile" "([^"]+)"', io.open(root, encoding="utf-8").read())))
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for f in files:
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n, a, b, cj = subckt(os.path.join(d, f))
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flag = "OK " if not a and not b and not cj else "!! "
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if a or b or cj:
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rc = 1
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print("%s%-28s 元件 %3d A:两端只挂标签 %d B:没进子电路 %d C:丁字口缺接点 %d %s"
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% (flag, f, n, len(a), len(b), len(cj), " ".join(sorted(set(a) | set(b)) + cj)))
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return rc
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if __name__ == "__main__":
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sys.exit(main(sys.argv[1:]))
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Reference in New Issue
Block a user