sync: HP_BOWEI 2026-10-15
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Myfro9
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"""n101：从原理图网表确定性地建 PCB（封装 + 网络，封装按页排在"停车场"里），再逐焊盘验收。
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**必须用 KiCad 自带的 python 跑**（要 pcbnew）：
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<KICAD_PYTHON> -m schgen.pcbimport <根图.kicad_sch> <输出.kicad_pcb> [--layers 2|4]
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为什么不用 kicad MCP 的 sync_schematic_to_board（G-0039）：它自报 success，实际
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ipots 载板写出 338 个封装（应 327）、191 个网（应 426）；DVBS2_dmod 上 26 个网（应 60），
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还冒出一个叫 PWR_FLAG 的网、U4 一串焊盘没网——所有 "Net-(...)" 无名网全丢。
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kicad-cli 没有"从原理图更新 PCB"子命令，GUI 的 F8 要人点，所以这里自己建。
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pcbnew swig 的坑（G-0038）：FootprintLoad() 便捷函数坏的，走 PCB_IO_KICAD_SEXPR；
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对 BOARD Remove() 过 FOOTPRINT 后 swig 类型注册会坏，所以**每次都建一块新板**，
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不做"载入旧板再删"。已有板子会被覆盖——布局开始之后就别再跑它了。
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"""
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import io
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import os
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import re
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import subprocess
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import sys
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import tempfile
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import xml.etree.ElementTree as ET
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import pcbnew
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from .env import kicad_cli, kicad_footprint_dir
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GAP, SHEET_GAP, FIELD_W = 2.0, 12.0, 250.0
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def mm(v):
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return pcbnew.FromMM(float(v))
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def netlist(sch):
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out = os.path.join(tempfile.mkdtemp(prefix="kf_pcb_"), "n.xml")
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subprocess.check_call([kicad_cli(), "sch", "export", "netlist", "--format", "kicadxml",
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"-o", out, sch], stdout=subprocess.DEVNULL, stderr=subprocess.DEVNULL)
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r = ET.parse(out).getroot()
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comps = []
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for c in r.iter("comp"):
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sh = c.find("sheetpath")
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flds = {f.get("name"): (f.text or "") for f in c.iter("field")}
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props = {pr.get("name") for pr in c.iter("property")}
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comps.append(dict(ref=c.get("ref"), val=c.findtext("value") or "", fields=flds,
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dnp="dnp" in props, no_bom="exclude_from_bom" in props,
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fp=c.findtext("footprint") or "",
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sheet=sh.get("names") if sh is not None else "",
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path=(sh.get("tstamps") if sh is not None else "") + (c.findtext("tstamps") or "")))
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nets = [(n.get("name"), [(x.get("ref"), x.get("pin")) for x in n.iter("node")])
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for n in r.iter("net")]
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return comps, nets
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def fp_dirs(prj_dir):
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d = {}
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t = os.path.join(prj_dir, "fp-lib-table")
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if os.path.exists(t):
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for m in re.finditer(r'\(name "([^"]+)"\).*?\(uri "([^"]+)"\)', io.open(t, encoding="utf-8").read()):
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d[m.group(1)] = m.group(2).replace("${KIPRJMOD}", prj_dir)
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return d
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_IO = pcbnew.PCB_IO_KICAD_SEXPR()
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def load_fp(libdir, name):
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fp = _IO.FootprintLoad(libdir, name)
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if fp is not None and not hasattr(fp, "SetReference"):
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fp = pcbnew.Cast_to_FOOTPRINT(fp)
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return fp
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def fp_box(fp):
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"""占地与包围盒相对原点的偏移——原点不一定在中心（连接器常在 1 脚）。"""
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fp.SetPosition(pcbnew.VECTOR2I(0, 0))
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try:
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bb = fp.GetBoundingBox(False, False)
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except TypeError:
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bb = fp.GetBoundingBox()
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return (pcbnew.ToMM(bb.GetWidth()), pcbnew.ToMM(bb.GetHeight()),
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pcbnew.ToMM(bb.GetX()), pcbnew.ToMM(bb.GetY()))
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def note(board, s, x, y, size=2.0):
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t = pcbnew.PCB_TEXT(board)
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t.SetText(s)
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t.SetPosition(pcbnew.VECTOR2I(mm(x), mm(y)))
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t.SetLayer(pcbnew.Cmts_User)
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t.SetTextSize(pcbnew.VECTOR2I(mm(size), mm(size)))
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t.SetTextThickness(mm(size / 6.0))
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t.SetHorizJustify(pcbnew.GR_TEXT_H_ALIGN_LEFT)
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board.Add(t)
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def build(sch, pcb, layers=2, x0=20.0, y0=20.0):
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prj_dir = os.path.dirname(os.path.abspath(sch))
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dirs = fp_dirs(prj_dir)
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share = kicad_footprint_dir()
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comps, nets = netlist(sch)
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board = pcbnew.CreateEmptyBoard()
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board.SetCopperLayerCount(layers)
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placed, y = {}, y0
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for sheet in sorted(set(c["sheet"] for c in comps)):
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grp = sorted((c for c in comps if c["sheet"] == sheet), key=lambda c: (c["fp"], c["ref"]))
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note(board, "%s (%d)" % (sheet, len(grp)), x0, y - 4)
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x, rowh = x0, 0.0
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for c in grp:
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if not c["fp"]:
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raise SystemExit("%s 没有封装" % c["ref"])
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lib, name = c["fp"].split(":", 1)
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fp = load_fp(dirs.get(lib) or os.path.join(share, lib + ".pretty"), name)
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if fp is None:
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raise SystemExit("载入不了封装 %s（%s）" % (c["fp"], c["ref"]))
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fp.SetFPID(pcbnew.LIB_ID(lib, name)) # 板上必须是 "库:名"，否则以后无法从库更新
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fp.SetReference(c["ref"])
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fp.SetValue(c["val"])
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# 原理图上的附加字段（MPN 等）也写进封装，否则 DRC 原理图对照报 Missing symbol field
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for k, v in c.get("fields", {}).items():
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if k not in ("Reference", "Value", "Footprint", "Datasheet") and v:
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fp.SetField(k, v)
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fd = fp.GetField(k)
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if fd is not None:
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fd.SetVisible(False) # 新建字段默认可见，会被印成丝印
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# 不贴(DNP)/不进 BOM 跟着原理图走，否则 DRC 报 footprint_symbol_mismatch
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fp.SetDNP(c.get("dnp", False))
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fp.SetExcludedFromBOM(c.get("no_bom", False))
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if c["path"]:
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try:
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fp.SetPath(pcbnew.KIID_PATH(c["path"])) # F8 靠它认同一个器件
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except Exception:
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pass
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board.Add(fp)
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w, h, ox, oy = fp_box(fp)
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if x > x0 and x + w > x0 + FIELD_W:
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x, y, rowh = x0, y + rowh + GAP, 0.0
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fp.SetPosition(pcbnew.VECTOR2I(mm(x - ox), mm(y - oy)))
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placed[c["ref"]] = fp
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x += w + GAP
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rowh = max(rowh, h)
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y += rowh + SHEET_GAP
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miss = []
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for name, nodes in nets:
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ni = pcbnew.NETINFO_ITEM(board, name)
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board.Add(ni)
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for ref, pin in nodes:
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fp = placed.get(ref)
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pads = [p for p in fp.Pads() if p.GetNumber() == pin] if fp else []
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if not pads: # 同号多焊盘（散热盘/安装脚）要全挂上
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miss.append("%s.%s" % (ref, pin))
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for pad in pads:
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pad.SetNet(ni)
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board.BuildListOfNets()
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pcbnew.SaveBoard(pcb, board)
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print("写出 %s：封装 %d，网 %d" % (pcb, len(placed), len(nets)))
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if miss:
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print("!! 连不上的节点 %d 个：%s" % (len(miss), " ".join(miss[:20])))
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return comps, nets, miss
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def verify(sch, pcb):
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"""独立验收：重新载入板子，按网表逐焊盘比对（G-0039：别信导入工具的自报）。"""
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comps, nets = netlist(sch)
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b = pcbnew.LoadBoard(pcb)
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fps = {f.GetReference(): f for f in b.GetFootprints()}
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bad = []
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want = {c["ref"] for c in comps}
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if set(fps) != want:
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bad.append("器件不一致：多 %s 少 %s" % (sorted(set(fps) - want), sorted(want - set(fps))))
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for c in comps:
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f = fps.get(c["ref"])
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if f and f.GetFPIDAsString() != c["fp"]:
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bad.append("%s 封装 %s != %s" % (c["ref"], f.GetFPIDAsString(), c["fp"]))
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pinnet = {(r, p): n for n, nodes in nets for r, p in nodes}
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npads = 0
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for ref, f in fps.items():
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for pad in f.Pads():
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num = pad.GetNumber()
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if not num:
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continue # 无编号的机械孔
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npads += 1
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exp = pinnet.get((ref, num))
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got = str(pad.GetNetname())
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if exp is None and got:
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bad.append("%s.%s 板上挂了 %s，网表里没有" % (ref, num, got))
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elif exp is not None and got != exp:
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bad.append("%s.%s 应为 %s，板上是 %r" % (ref, num, exp, got))
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boardnets = {str(n) for n in b.GetNetsByName().keys() if str(n)} # swig 给的是 wxString
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wantnets = {n for n, _ in nets}
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if boardnets != wantnets:
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bad.append("网名不一致：多 %s 少 %s" % (sorted(boardnets - wantnets)[:10],
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sorted(wantnets - boardnets)[:10]))
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print("验收：器件 %d/%d，网 %d/%d，有编号焊盘 %d，问题 %d"
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% (len(fps), len(want), len(boardnets), len(wantnets), npads, len(bad)))
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for x in bad[:30]:
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print(" !! " + x)
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return bad
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def main(argv):
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sch, pcb = argv[0], argv[1]
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layers = int(argv[argv.index("--layers") + 1]) if "--layers" in argv else 2
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_, _, miss = build(sch, pcb, layers)
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bad = verify(sch, pcb)
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return 1 if (miss or bad) else 0
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if __name__ == "__main__":
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sys.stdout.reconfigure(encoding="utf-8")
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sys.exit(main(sys.argv[1:]))
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