sync: SHANGHAI-U9 2026-10-28

2026-10-28 14:52:42 +08:00
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+{
+  "schema_version": 1,
+  "board_id": "ipots",
+  "profile_revision": 1,
+  "profile_status": "build-only; NOT deployment-validated (G4-G6 not run)",
+  "soc": "XC7Z020CLG400-2",
+  "boot": {
+    "mode_straps": "SW1 2-pos switch -> MIO4/MIO5 (ON=GND); documented JTAG=ON/ON, QSPI=ON/OFF, SD=OFF/OFF",
+    "mode_straps_status": "UNKNOWN: decode vs Zynq BOOT_MODE and current position unverified; verify by 0xF800025C readback at G4",
+    "device": "qspi",
+    "qspi_topology": "single",
+    "composition": ["fsbl", "u-boot"]
+  },
+  "qspi": {
+    "family": "W25Q256FV",
+    "validated_probe": "UNKNOWN",
+    "total_bytes": 33554432,
+    "planned_erase_bytes": 65536,
+    "erase_bytes_status": "UNKNOWN until U-Boot sf probe; layout aligned to 64 KiB",
+    "reported_page_bytes": "UNKNOWN",
+    "addressing_above_16MiB": "UNKNOWN: kernel region crosses 0x01000000; must pass full readback at G5",
+    "mio": "1..6 single SS, bank0 3.3 V, no feedback clock",
+    "partitions": [
+      {"name": "boot", "offset": "0x00000000", "size": "0x00400000"},
+      {"name": "bootenv", "offset": "0x00400000", "size": "0x00040000"},
+      {"name": "kernel", "offset": "0x00440000", "size": "0x01800000"},
+      {"name": "update", "offset": "0x01C40000", "size": "0x003C0000"}
+    ]
+  },
+  "ddr": {
+    "type": "DDR3",
+    "hdf_part": "MT41K256M16 RE-15E (substitute model)",
+    "board_part": "NT5CC256M16",
+    "bytes": 1073741824,
+    "status": "UNKNOWN: substitute DDR parameters must be validated at first boot (G4/G6)"
+  },
+  "console": {"uart": "ps7_uart0", "mio": [14, 15], "baud": 115200, "connector": "J601", "host_adapter": "UNKNOWN"},
+  "storage": {
+    "kind": "soldered-emmc",
+    "part": "KLM8G1GETF 8 GB",
+    "controller": "sd1",
+    "data_mio": [46, 47, 48, 49, 50, 51],
+    "card_detect": "none",
+    "bus_width": 4,
+    "max_frequency_hz": 25000000,
+    "max_frequency_status": "UNKNOWN: conservative choice, not measured",
+    "card_voltage_v": "UNKNOWN",
+    "ps_voltage_v": 1.8,
+    "has_write_protect": false,
+    "sd0": "disabled in HDF (no socket)"
+  },
+  "ethernet": {
+    "controller": "gem0",
+    "mio": "16..27, MDIO 52..53",
+    "phy": "YT8521SC-CA",
+    "mdio_address": 3,
+    "phy_mode": "rgmii-id",
+    "phy_mode_status": "UNKNOWN: Linux 4.14 has no Motorcomm driver; generic PHY used, PHY delays rely on straps",
+    "phy_reset": "PS_POR_B"
+  },
+  "recovery": {"method": "JTAG J600 (IDC14 2.0 mm) + SW1 JTAG mode", "status": "UNKNOWN: cable, power control and JTAG boot not proven"}
+}
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+# ipots board reference (ipots_tunerX10 carrier + ZYNQ7020 core board 2V5)
+
+Status: **build-only profile, revision 1 (2026-10-27).** Created for ipots_recX10 (prjID `ipots-recx10`) from
+`Notes/Task-PR00.md` §8.5 (carrier/core-board schematic facts), the Vivado 2018.1 HDF
+`ipots_recX10_xc7z020_v0.1_d20261027_b0002.hdf` (design_1.hwh) and the first PetaLinux 2018.1 build
+(`Notes/auto/20261027-1705-rx-pl-ps-build/R02-T5-*`). **G0 hardware items and G4-G6 have never been run on this
+board.** Every item marked **UNKNOWN** below must be measured at the named gate before it is used for an erase or
+write; placeholders are not deployment permission. Never borrow HJX9009 or emv9.3 constants.
+
+Use [ipots-profile.json](ipots-profile.json) as the `qspi_cache.py --board-profile` input, not this document.
+
+## Identity
+
+| Item | Value | Evidence / status |
+|---|---|---|
+| Board | ipots_tunerX10 carrier (PCB SHA 0d3edf1f..., full SHA/serial **UNKNOWN**) + Qimingxing ZYNQ7020 core board 2V5 | Task-PR00 §8.5 |
+| SoC | XC7Z020CLG400-2 | HDF |
+| Hardware handoff | Vivado 2018.1 `.hdf`; must contain PS7 + M_AXI_GP0 (`axil_regs_0` at 0x43C00000/64 KiB) and SD0 disabled. The old NERC baseline `carrier_current_0020.hdf` (GP0=0, SD0 on) is not valid input | first build input: HDF b0002, sha256 `4f600081244d0203...dd65b82b` (exact value in each delivery's build_inputs.json) |
+| Tools | PetaLinux / Vivado / SDK 2018.1; no migration authorised | Task-PR00 §3.1 |
+| Transition role | QSPI initramfs rescue Linux: network, eMMC diagnosis, preparing the production system | Task-PR00 §8.5 |
+| Production storage | soldered eMMC KLM8G1GETF 8 GB on PS SD1 (petalinux-emmc stage) | core board p9 |
+| DDR | DDR3 1 GiB (32-bit, 2 x 4 Gbit x16). HDF uses the **substitute** model `MT41K256M16 RE-15E`; the board carries NT5CC256M16. Stability **UNKNOWN** -> first boot (G4) + memory test (G6) | HDF, Task-PR00 §13#5 |
+
+## Boot and QSPI
+
+| Item | Value | Evidence / status |
+|---|---|---|
+| Boot straps | SW1 two-position switch -> MIO4 (QSPI_D2) / MIO5 (QSPI_D3), 10 K pull-up + 20 K series, ON = GND. Documented: JTAG = ON/ON, QSPI = ON/OFF, SD = OFF/OFF | bmem ipots-tunerx10 D-0014 via Task-PR00 §8.5. Decode against Zynq BOOT_MODE and the current switch position **UNKNOWN** -> read `md.b 0xF800025C` at G4 |
+| QSPI part | Winbond W25Q256FV, 32 MiB, single chip, single SS, x4, MIO1..6, bank0 3.3 V, no feedback clock, 200 MHz ref | core board p9; HDF `PCW_QSPI_*` |
+| Geometry | total 33554432 B. Erase / page size **UNKNOWN** until U-Boot `sf probe` (datasheet: 4 KiB sector / 64 KiB block, 256 B page). Layout is aligned to 64 KiB | G4 `sf probe` must be recorded before any erase |
+| > 16 MiB addressing | W25Q256 needs 4-byte addressing or a bank register. U-Boot 2018.01 / Linux 4.14 support on this board **UNKNOWN**. The `kernel` region crosses 0x01000000, so G5 full readback is the deciding test; BOOT.BIN is kept far below 16 MiB | new risk vs. HJX9009 |
+| BOOT.BIN | FSBL + U-Boot only; no PL bitstream (PL is loaded by Linux FPGA manager), no image.ub | Task-PR00 §8.4/8.5 |
+| Recovery | JTAG J600 (IDC14 2.0 mm) + SW1 JTAG mode; cable type, host adapter and power control **UNKNOWN**; JTAG FSBL/U-Boot boot never demonstrated. **Stop before the first QSPI erase until this is proven** | Task-PR00 §8.5 |
+
+Planned transition layout (revision 1; also in `flash_layout.json` of each delivery):
+
+| Region | Offset | Size | End (excl.) | Content |
+|---|---:|---:|---:|---|
+| boot | `0x00000000` | `0x00400000` (4 MiB) | `0x00400000` | BOOT.BIN (FSBL + U-Boot) |
+| bootenv | `0x00400000` | `0x00040000` (256 KiB) | `0x00440000` | U-Boot environment |
+| kernel | `0x00440000` | `0x01800000` (24 MiB) | `0x01C40000` | rescue FIT `image.ub.qspi` (kernel + DTB + initramfs) |
+| update | `0x01C40000` | `0x003C0000` (3.75 MiB) | `0x02000000` | reserved; purpose not yet assigned (above 16 MiB, so not BootROM-searchable) |
+
+RAM: U-Boot `netstart`/`loadaddr` 0x10000000 (PetaLinux `NETBOOT_OFFSET`), `CONFIG_SYS_BOOTM_LEN 0x08000000`. Calculate the
+real image read/erase length per build; never reuse an old length.
+
+## Console and networking
+
+| Item | Value | Evidence / status |
+|---|---|---|
+| UART | PS UART0 MIO14/15 -> carrier J601 (XH2.54-3P GND/RXD/TXD), 3.3 V, 115200 (`ttyPS0`) | HDF, Task-PR00 §8.5 |
+| Host COM adapter | **UNKNOWN**. Host COM3/COM4 belong to the SMOD relays, not this board | G0 on site |
+| Ethernet | PS GEM0 MIO16..27, MDIO MIO52/53, 1000 Mbit/s | HDF |
+| PHY | Motorcomm YT8521SC-CA at MDIO address 3, RGMII 1.8 V, reset tied to PS_POR_B | core board p11 |
+| PHY driver / delays | Linux 4.14 (PetaLinux 2018.1) has **no Motorcomm driver**; build uses the generic PHY with `phy-mode = "rgmii-id"` (core-board BSP practice per Task-PR00 §8.3). Actual RGMII delay behaviour (strap defaults) **UNKNOWN** -> G6 ping/TFTP/iperf | |
+| MAC | build uses locally administered `02:52:10:00:00:01`; one board only. Change per board if more than one is on a LAN | build choice |
+| Live addresses / TFTP | discover every run; VM build host is on VMware NAT, the board's path to a TFTP server is **UNKNOWN** | G0/G6 |
+
+## Later storage (SD1 eMMC)
+
+| Item | Value | Evidence / status |
+|---|---|---|
+| Device | soldered eMMC KLM8G1GETF 8 GB | core board p9 |
+| Controller | PS SD1 (`sdhci1`, 0xE0101000), MIO46..51, 4-bit; SD0 disabled in HDF (no socket) | HDF |
+| CD / WP / power | none; DT uses `non-removable` and `disable-wp` (opposite of HJX9009, which must not use non-removable) | HDF `PCW_SD1_GRP_*=0` |
+| Voltage / max frequency | card VCCQ **UNKNOWN**; build limits `max-frequency` to 25 MHz and sets `no-1-8-v` as a conservative choice, not a measured limit | E0 |
+| U-Boot read of SD1 before Linux | **UNKNOWN** -> E0 `mmc list; mmc info` (DT alias mmc0 = sdhci1, do not assume the device number) | |
+| Linux naming | do not infer from `/dev/mmcblkN`; identify by CID/capacity | skill rule |
+| Current contents | **UNKNOWN**; any formatting needs separate user authorisation | |
+
+## PL access
+
+- `axil_regs_0` (BD module reference) at 0x43C00000, 64 KiB, behind M_AXI_GP0. The DTG emits a PL node for it; the build
+  overrides its `compatible` with `generic-uio` and passes `uio_pdrv_genirq.of_id=generic-uio`, so `/dev/uio*` exists but no
+  driver touches the registers. Applications use `/dev/mem` (`CONFIG_STRICT_DEVMEM` off).
+- **Hazard:** accessing GP0 before the PL is loaded hangs the bus (Task-PR00 §13#14). Load the PL through the FPGA manager
+  first, then read `ID_VER` (0x43C00000).
+
+## Acceptance decisions / hazards
+
+- Cold-boot count: G6 >= 2 complete power cycles; warm resets do not count (hot reset behaviour of PL/PHY **UNKNOWN**).
+- Network: ping plus a real TFTP transfer with byte count and SHA-256.
+- Storage: read-only enumeration only (CID, capacity, partition table, sample reads); formatting is petalinux-emmc E2.
+- Stop/recovery threshold: no QSPI erase until JTAG FSBL/U-Boot boot and SW1 JTAG mode are proven, the console is captured,
+  and the user has confirmed the destructive target (board, hashes, ranges, recovery path).
+- Known risks: substitute DDR model; YT8521 without driver; RGMII SI unsigned-off (Task-PR00 §13#4); W25Q256 > 16 MiB access.
+
+## First build facts (R02-T5, 2026-10-27; static/VM only)
+
+- U-Boot 2018.01 (PetaLinux default `zynq_zc702_config` base): `CONFIG_ZYNQ_QSPI`, `CONFIG_SPI_FLASH_WINBOND` (table contains
+  `w25q256`), `CONFIG_SPI_FLASH_BAR` (bank-register access above 16 MiB), `CONFIG_SF_DUAL_FLASH=y` (default; DT says
+  `is-dual = <0>`), env in SPI flash `ENV_OFFSET 0x400000 / ENV_SIZE 0x40000 / ENV_SECT_SIZE 0x20000`, PHY = generic.
+  Whether `SF_DUAL_FLASH` misbehaves with the single W25Q256 is **UNKNOWN** -> G4 `sf probe` banner.
+- DTG emits the QSPI flash as `n25q512a`; the build overrides it to `"w25q256", "jedec,spi-nor"`. If the live probe reports a
+  different part, treat it as profile drift (workflow G1-G3 rule).
+- Generated default `bootcmd=run default_bootcmd` = `sf probe 0 && sf read 0x10000000 0x440000 0x1800000 && bootm 0x10000000`.
+- First FIT: 16580256 B (erase 0xFD0000, ends at 0x01410000, i.e. above 16 MiB); BOOT.BIN 558752 B (FSBL + U-Boot only).