bowei/skills-win
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boweiandClaude Opus 5 0b5583a5c0 sync: WIN-BOWEI 2026-08-10 硬编码审计：两个 flow driver 的工程根改读 skills_env.md 
- run_fpga_local.py: FPGA_FLOW_ROOT 写死 E:\LangGraph_Design\fpga-goldenref-flow
  -> _env_lookup(FPGA_GOLDENREF_ROOT)，未配置时给出明确提示。
- run_imx6_flow.py: DEFAULT_PROJECT 写死 -> _env_lookup(FPGA_IMX6_FLOW_ROOT)，
  --project-dir 为空时报错而不是拿错路径继续。
与 sim-rtl-flow / zynq-imx6-flow 已有写法一致。

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
 2026-08-19 12:50:44 +08:00
Myfro9 bceafcd58c Update FPGA and Vivado skills 2026-07-14 18:18:17 +08:00
Myfro9 814dbf1681 更新了skill 2026-06-22 16:41:44 +08:00