{
  "_README": "Rule 2 of Task12-1: m code inside an RTL-bound subtree is only acceptable against a NAMED Xilinx IP, proven cycle-true. Copy this file to Notes/<model>_mcode_exemptions.json and fill it in. Every field is mandatory; check_exemptions.py rejects the entry otherwise.",
  "model": "dpd_ntn_05",
  "hdl_target": "dpd_ntn_05/DpdAlign_HDL",
  "exemptions": [
    {
      "block": "dpd_ntn_05/DpdAlign_HDL/RxAlign_HDL/RxAlignCore",
      "reason": "为什么原生 Simulink 模块搭不出来(必须具体:算法结构/时序/资源,不接受“太麻烦”)",
      "xilinx_ip": "cordic 6.0 (Arc_Tan) + dist_mem_gen sin/cos ROM + blk_mem_gen SDP",
      "ip_scope": "IP 覆盖的范围;剩下仍由 m 代码实现的部分要写清楚,它们仍然是欠账",
      "cycle_true_evidence": "vivado/rtl_ip/dpd_ntn_05/cmp/cmp_result.txt",
      "evidence_kind": "rtl-ip-replace 双 DUT 逐拍对比(首行须为 PASS)",
      "approved_by": "bowei",
      "date": "2026-07-24"
    }
  ]
}