function hits = hdl_block_search(varargin)
%HDL_BLOCK_SEARCH  Find a native, RTL-generatable Simulink block (Task12-1 rule 1).
%
%   hdl_block_search                 list every block in the HDL Coder library
%   hdl_block_search('ram')          blocks whose name matches a keyword
%   hdl_block_search('sin','cos')    several keywords (OR)
%
%   Source of truth is the HDL Coder block library (hdlsllib) plus the HDL
%   Optimized blocks of DSP HDL / Wireless HDL / Vision HDL: anything in there
%   generates RTL directly, so it is a legal building block.  Anything NOT in
%   there needs checkhdl before you rely on it.

% Sub-libraries are listed individually: the top-level DSP HDL library holds
% links, which find_system will not walk into.
libs = {'hdlsllib', ...                                   % HDL Coder baseline set
        'dsphdlfiltering2', 'dsphdlmathfun2', ...         % FIR/CIC/LMS/Biquad, CORDIC
        'dsphdlxfrm2', 'dsphdlsigops2', 'dsphdlsrcs2', ...% FFT/IFFT, Farrow/NCO/resample
        'whdllib', 'visionhdllib'};
hits = {};
for i = 1:numel(libs)
    try
        load_system(libs{i});
    catch
        continue
    end
    blks = find_system(libs{i}, 'SearchDepth', 5, 'Type', 'Block');
    for k = 1:numel(blks)
        nm = strrep(get_param(blks{k}, 'Name'), newline, ' ');
        if isempty(varargin) || any(cellfun(@(p) ~isempty(regexpi(nm, p, 'once')), varargin))
            hits{end+1, 1} = nm; %#ok<AGROW>
            hits{end, 2} = blks{k}; %#ok<AGROW>
        end
    end
end

if isempty(hits)
    fprintf(['no HDL library block matches %s\n' ...
             '-> if you cannot build it from these blocks, rule 2 applies: name the Xilinx IP\n' ...
             '   that will implement it, prove the swap cycle-true, and file the exemption.\n'], ...
            strjoin(varargin, ', '));
    return
end

[~, ia] = unique(hits(:, 1));
hits = hits(sort(ia), :);
fprintf('%d HDL-generatable block(s):\n', size(hits, 1));
for k = 1:size(hits, 1)
    fprintf('  %-42s  %s\n', hits{k, 1}, hits{k, 2});
end
end