// AXI-Stream FIFO 模块（测试用，深度4）
module axis_fifo #(
    parameter DATA_WIDTH = 8,
    parameter DEPTH      = 4
)(
    input  wire                   clk,
    input  wire                   rst_n,
    // 从机（写入）端口
    input  wire [DATA_WIDTH-1:0]  s_tdata,
    input  wire                   s_tvalid,
    output wire                   s_tready,
    // 主机（读出）端口
    output wire [DATA_WIDTH-1:0]  m_tdata,
    output wire                   m_tvalid,
    input  wire                   m_tready
);

    reg [DATA_WIDTH-1:0] mem [0:DEPTH-1];
    reg [$clog2(DEPTH):0] wr_ptr, rd_ptr, count;

    assign s_tready = (count < DEPTH);
    assign m_tvalid = (count > 0);
    assign m_tdata  = mem[rd_ptr[$clog2(DEPTH)-1:0]];

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            wr_ptr <= 0; rd_ptr <= 0; count <= 0;
        end else begin
            if (s_tvalid && s_tready) begin
                mem[wr_ptr[$clog2(DEPTH)-1:0]] <= s_tdata;
                wr_ptr <= wr_ptr + 1;
                count  <= count + 1;
            end
            if (m_tvalid && m_tready) begin
                rd_ptr <= rd_ptr + 1;
                count  <= count - 1;
            end
            // 同时读写（count 保持不变已在上面分开处理，这里修正）
            if (s_tvalid && s_tready && m_tvalid && m_tready) begin
                count <= count; // 读写同时，count 不变
            end
        end
    end

endmodule