boweiandClaude Opus 5
e07cfaa6d1
- fpga_flash: 新增 build_zynq_boot.py / program_zynq_qspi.py（bootgen + program_flash， 含备份、SHA-256/容量/marker 守卫）；vivado_env.py 增 resolve_sdk_dir（SDK_ROOT/SDK_PATH）； SKILL.md 补 Zynq 烧写流程，示例去掉写死的 D:\Xilinx\SDK\2018.1，改由 skills_env.md 解析。 - rtl-ip-replace: gen_ip.tcl / namespace_ip.py 更新。 - sim-rtl-flow: SKILL.md 与 run_sim_rtl_flow.py 更新。 Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
213 lines
12 KiB
Tcl
213 lines
12 KiB
Tcl
# =============================================================================
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# gen_ip.tcl -- create the Vivado IPs listed in rtl_ip/ip_manifest.tcl
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# usage: vivado -mode batch -source gen_ip.tcl -tclargs <ip_manifest.tcl> <ip_out_dir> [part]
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# Managed-IP style: .xci + synthesis + simulation targets are generated so the
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# cores can be (a) added to the synthesis project and (b) compiled for xsim.
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# =============================================================================
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set manifest [lindex $argv 0]
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set ipdir [file normalize [lindex $argv 1]]
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set part xc7z100ffg900-2
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if {[llength $argv] > 2} { set part [lindex $argv 2] }
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file mkdir $ipdir
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create_project -in_memory -part $part
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set_property target_language Verilog [current_project]
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set ips {}
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source $manifest ;# fills $ips: list of {type {..} name {..} width {..} depth {..} coe {..} mode {..}}
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# manifest field with a default (older manifests do not carry the newer keys)
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proc opt {arrname key def} {
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upvar 1 $arrname c
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if {[info exists c($key)] && $c($key) ne {}} { return $c($key) }
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return $def
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}
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foreach ip $ips {
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array unset c; array set c $ip
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set name $c(name)
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if {[file exists $ipdir/$name/$name.xci]} {
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puts "###### SKIP $name (exists)"
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continue
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}
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switch -- $c(type) {
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dist_mem_gen {
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# mode {rom} (default) -- constant lookup table, asynchronous read.
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# mode {dual_port_ram} -- LUTRAM, port A = write + async read (spo),
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# port B = async read (dpo), NO output registers. Use this (not
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# blk_mem_gen) whenever the generated RAM needs a DEFINED read of
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# the pre-write word while the other port writes the same address:
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# a block-RAM primitive leaves the opposite port's read data
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# undefined on such a collision (PG058), distributed RAM does not.
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# The output registers / write-first read-back stay in the RTL
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# wrapper so latency and enb gating remain cycle-identical.
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set dmode [opt c mode {rom}]
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create_ip -name dist_mem_gen -vendor xilinx.com -library ip -version 8.0 \
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-module_name $name -dir $ipdir
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if {$dmode eq "dual_port_ram"} {
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set_property -dict [list \
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CONFIG.memory_type {dual_port_ram} \
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CONFIG.data_width $c(width) \
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CONFIG.depth $c(depth) \
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CONFIG.input_options {non_registered} \
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CONFIG.output_options {non_registered} \
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CONFIG.dual_port_address {non_registered} \
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CONFIG.input_clock_enable {false} \
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CONFIG.default_data {0} \
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] [get_ips $name]
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} else {
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set_property -dict [list \
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CONFIG.memory_type {rom} \
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CONFIG.data_width $c(width) \
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CONFIG.depth $c(depth) \
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CONFIG.coefficient_file $c(coe) \
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] [get_ips $name]
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}
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}
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blk_mem_gen {
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# mode {sdp_readfirst_commonclk} (default): SDP, common clock,
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# READ_FIRST on the write port, no output register, ENA/ENB pins --
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# matches SimpleDualPortRAM_generic semantics exactly.
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# mode {tdp_writefirst_commonclk}: TRUE dual port, port A
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# WRITE_FIRST (write with read-back), port B READ_FIRST.
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# CAUTION: a BRAM primitive does NOT define the port-B read data
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# when port A writes the same address in the same cycle; only use
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# this when the design provably never collides.
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set bmode [opt c mode {sdp_readfirst_commonclk}]
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set mtype {Simple_Dual_Port_RAM}
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set opa {READ_FIRST}
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if {$bmode eq "tdp_writefirst_commonclk"} {
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set mtype {True_Dual_Port_RAM}
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set opa {WRITE_FIRST}
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}
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create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 \
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-module_name $name -dir $ipdir
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set_property -dict [list \
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CONFIG.Memory_Type $mtype \
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CONFIG.Assume_Synchronous_Clk {true} \
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CONFIG.Use_Byte_Write_Enable {false} \
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CONFIG.Write_Width_A $c(width) \
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CONFIG.Write_Depth_A $c(depth) \
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CONFIG.Read_Width_A $c(width) \
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CONFIG.Write_Width_B $c(width) \
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CONFIG.Read_Width_B $c(width) \
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CONFIG.Operating_Mode_A $opa \
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CONFIG.Enable_A {Use_ENA_Pin} \
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CONFIG.Enable_B {Use_ENB_Pin} \
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CONFIG.Register_PortB_Output_of_Memory_Primitives {false} \
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CONFIG.Register_PortB_Output_of_Memory_Core {false} \
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] [get_ips $name]
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if {$bmode eq "tdp_writefirst_commonclk"} {
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set_property -dict [list \
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CONFIG.Operating_Mode_B {READ_FIRST} \
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CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
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CONFIG.Register_PortA_Output_of_Memory_Core {false} \
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] [get_ips $name]
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}
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}
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fifo_generator {
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# guided: mode field carries standard|fwft; depth/width from manifest
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create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 \
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-module_name $name -dir $ipdir
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set rm {Standard_FIFO}
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if {[info exists c(mode)] && $c(mode) eq "fwft"} { set rm {First_Word_Fall_Through} }
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set_property -dict [list \
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CONFIG.Fifo_Implementation {Common_Clock_Block_RAM} \
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CONFIG.Performance_Options $rm \
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CONFIG.Input_Data_Width $c(width) \
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CONFIG.Input_Depth $c(depth) \
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CONFIG.Output_Data_Width $c(width) \
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CONFIG.Output_Depth $c(depth) \
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] [get_ips $name]
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}
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cordic {
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# guided: Arc_Tan phase-seed kernel. Coarse rotation = full-quadrant atan2
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# (bidirectional-adjustment principle: better than the FSM's RHP quirk);
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# Radians 3QN phase; Truncate rounding; ACLKEN so enb gating stays exact;
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# parallel/maximum pipelining -> latency ~input_width+4, well under the
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# 64-cycle commit budget.
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create_ip -name cordic -vendor xilinx.com -library ip -version 6.0 \
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-module_name $name -dir $ipdir
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set_property -dict [list \
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CONFIG.Functional_Selection {Arc_Tan} \
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CONFIG.Input_Width $c(width) \
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CONFIG.Output_Width $c(out_width) \
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CONFIG.Data_Format {SignedFraction} \
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CONFIG.Phase_Format {Radians} \
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CONFIG.Coarse_Rotation {true} \
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CONFIG.Round_Mode {Truncate} \
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CONFIG.ACLKEN {true} \
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CONFIG.Pipelining_Mode {Maximum} \
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] [get_ips $name]
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}
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fir_compiler {
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# guided (Task12 §六). Cycle-true-critical settings:
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# Integer_Coefficients : taps go in as integers, the IP must NOT re-quantise
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# Full_Precision output : truncation stays OUTSIDE, done the way the RTL did it
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# Input_Sample_Period/1 : one sample per clock, no hardware folding
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# -> the latency is a fixed number we can align to
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# ACLKEN : gated by enb exactly like the generated RTL
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# no TREADY / no input FIFO: pure pipeline, no variable-latency handshake
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create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 \
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-module_name $name -dir $ipdir
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set_property -dict [list \
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CONFIG.Filter_Type [opt c filter_type {Single_Rate}] \
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CONFIG.CoefficientSource {COE_File} \
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CONFIG.Coefficient_File $c(coe) \
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CONFIG.Quantization {Integer_Coefficients} \
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CONFIG.Coefficient_Width $c(coef_width) \
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CONFIG.Coefficient_Fractional_Bits [opt c coef_frac 0] \
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CONFIG.Coefficient_Sign {Signed} \
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CONFIG.Coefficient_Structure [opt c coef_structure {Inferred}] \
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CONFIG.Data_Width $c(width) \
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CONFIG.Data_Fractional_Bits [opt c frac 0] \
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CONFIG.Data_Sign {Signed} \
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CONFIG.Output_Rounding_Mode {Full_Precision} \
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CONFIG.RateSpecification {Input_Sample_Period} \
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CONFIG.SamplePeriod 1 \
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CONFIG.HardwareOversamplingRate 1 \
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CONFIG.Interpolation_Rate [opt c interp 1] \
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CONFIG.Decimation_Rate [opt c decim 1] \
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CONFIG.Zero_Pack_Factor [opt c zero_pack 1] \
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CONFIG.Number_Channels [opt c channels 1] \
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CONFIG.Number_Paths [opt c paths 1] \
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CONFIG.Coefficient_Reload [opt c reload {false}] \
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CONFIG.Num_Reload_Slots [opt c reload_slots 1] \
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CONFIG.Has_ACLKEN [opt c aclken {true}] \
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CONFIG.Has_ARESETn [opt c aresetn {false}] \
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CONFIG.M_DATA_Has_TREADY {false} \
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CONFIG.S_DATA_Has_FIFO {false} \
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] [get_ips $name]
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}
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cic_compiler {
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# guided: only for large integer rate changes (CIC), fixed rate so the
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# decimation/interpolation cadence is static and comparable cycle by cycle.
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create_ip -name cic_compiler -vendor xilinx.com -library ip -version 4.0 \
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-module_name $name -dir $ipdir
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set rate [opt c rate 1]
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set_property -dict [list \
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CONFIG.Filter_Type [opt c filter_type {Decimation}] \
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CONFIG.Number_Of_Stages [opt c stages 3] \
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CONFIG.Differential_Delay [opt c diff_delay 1] \
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CONFIG.Sample_Rate_Changes {Fixed} \
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CONFIG.Fixed_Or_Initial_Rate $rate \
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CONFIG.Minimum_Rate [opt c min_rate $rate] \
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CONFIG.Maximum_Rate [opt c max_rate $rate] \
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CONFIG.Input_Data_Width $c(width) \
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CONFIG.Quantization {Full_Precision} \
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CONFIG.RateSpecification {Sample_Period} \
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CONFIG.SamplePeriod 1 \
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CONFIG.Number_Of_Channels [opt c channels 1] \
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CONFIG.Use_Xtreme_DSP_Slice {false} \
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CONFIG.HAS_ACLKEN [opt c aclken {true}] \
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CONFIG.HAS_ARESETN [opt c aresetn {false}] \
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CONFIG.HAS_DOUT_TREADY {false} \
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] [get_ips $name]
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}
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default { puts "###### UNKNOWN IP TYPE: $c(type) ($name)"; continue }
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}
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generate_target {instantiation_template synthesis simulation} [get_ips $name]
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puts "###### GENERATED $name ($c(type))"
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}
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puts "###### DONE [llength $ips] ip(s) in $ipdir"
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