19 lines
497 B
Verilog
19 lines
497 B
Verilog
// 8位计数器模块
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module counter8 (
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input wire clk, // 系统时钟
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input wire rst_n, // 低有效复位
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input wire en, // 使能信号
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output reg [7:0] count, // 计数输出
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output wire overflow // 溢出标志（count == 8'hFF）
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);
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assign overflow = (count == 8'hFF) & en;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n)
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count <= 8'h00;
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else if (en)
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count <= count + 1'b1;
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end
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endmodule |