bowei
ea4541ee90
- simulink_rtl_dev / rtl-ip-replace: 从工程级 .claude/skills 迁到用户级并去工程耦合 (模型名/Notes 文档依赖/工程实测基线移出; addpath 与脚本路径改用户级) - rtl-ip-replace/scripts/gen_cmp_tb.py: Vivado 路径不再写死, 改读 VIVADO_PATH / XILINX_VIVADO (兼容 install root / bin / bin\vivado.bat 三种写法), 回落时提示 去设 skills_env.md 的 VIVADO_PATH - simulink-rtl-redev: 新增。原生模型改动后的仿真模型同步规范, 含两个实测过的工具 check_sync.py (三条时序链新鲜度闸门) 与 measure_k.m (时域/频域/包络三估计器互证) - sim-rtl-flow/SKILL.md: 加入 sync_sim:* 步骤, 引用上述三个 skill
51 lines
2.0 KiB
Matlab
51 lines
2.0 KiB
Matlab
function hits = hdl_block_search(varargin)
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%HDL_BLOCK_SEARCH Find a native, RTL-generatable Simulink block (Task12-1 rule 1).
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%
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% hdl_block_search list every block in the HDL Coder library
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% hdl_block_search('ram') blocks whose name matches a keyword
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% hdl_block_search('sin','cos') several keywords (OR)
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%
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% Source of truth is the HDL Coder block library (hdlsllib) plus the HDL
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% Optimized blocks of DSP HDL / Wireless HDL / Vision HDL: anything in there
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% generates RTL directly, so it is a legal building block. Anything NOT in
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% there needs checkhdl before you rely on it.
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% Sub-libraries are listed individually: the top-level DSP HDL library holds
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% links, which find_system will not walk into.
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libs = {'hdlsllib', ... % HDL Coder baseline set
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'dsphdlfiltering2', 'dsphdlmathfun2', ... % FIR/CIC/LMS/Biquad, CORDIC
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'dsphdlxfrm2', 'dsphdlsigops2', 'dsphdlsrcs2', ...% FFT/IFFT, Farrow/NCO/resample
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'whdllib', 'visionhdllib'};
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hits = {};
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for i = 1:numel(libs)
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try
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load_system(libs{i});
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catch
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continue
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end
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blks = find_system(libs{i}, 'SearchDepth', 5, 'Type', 'Block');
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for k = 1:numel(blks)
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nm = strrep(get_param(blks{k}, 'Name'), newline, ' ');
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if isempty(varargin) || any(cellfun(@(p) ~isempty(regexpi(nm, p, 'once')), varargin))
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hits{end+1, 1} = nm; %#ok<AGROW>
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hits{end, 2} = blks{k}; %#ok<AGROW>
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end
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end
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end
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if isempty(hits)
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fprintf(['no HDL library block matches %s\n' ...
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'-> if you cannot build it from these blocks, rule 2 applies: name the Xilinx IP\n' ...
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' that will implement it, prove the swap cycle-true, and file the exemption.\n'], ...
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strjoin(varargin, ', '));
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return
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end
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[~, ia] = unique(hits(:, 1));
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hits = hits(sort(ia), :);
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fprintf('%d HDL-generatable block(s):\n', size(hits, 1));
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for k = 1:size(hits, 1)
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fprintf(' %-42s %s\n', hits{k, 1}, hits{k, 2});
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end
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end
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