feat(atsc_app): 更新138R射频状态展示与维护说明

将发布版本记录更新至138R，并在Overview中为SNR、LIMD和UIMD增加与Dashboard一致的阈值着色，同时统一LIMD/UIMD趋势顺序。
补充ORx QEC测试背景和DPD结束后FAGC恢复方案注释；恢复调用仍保持注释状态，不改变现有运行行为。
已执行暂存区差异、空白错误及冲突标记检查；未执行编译和设备验证。

src/Makefile

@@ -85,6 +85,8 @@ SVN_VER_NUM=136RT3
 
 SVN_VER_NUM=137R
 
+SVN_VER_NUM=138R
+
 OUT_FS_DIR := $(PWD)/../out/rootfs
 UPGARDE_IMX_FS_DIR := SMOD
 OUT_WEB_PKG_DIR := $(PWD)/../out/upgrade_imx_fs/$(UPGARDE_IMX_FS_DIR)/src
@@ -120,29 +122,29 @@ all:
 #	@cp logrotate_master/popt-1.7/oneshu_install/libpopt.so*  ../out/upgrade_imx_fs/$(UPGARDE_IMX_FS_DIR)/src/lib/
 #	@cp logrotate_master/popt-1.7/oneshu_install/libpopt.so*  ../out/rootfs/lib/
 	@echo "\n\n\t APP+WEB+9528+log+daemon intall ok\n\n"
-
+	
 	cp $(PWD)/anywave_exc_start.sh  $(OUT_FS_DIR)/aw/
 	cp $(PWD)/anywave_exc_start.sh  $(OUT_WEB_PKG_DIR)/aw/
 	cp $(PWD)/sh/load_to_cfg_file.sh  $(OUT_FS_DIR)/aw/anywave/
 	cp $(PWD)/sh/load_to_cfg_file.sh  $(OUT_WEB_PKG_DIR)/aw/anywave/
 	cp $(PWD)/sh/sync_to_bkp_file.sh  $(OUT_FS_DIR)/aw/anywave/
 	cp $(PWD)/sh/sync_to_bkp_file.sh  $(OUT_WEB_PKG_DIR)/aw/anywave/
-
+		
 	@ echo -n "$(RELEAS_NUM)_$(RLS_DATETIME)_$(SVN_VER_NUM)" > $(OUT_FS_DIR)/aw/release_version.ini
 	@ echo -n "$(RELEAS_NUM)_$(RLS_DATETIME)_$(SVN_VER_NUM)" > $(OUT_WEB_PKG_DIR)/aw/release_version.ini
 	@ echo "\n\t $(RELEAS_NUM)_$(RLS_DATETIME)_$(SVN_VER_NUM)\n"
-
+	
 	cp $(PWD)/web/upgrade_shell/*   $(OUT_FS_DIR)/aw/anywave/upgrade_shell/
 	cp $(PWD)/web/upgrade_shell/*   $(OUT_WEB_PKG_DIR)/aw/anywave/upgrade_shell/
 	cp $(PWD)/web/sh/*   $(OUT_WEB_PKG_DIR)/aw/anywave/web/sh/
 	cp $(PWD)/web/sh/*   $(OUT_FS_DIR)/aw/anywave/web/sh/
-
+		
-
+	
 	@rm -rf $(OUT_FS_DIR)/*.tar.bz2
 	@cd $(OUT_FS_DIR)/; tar cjf rootfs-console.tar.bz2 *
 	@mv $(OUT_FS_DIR)/rootfs-console.tar.bz2   $(OUT_FS_DIR)/../
 	@echo "\n\n\t rootfs-console.tar.bz2 compress and mv ok\n\n"
-
+	
 	@rm -rf $(PWD)/../out/upgrade_imx_fs/*.tar.gz
 	dos2unix $(PWD)/../out/upgrade_imx_fs/$(UPGARDE_IMX_FS_DIR)/*.sh
 	@cd $(PWD)/../out/upgrade_imx_fs/; tar czf $(WEB_PKG_NAME) $(UPGARDE_IMX_FS_DIR)
@@ -153,7 +155,7 @@ all:
 	rm -rf ~/$(WEB_PKG_NAME)
 	@echo "Done!"
 	@echo ""
-
+	
 all_key:
 	@$(MAKE) -C atsc_app_new_key_lcd clean
 	@$(MAKE) -C atsc_app_new_key_lcd install
@@ -174,29 +176,29 @@ all_key:
 #	@cp logrotate_master/popt-1.7/oneshu_install/libpopt.so*  ../out/upgrade_imx_fs/$(UPGARDE_IMX_FS_DIR)/src/lib/
 #	@cp logrotate_master/popt-1.7/oneshu_install/libpopt.so*  ../out/rootfs/lib/
 	@echo "\n\n\t APP+WEB+9528+log+daemon intall ok\n\n"
-
+	
 	cp $(PWD)/anywave_exc_start.sh  $(OUT_FS_DIR)/aw/
 	cp $(PWD)/anywave_exc_start.sh  $(OUT_WEB_PKG_DIR)/aw/
 	cp $(PWD)/sh/load_to_cfg_file.sh  $(OUT_FS_DIR)/aw/anywave/
 	cp $(PWD)/sh/load_to_cfg_file.sh  $(OUT_WEB_PKG_DIR)/aw/anywave/
 	cp $(PWD)/sh/sync_to_bkp_file.sh  $(OUT_FS_DIR)/aw/anywave/
 	cp $(PWD)/sh/sync_to_bkp_file.sh  $(OUT_WEB_PKG_DIR)/aw/anywave/
-
+		
 	@ echo -n "$(RELEAS_NUM)_$(RLS_DATETIME)_$(SVN_VER_NUM)" > $(OUT_FS_DIR)/aw/release_version.ini
 	@ echo -n "$(RELEAS_NUM)_$(RLS_DATETIME)_$(SVN_VER_NUM)" > $(OUT_WEB_PKG_DIR)/aw/release_version.ini
 	@ echo "\n\t $(RELEAS_NUM)_$(RLS_DATETIME)_$(SVN_VER_NUM)\n"
-
+	
 	cp $(PWD)/web/upgrade_shell/*   $(OUT_FS_DIR)/aw/anywave/upgrade_shell/
 	cp $(PWD)/web/upgrade_shell/*   $(OUT_WEB_PKG_DIR)/aw/anywave/upgrade_shell/
 	cp $(PWD)/web/sh/*   $(OUT_WEB_PKG_DIR)/aw/anywave/web/sh/
 	cp $(PWD)/web/sh/*   $(OUT_FS_DIR)/aw/anywave/web/sh/
-
+		
-
+	
 	@rm -rf $(OUT_FS_DIR)/*.tar.bz2
 	@cd $(OUT_FS_DIR)/; tar cjf rootfs-console.tar.bz2 *
 	@mv $(OUT_FS_DIR)/rootfs-console.tar.bz2   $(OUT_FS_DIR)/../
 	@echo "\n\n\t rootfs-console.tar.bz2 compress and mv ok\n\n"
-
+	
 	@rm -rf $(PWD)/../out/upgrade_imx_fs/*.tar.gz
 	dos2unix $(PWD)/../out/upgrade_imx_fs/$(UPGARDE_IMX_FS_DIR)/*.sh
 	@cd $(PWD)/../out/upgrade_imx_fs/; tar czf $(WEB_PKG_NAME) $(UPGARDE_IMX_FS_DIR)
@@ -207,7 +209,7 @@ all_key:
 	rm -rf ~/$(WEB_PKG_NAME)
 	@echo "Done!"
 	@echo ""
-
+	
 all_nlogo:
 	@$(MAKE) -C atsc_app clean
 	@$(MAKE) -C atsc_app all
@@ -229,29 +231,29 @@ all_nlogo:
 	@cp logrotate_master/popt-1.7/oneshu_install/libpopt.so*  ../out/upgrade_imx_fs/$(UPGARDE_IMX_FS_DIR)/src/lib/
 	@cp logrotate_master/popt-1.7/oneshu_install/libpopt.so*  ../out/rootfs/lib/
 	@echo "\n\n\t APP+WEB+9528+log+daemon intall ok\n\n"
-
+	
 	cp $(PWD)/anywave_exc_start.sh  $(OUT_FS_DIR)/aw/
 	cp $(PWD)/anywave_exc_start.sh  $(OUT_WEB_PKG_DIR)/aw/
 	cp $(PWD)/sh/load_to_cfg_file.sh  $(OUT_FS_DIR)/aw/anywave/
 	cp $(PWD)/sh/load_to_cfg_file.sh  $(OUT_WEB_PKG_DIR)/aw/anywave/
 	cp $(PWD)/sh/sync_to_bkp_file.sh  $(OUT_FS_DIR)/aw/anywave/
 	cp $(PWD)/sh/sync_to_bkp_file.sh  $(OUT_WEB_PKG_DIR)/aw/anywave/
-
+		
 	@ echo -n "$(RELEAS_NUM)_$(RLS_DATETIME)_$(SVN_VER_NUM)" > $(OUT_FS_DIR)/aw/release_version.ini
 	@ echo -n "$(RELEAS_NUM)_$(RLS_DATETIME)_$(SVN_VER_NUM)" > $(OUT_WEB_PKG_DIR)/aw/release_version.ini
 	@ echo "\n\t $(RELEAS_NUM)_$(RLS_DATETIME)_$(SVN_VER_NUM)\n"
-
+	
 	cp $(PWD)/web/upgrade_shell/*   $(OUT_FS_DIR)/aw/anywave/upgrade_shell/
 	cp $(PWD)/web/upgrade_shell/*   $(OUT_WEB_PKG_DIR)/aw/anywave/upgrade_shell/
 	cp $(PWD)/web/sh/*   $(OUT_WEB_PKG_DIR)/aw/anywave/web/sh/
 	cp $(PWD)/web/sh/*   $(OUT_FS_DIR)/aw/anywave/web/sh/
-
+		
-
+	
 	@rm -rf $(OUT_FS_DIR)/*.tar.bz2
 	@cd $(OUT_FS_DIR)/; tar cjf rootfs-console.tar.bz2 *
 	@mv $(OUT_FS_DIR)/rootfs-console.tar.bz2   $(OUT_FS_DIR)/../
 	@echo "\n\n\t rootfs-console.tar.bz2 compress and mv ok\n\n"
-
+	
 	@rm -rf $(PWD)/../out/upgrade_imx_fs/*.tar.gz
 	dos2unix $(PWD)/../out/upgrade_imx_fs/$(UPGARDE_IMX_FS_DIR)/*.sh
 	@cd $(PWD)/../out/upgrade_imx_fs/; tar czf $(WEB_PKG_NAME_NL) $(UPGARDE_IMX_FS_DIR)
@@ -260,7 +262,7 @@ all_nlogo:
 	rm -rf ~/$(WEB_PKG_NAME_NL)
 	@echo "Done!"
 	@echo ""
-
+	
 all_korea_logo:
 	@$(MAKE) -C atsc_app install
 #	@$(MAKE) -C cttb_app_38j82 install
@@ -280,42 +282,42 @@ all_korea_logo:
 	@cp logrotate_master/popt-1.7/oneshu_install/libpopt.so*  ../out/upgrade_imx_fs/$(UPGARDE_IMX_FS_DIR)/src/lib/
 	@cp logrotate_master/popt-1.7/oneshu_install/libpopt.so*  ../out/rootfs/lib/
 	@echo "\n\n\t APP+WEB+9528+log+daemon intall ok\n\n"
-
+	
 	cp $(PWD)/anywave_exc_start.sh  $(OUT_FS_DIR)/aw/
 	cp $(PWD)/anywave_exc_start.sh  $(OUT_WEB_PKG_DIR)/aw/
 	cp $(PWD)/sh/load_to_cfg_file.sh  $(OUT_FS_DIR)/aw/anywave/
 	cp $(PWD)/sh/load_to_cfg_file.sh  $(OUT_WEB_PKG_DIR)/aw/anywave/
 	cp $(PWD)/sh/sync_to_bkp_file.sh  $(OUT_FS_DIR)/aw/anywave/
 	cp $(PWD)/sh/sync_to_bkp_file.sh  $(OUT_WEB_PKG_DIR)/aw/anywave/
-
+		
 	@ echo -n "$(RELEAS_NUM)_$(RLS_DATETIME)_$(SVN_VER_NUM)" > $(OUT_FS_DIR)/aw/release_version.ini
 	@ echo -n "$(RELEAS_NUM)_$(RLS_DATETIME)_$(SVN_VER_NUM)" > $(OUT_WEB_PKG_DIR)/aw/release_version.ini
 	@ echo "\n\t $(RELEAS_NUM)_$(RLS_DATETIME)_$(SVN_VER_NUM)\n"
-
+	
 	cp $(PWD)/web/upgrade_shell/*   $(OUT_FS_DIR)/aw/anywave/upgrade_shell/
 	cp $(PWD)/web/upgrade_shell/*   $(OUT_WEB_PKG_DIR)/aw/anywave/upgrade_shell/
 	cp $(PWD)/web/sh/*   $(OUT_WEB_PKG_DIR)/aw/anywave/web/sh/
 	cp $(PWD)/web/sh/*   $(OUT_FS_DIR)/aw/anywave/web/sh/
-
+		
-
+	
 	@rm -rf $(OUT_FS_DIR)/*.tar.bz2
 	@cd $(OUT_FS_DIR)/; tar cjf rootfs-console.tar.bz2 *
 	@mv $(OUT_FS_DIR)/rootfs-console.tar.bz2   $(OUT_FS_DIR)/../
 	@echo "\n\n\t rootfs-console.tar.bz2 compress and mv ok\n\n"
-
+	
 	@rm -rf $(PWD)/../out/upgrade_imx_fs/*.tar.gz
 	dos2unix $(PWD)/../out/upgrade_imx_fs/$(UPGARDE_IMX_FS_DIR)/*.sh
 	@cd $(PWD)/../out/upgrade_imx_fs/; tar czf $(WEB_PKG_NAME_KOREA) $(UPGARDE_IMX_FS_DIR)
 	@mv $(PWD)/../out/upgrade_imx_fs/$(WEB_PKG_NAME_KOREA) $(PWD)/../out/
 	@echo "\n\n\t $(WEB_PKG_NAME_KOREA) compress and mv ok\n\n"
-	rm -rf ~/$(WEB_PKG_NAME_KOREA)
+	rm -rf ~/$(WEB_PKG_NAME_KOREA)	
 	@echo "Done!"
 	@echo ""
-
+	
 dtb:
 	@cp $(PWD)/../tools/linux-4.1.15/arch/arm/boot/dts/imx6ull-S-gpmi-1024x600c7.dtb  $(PWD)/../out/
 	@echo "\n\n\t imx6ull-S-gpmi-1024x600c7.dtb mv ok\n\n"
-
+	
 zImage:
 	@cp $(PWD)/../tools/linux-4.1.15/arch/arm/boot/zImage  $(PWD)/../out/
 	@echo "\n\n\t zImage mv ok\n\n"
@@ -327,10 +329,10 @@ kernel_zImage:
 	@echo "$(KERNEL_PATH) is existed\n\n"
 	@$(MAKE) -C $(KERNEL_PATH)  zImage -j4
  else
-	@echo "$(KERNEL_PATH) is not exist , uncompress linux-4.1.15.tar.gz ...ing"
+	@echo "$(KERNEL_PATH) is not exist , uncompress linux-4.1.15.tar.gz ...ing" 
 	@cd $(PWD)/../tools/; tar -xzf linux-4.1.15.tar.gz
 	@cp $(PWD)/../kernel/linux-4.1.15/config_emv6.3  $(KERNEL_PATH)/.config
-	@$(MAKE) -C $(KERNEL_PATH)  zImage -j4
+	@$(MAKE) -C $(KERNEL_PATH)  zImage -j4 
  endif
 
 
@@ -339,7 +341,7 @@ kernel_dtbs:
 	@echo "$(KERNEL_PATH)     "
 	@$(MAKE) -C $(KERNEL_PATH)  dtbs -j4
  else
-	@echo "$(KERNEL_PATH) is not exist , uncompress linux-4.1.15.tar.gz ...ing"
+	@echo "$(KERNEL_PATH) is not exist , uncompress linux-4.1.15.tar.gz ...ing" 
 	@cd $(PWD)/../tools/; tar -xzf linux-4.1.15.tar.gz
 	@cp $(PWD)/../kernel/linux-4.1.15/config_emv6.3  $(KERNEL_PATH)/.config
 	@$(MAKE) -C $(KERNEL_PATH)  zImage -j4

src/atsc_app/adrv9009/adrv9009_config.c

@@ -340,7 +340,13 @@ int adrv9009_cfg(int which_9009)
                             TAL_ADC_STITCHING|
 
 							TAL_ORX_LO_DELAY |	//add 260518 ORx 专用初始化校准
-							TAL_ORX_QEC_INIT    //add 260518 ORx 专用初始化校准
+							/*
+							 * PR16 hardware A/B test: keep the one-shot cold-boot
+							 * QEC init, but do not enable TAL_TRACK_ORX1_QEC.
+							 * Forced tracking reached IRR=58 dB / 2099 updates,
+							 * while the exported ORx IQ stream became all zero.
+							 */
+							TAL_ORX_QEC_INIT
 							;
 	uint8_t errorFlag = 0;
 	taliseErr_t mykError = TAL_ERR_OK;

src/atsc_app/bsp/dpd_proc.c

@@ -42,8 +42,8 @@
  * 两段，所以一并延长到 FAGC_PH7_SHORT_SEC，按 FAGC_LOCK_SEC_SHORT 切分。
  */
 #define FAGC_LOCK_SEC        (10)
-#define FAGC_LOCK_SEC_SHORT  (4)
+#define FAGC_LOCK_SEC_SHORT  (2)
-#define FAGC_PH7_SHORT_SEC   (8)
+#define FAGC_PH7_SHORT_SEC   (5)
 
 
 enum{PHASE6_SET_SAVE=1,PHASE10_SET_SAVE,WPP_SET_SAVE};
@@ -119,7 +119,7 @@ void write_unit_area_addr_to_spi_blkbuf(uint8 Taddr,uint16 Iaddr,uint8 Raddr, u8
 		pblk[0] = 0x7f & (((Raddr&0x3)<<2) | ((Iaddr>>8)&0x3));
 	else//wr
 		pblk[0] = 0x80 | (((Raddr&0x3)<<2) | ((Iaddr>>8)&0x3));
-
+	
 	pblk[1] = Iaddr&0xff;
 	pblk[2] = Taddr;
 }
@@ -351,13 +351,13 @@ static void * display_save_load_percent_thr(void * args)
 	char temp_buf[20];
 	static u32 x_time_cnt = 0;
 	printf("enter display\n");
-
+	
 	x_time_cnt = 0;
 	while(1){
     	log_printf(LOG_DEBUG, I_USER_CFG, "%02d%%   \n", atsc_para.system_para.save_load_data_percent);
 		memset(temp_buf,0,sizeof(temp_buf));
         sprintf((char*)temp_buf,"%02d%%   ",atsc_para.system_para.save_load_data_percent);
-
+		
         lcd_write_string(1,15,(uint8*)temp_buf);
         lcd_write_cache();
 
@@ -375,7 +375,7 @@ static void * display_save_load_percent_thr(void * args)
 		usleep(250*1000);
 	};
 
-
+	
 	printf(" thr exit display %d,  display_sta=%d [0-start,2-stop]\n", ret_code, st_extend_state.display_stop);
 	st_extend_state.display_stop = E_DISPLAY_END;
 }
@@ -386,12 +386,12 @@ static int thr_display_percent_thread(void)
     pthread_t display_thr_id;
 	int state;
 	pthread_attr_t attr;
-
+	
 
 	log_printf(LOG_DEBUG,I_NOUSED,"[.thr.]->-\n");
 
 	pthread_attr_init(&attr);
-	pthread_attr_setdetachstate(&attr, PTHREAD_CREATE_DETACHED);
+	pthread_attr_setdetachstate(&attr, PTHREAD_CREATE_DETACHED);  
 
     ret = pthread_create(&display_thr_id, &attr, (void *)display_save_load_percent_thr, NULL);//
     if(ret != 0){
@@ -451,7 +451,7 @@ void clear_check_sum(S_CHECK_SUM *parea_check)
 {
 	parea_check->area_imx_w_check =0;
 	parea_check->area_imx_r_check =0;
-
+	
 	parea_check->area_fpga_w_check=0;
 	parea_check->area_fpga_r_check=0;
 }
@@ -515,15 +515,15 @@ static int load_file_and_write_area(void)
         for(Taddr=0; Taddr<=31; Taddr++){
 			memset(spi_blk_buf, 0, sizeof(spi_blk_buf));
 			write_unit_area_addr_to_spi_blkbuf(Taddr,0,0, E_WRITE, &spi_blk_buf[0]);
-
+		
 			memcpy(&spi_blk_buf[3+12],    &dataBuffer[0+Taddr*DPD_AREA0_WR_UNIT_DATA_LEN],   4);
 			memcpy(&spi_blk_buf[3+12+16], &dataBuffer[0+Taddr*DPD_AREA0_WR_UNIT_DATA_LEN+4], 4);
-
+			
 			ispi_tx_big_block(spi_blk_buf, SPI_BLK_LEN);
-
+			
 			calc_area_u32_check_sum(&area_check.area_imx_w_check, &spi_blk_buf[3], 32);
         }
-
+		
 		//area_check
 		area_check.area_fpga_w_check = read_fpga_area_u32_check_sum(E_CHECK_FOR_WIRTE);
 		if(area_check.area_imx_w_check != area_check.area_fpga_w_check){
@@ -535,11 +535,11 @@ static int load_file_and_write_area(void)
 		else{
 			printf("a0 [u32_check]:imx_w_check and fpga_w_check [0x%04x 0x%04x]!\n", area_check.area_imx_w_check, area_check.area_fpga_w_check);
 		}
-
+		
 		fpga_byte_write(DPD_SEG,0x40,0);
         log_printf(LOG_DEBUG, I_USER_CFG, "<< end area0\n");
 
-
+		
 
 		//-------------------------------------------------------------------------------
     	//区域1
@@ -547,21 +547,21 @@ static int load_file_and_write_area(void)
 		clear_check_sum(&area_check);
 		fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE|MASK_TO_FPGA_CHECK_CLEAR);
 		fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE);
-
+		
         fpga_byte_write(DPD_SEG,0x40,MASK_DPD_DATA_AREA1_MODE);
-
+		
         for(Taddr=0;Taddr<=15;Taddr++){
 
 			memset(spi_blk_buf, 0, sizeof(spi_blk_buf));
 			write_unit_area_addr_to_spi_blkbuf(Taddr,0,0, E_WRITE, &spi_blk_buf[0]);
-
+		
 			memcpy(&spi_blk_buf[3], &dataBuffer[1024+Taddr*DPD_AREA1_WR_UNIT_DATA_LEN], DPD_AREA1_WR_UNIT_DATA_LEN);
 
 			ispi_tx_big_block(spi_blk_buf, SPI_BLK_LEN);
-
+			
 			calc_area_u32_check_sum(&area_check.area_imx_w_check, &spi_blk_buf[3], 32);
         }
-
+		
 		//area_check
 		area_check.area_fpga_w_check = read_fpga_area_u32_check_sum(E_CHECK_FOR_WIRTE);
 		if(area_check.area_imx_w_check != area_check.area_fpga_w_check){
@@ -599,18 +599,18 @@ static int load_file_and_write_area(void)
 	    fpga_byte_write(DPD_SEG,0x40,MASK_DPD_DATA_AREA3_MODE);
 
 	    for(Iaddr=0; Iaddr<=511; Iaddr++){
-
+			
 			memset(spi_blk_buf, 0, sizeof(spi_blk_buf));
 			write_unit_area_addr_to_spi_blkbuf(0,Iaddr,0, E_WRITE, &spi_blk_buf[0]);
-
+		
 			memcpy(&spi_blk_buf[3+12],    &dataBuffer[Iaddr*DPD_AREA3_WR_UNIT_DATA_LEN],   4);
 			memcpy(&spi_blk_buf[3+12+16], &dataBuffer[Iaddr*DPD_AREA3_WR_UNIT_DATA_LEN+4], 4);
-
+			
 			ispi_tx_big_block(spi_blk_buf, SPI_BLK_LEN);
 
 			calc_area_u32_check_sum(&area_check.area_imx_w_check, &spi_blk_buf[3], 32);
 	    }
-
+		
 		//area_check
 		area_check.area_fpga_w_check = read_fpga_area_u32_check_sum(E_CHECK_FOR_WIRTE);
 		if(area_check.area_imx_w_check != area_check.area_fpga_w_check){
@@ -643,22 +643,22 @@ static int load_file_and_write_area(void)
 	    area2_cnt=0;
 
 	    fpga_byte_write(DPD_SEG,0x40,MASK_DPD_DATA_AREA2_MODE);
-
+		
 	    log_printf(LOG_DEBUG, I_USER_CFG, "\n\n[area2] start read area2 data.\n");
 		clear_check_sum(&area_check);
 		fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE|MASK_TO_FPGA_CHECK_CLEAR);
 		fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE);
-
+		
 	    for(Taddr=0;Taddr<=8;Taddr++) {//8
 	        for(Raddr=0;Raddr<=3;Raddr++) {//3
 				if(Raddr==2)
 			  	  continue;
-
+				
 				if(Raddr==3)
 			  	    Iaddr_Max = 127;
 			    else
 			  	    Iaddr_Max = 1023;//1023
-
+				
 	            for(Iaddr=0; Iaddr<=Iaddr_Max; Iaddr++) {
 	                area2_cnt++;
 
@@ -688,14 +688,14 @@ static int load_file_and_write_area(void)
 					memset(spi_blk_buf, 0, sizeof(spi_blk_buf));
 					write_unit_area_addr_to_spi_blkbuf(Taddr,Iaddr,Raddr, E_WRITE, &spi_blk_buf[0]);
 					memcpy(&spi_blk_buf[3], &dataBuffer[bufOffset*DPD_AREA2_WR_UNIT_EXT_DATA_LEN], DPD_AREA2_WR_UNIT_EXT_DATA_LEN);
-
+					
 					if(Raddr==3){//Iaddr(0~127)-IQ(28bit)
 						memset(&spi_blk_buf[3],   0, 12);
 						memset(&spi_blk_buf[3+16],0, 12);
 						spi_blk_buf[3+12]      =spi_blk_buf[3+12]&0x0f;
 						spi_blk_buf[3+12+16]   =spi_blk_buf[3+12+16]&0x0f;
 					}
-					else{//IQ(106bit) (13byte+2bit)
+					else{//IQ(106bit) (13byte+2bit) 
 						memset(&spi_blk_buf[3],   0, 2);
 						memset(&spi_blk_buf[3+16],0, 2);
 						spi_blk_buf[3+2]      =spi_blk_buf[3+2]&0x03;
@@ -705,7 +705,7 @@ static int load_file_and_write_area(void)
 					ispi_tx_big_block(spi_blk_buf, SPI_BLK_LEN);
 
 					calc_area_u32_check_sum(&area_check.area_imx_w_check, &spi_blk_buf[3], 32);
-
+					
 	                bufOffset++;
 	                byte32Cnt++;
 
@@ -744,7 +744,7 @@ CKECK_WRITE_ERR_PROC:
     if(ret<0){
 		fpga_byte_write(DPD_SEG,0x40,0);
 		fpga_byte_write(DPD_SEG,0x41,0);
-
+		
 		st_extend_state.display_stop=E_DISPLAY_STOP;
 	  	delay_ms(500);
 		while(1){
@@ -763,7 +763,7 @@ CKECK_WRITE_ERR_PROC:
 		}
 
 		fpga_byte_write(DPD_SEG,0x41, 0);
-
+		
         lcd_write_string(LINE_1,0,"         ADPC data load error!       [9]");
         lcd_write_string(LINE_2,0,"                                        ");
 		lcd_write_cache();
@@ -824,7 +824,7 @@ static int read_area_and_store_file()
 	S_CHECK_SUM area_check={0};
 
 	fpga_byte_write(DPD_SEG,0x41, MASK_TO_SPI_WR_RD_ENABLE);
-
+	
 
     atsc_para.system_para.adpc_err = DPD_SAVE_DATA;
     lcd_write_string(LINE_1,0," WAIT A MOMENT ....                     ");
@@ -836,18 +836,18 @@ static int read_area_and_store_file()
 
     //区域0+1
 	//----------------------------------------------------------------------------------
-
+	
 	//区域0
 	if(1){
 	    log_printf(LOG_DEBUG, I_USER_CFG, "\n\n[area0]start read area0 data.\n");
 	    memset(&dataBuffer[0],0,sizeof(dataBuffer));
 
 	    fpga_byte_write(DPD_SEG,0x40, MASK_DPD_DATA_AREA0_MODE);
-
+		
 		clear_check_sum(&area_check);
 		fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE|MASK_TO_FPGA_CHECK_CLEAR);
 		fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE);
-
+		
 	    for(Taddr=0;Taddr<=31;Taddr++){
 			memset(spi_blk_buf, 0, sizeof(spi_blk_buf));
 			write_unit_area_addr_to_spi_blkbuf(Taddr,0,0, E_READ, &spi_blk_buf[0]);
@@ -865,7 +865,7 @@ static int read_area_and_store_file()
 			dpd_ck_status=CK_WR_ERR;
 			goto CKECK_READ_ERR_PROC;
 		}
-
+		
 		fpga_byte_write(DPD_SEG,0x40,0);
 	}
 
@@ -875,17 +875,17 @@ static int read_area_and_store_file()
 	if(1){
 	    log_printf(LOG_DEBUG, I_USER_CFG, "\n\n[area1]start read area1 data.\n");
 	    fpga_byte_write(DPD_SEG,0x40,MASK_DPD_DATA_AREA1_MODE);
-
+		
 		clear_check_sum(&area_check);
 		fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE|MASK_TO_FPGA_CHECK_CLEAR);
 		fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE);
-
+		
 	    for(Taddr=0;Taddr<=15;Taddr++){
 			memset(spi_blk_buf, 0, sizeof(spi_blk_buf));
 			write_unit_area_addr_to_spi_blkbuf(Taddr,0,0, E_READ, &spi_blk_buf[0]);
 			ispi_rx_big_block(spi_blk_buf, SPI_BLK_LEN);
 			calc_area_u32_check_sum(&area_check.area_imx_r_check, &spi_blk_buf[3], 32);
-
+			
 			memcpy(&dataBuffer[1024+Taddr*DPD_AREA1_WR_UNIT_DATA_LEN], &spi_blk_buf[3], DPD_AREA1_WR_UNIT_DATA_LEN);
 	    }
 		//area_check
@@ -896,10 +896,10 @@ static int read_area_and_store_file()
 			dpd_ck_status=CK_WR_ERR;
 			goto CKECK_READ_ERR_PROC;
 		}
-
+	    
 		fpga_byte_write(DPD_SEG,0x40,0);
 	}
-
+	
 	rw_e2rom_dpd(RW_ADPC_SAVE,E_DPD_AREA_FIRST_4K,0,&dataBuffer[0]);
 
 
@@ -910,11 +910,11 @@ static int read_area_and_store_file()
 		memset(&dataBuffer[0],0,sizeof(dataBuffer));
 
         fpga_byte_write(DPD_SEG,0x40, MASK_DPD_DATA_AREA3_MODE);
-
+		
 		clear_check_sum(&area_check);
 		fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE|MASK_TO_FPGA_CHECK_CLEAR);
 		fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE);
-
+		
         for(Iaddr=0;Iaddr<=511;Iaddr++){
 			memset(spi_blk_buf, 0, sizeof(spi_blk_buf));
 			write_unit_area_addr_to_spi_blkbuf(0,Iaddr,0, E_READ, &spi_blk_buf[0]);
@@ -938,7 +938,7 @@ static int read_area_and_store_file()
     }
 
 
-
+	
 	st_extend_state.display_stop=E_DISPLAY_START;
 	atsc_para.system_para.save_load_data_percent = 0;
 
@@ -959,21 +959,21 @@ static int read_area_and_store_file()
 
 	  Iaddr_Max = 1023;
       fpga_byte_write(DPD_SEG,0x40, MASK_DPD_DATA_AREA2_MODE);
-
+	  
 	  clear_check_sum(&area_check);
 	  fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE|MASK_TO_FPGA_CHECK_CLEAR);
 	  fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE);
-
+	  
       for(Taddr=0; Taddr<=8; Taddr++){
 	      for(Raddr=0; Raddr<=3; Raddr++){
 		  	  if(Raddr==2)
 			  	  continue;
-
+			  
 			  if(Raddr==3)
 			  	  Iaddr_Max = 127;
 			  else
 			  	  Iaddr_Max = 1023;
-
+			  
 	          for(Iaddr=0; Iaddr<=Iaddr_Max; Iaddr++){
 	              area2_cnt++;
 
@@ -1001,11 +1001,11 @@ static int read_area_and_store_file()
 	                  saveOffset++;
 
 	                  Num=100*byte32Cnt/(19584);
-
+					  
 	                  //sprintf((char*)temp_buf,"%02d%%   %d",Num,flash_get_err_time());
 	                  //log_printf(LOG_DEBUG,I_NOUSED,"%02d%%   4kByte-write to file\n",Num);
 	                  atsc_para.system_para.save_load_data_percent = Num;
-
+					  
 					  //area_check
 					  area_check.area_fpga_r_check = read_fpga_area_u32_check_sum(E_CHECK_FOR_RAED);
 					  if(area_check.area_imx_r_check != area_check.area_fpga_r_check){
@@ -1032,7 +1032,7 @@ static int read_area_and_store_file()
 			  goto CKECK_READ_ERR_PROC;
 		 }
       }
-
+	  
 	  atsc_para.system_para.save_load_data_percent = 100*(byte32Cnt)/(19584);
       printf("[read-end]read finished. area2_cnt=%d\n",area2_cnt);
 	  fpga_byte_write(DPD_SEG,0x40, 0);
@@ -1051,7 +1051,7 @@ static int read_area_and_store_file()
 	st_extend_state.display_stop=E_DISPLAY_STOP;
   	delay_ms(500);
 	while(1){
-
+		
 		if(st_extend_state.display_stop==E_DISPLAY_END){
 			printf(" mthr check display_stoped \n");
 			break;
@@ -1064,13 +1064,13 @@ static int read_area_and_store_file()
 			break;
 		}
 	}
-
+	
 
 CKECK_READ_ERR_PROC:
     if(dpd_ck_status==CK_WR_ERR){
 		fpga_byte_write(DPD_SEG,0x40, 0);
 		fpga_byte_write(DPD_SEG,0x41, 0);
-
+	
 		//sync display
 		st_extend_state.display_stop=E_DISPLAY_STOP;
 	  	delay_ms(500);
@@ -1128,10 +1128,10 @@ int dpd_curve_proc(uint8 proc_mode)
 
         time_stop = get_current_time_ms();
         log_printf(LOG_INFO, I_SYS_STATUS, "{time cal to mcu} total_time=%ds ret=%d\n",(time_stop-time_start)/1000, ret);
-
+		
         //u_size = usr_get_file_size();
         //log_printf(LOG_DEBUG, I_USER_CFG, "file size=%d\n",u_size);
-
+		
     }
     else if(proc_mode == E_LOAD_TO_FPGA)
     {
@@ -1151,7 +1151,7 @@ int dpd_curve_proc(uint8 proc_mode)
 
         time_stop = get_current_time_ms();
         log_printf(LOG_INFO, I_SYS_STATUS, "{time_cal to FPGA} total_time=%ds ret=%d\n",(time_stop-time_start)/1000, ret);
-
+        
 
         //fpga_byte_write(0x01, 0x26, 1);  // RF set ON
         //printf("ON RF\n");
@@ -2303,7 +2303,7 @@ void refresh_update_dpd(void *parg,void *parv)
                     else{//AUTO
                     	if(stc_insert_step==0){
 							stc_insert_step  = 1;
-
+							
 							//1. 在4结束后，lin_update_set = 0, 同时把0x21的bit7 设置为1。其它都不动；
 							dpd_ctl2_reg = (DPD_CTRL2_AMP_CHK | DPD_CTRL2_POLYESTI_UPDATE);
                     		fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg);//0x21
@@ -2311,12 +2311,12 @@ void refresh_update_dpd(void *parg,void *parv)
 						}
 
 						if(sec_cnt >= 90+5){
-
+							
 							//2. 过个5秒左右，0x21 的bit7 设置为0，然后进入状态5；
 							dpd_ctl2_reg = (DPD_CTRL2_AMP_CHK );
                     		fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg);//0x21
                     		printf("phase4 end set Reg0x21=0x%x\n", dpd_ctl2_reg);
-
+							
 	                        g_query_operate=0;
 	                        psys->dpd_phase=5;
 	                        sec_cnt       = 0;
@@ -2930,7 +2930,7 @@ DPD_SAVE_PROC:
         fpga_byte_write(5,FPGA_ADDR_DPD_CTRL1, 0);
         fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, 0);
 		u_dpdctl_r23.u8val = 0;
-		u_dpdctl_r23.dpd_bt.rf_sel = DPD_RF_SEL_VALUE(E_SELECT_A);
+		u_dpdctl_r23.dpd_bt.rf_sel = DPD_RF_SEL_VALUE(E_SELECT_A);
         fpga_byte_write(5,FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val);
         log_printf(LOG_DEBUG, I_USER_CFG, "[update] success --- u_dpdctl_r23=0x%x\n", u_dpdctl_r23.u8val);
 
@@ -2987,10 +2987,10 @@ DPD_SAVE_PROC:
         reset_dpd_to_normal_state();
 
         /* 恢复冷启动后的ORx FAGC实时跟踪状态。 */
-        boot_cfg_fagc_update();
+        /*boot_cfg_fagc_update();
 
         log_printf(LOG_INFO, I_USER_CFG,
-                   "[DPD] update complete, ORx FAGC tracking restored\n");
+                   "[DPD] update complete, ORx FAGC tracking restored\n");*/
 
         psys->final_stage = 0xff;
 

src/atsc_app/bsp/isys_config.c

@@ -980,8 +980,7 @@ void fpga_para_init(void)
     {
 		if(atsc_para.rf_para.rf && (adrv9009_set_tx_path_enable(1) != OK))
 		{
-			log_printf(LOG_ERR, I_SYS_STATUS,
+			log_printf(LOG_ERR, I_SYS_STATUS, "ADRV9009 TX enable failed, continue restoring requested RF state\n");
-					   "ADRV9009 TX enable failed, continue restoring requested RF state\n");
 		}
 		fpga_boot_rf_hold_release();
     }