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新增：FPGA 升级后热恢复射频链路

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This commit is contained in:
rfeng
2026-08-28 13:26:45 +08:00
parent 47b782e976
commit 33d8f4f428
7 changed files with 257 additions and 93 deletions
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src/atsc_app/task/http_get.c
+8 -10
View File
@@ -1055,15 +1055,14 @@ void http_write_sys(S_CGI_SET *ppara)
}
if(ppara->sys_reset) {
log_printf(LOG_DEBUG, I_USER_CFG, "SYSTEM RESET NOW (IMX+FPGA)!!!!!!!!!!!!!\n");
//复位 FPGA本身复位
fpga_byte_write(0x01,0xfe,0x5a);
fpga_byte_write(0x01,0xfe,0xa5);
// [one@20220419 add imx reset]
system("sync");
system("reboot");
}
/* A Web System Reset is an IMX warm reboot. Keep FPGA, AD9528 and
* ADRV9009 powered so the normal boot path can preserve the RF link. */
log_printf(LOG_DEBUG, I_USER_CFG,
"WEB SYSTEM RESET NOW (IMX warm reboot, keep RF hardware)\n");
system("sync");
system("reboot");
return;
}
}
@@ -1624,4 +1623,3 @@ void http_save_change_para(void *p)
/*****************************END**************************************/
src/atsc_app/task/iweb_task.c
+4 -1
View File
@@ -1576,8 +1576,8 @@ int get_tsoip_systs1(char *pbuf, short bufMaxLen)
((pnet->udp_rtp&0xff)<<16)|((pnet->packet_len&0xff)<<8)|(pnet->receive_type&0xff),
pnet->fec,
pnet->delay,
pnet->col,
pnet->row,
pnet->col,
pnet->dest_ip[0],
(pnet->dest_ip[1]<<16)|(pnet->dest_ip[2]<<8)|pnet->dest_ip[3],
pnet->dest_port,
@@ -1777,6 +1777,9 @@ int start_fpga_upgrade(char *value,short maxlen)
return 0;
}
log_printf(LOG_INFO, I_USER_CFG, "get FPGA .mcs upgrade cmd from web.\n");
/* Clear the previous request's terminal status before the asynchronous
* imx_up_thr starts. Otherwise the web poll can consume a stale DONE. */
fpga_up_write_status("PENDING", 0, 0);
set_fpga_up_flg(1);
return 0;
}
src/atsc_app/task/tcp_task.c
+4 -4
View File
@@ -863,7 +863,7 @@ static uint32 fpga_upgrade_process(void)
#define FPGA_UP_STATUS_PATH "/tmp/fpga_up_status"
/* Publish flash progress for the web page: one line "<PHASE> <PCT> <RET>".
* PHASE: PENDING|ERASE|WRITE|DONE|ERROR ; fpga_up_status.cgi serves this file. */
* PHASE: PENDING|ERASE|WRITE|RELINK|READY|ERROR ; fpga_up_status.cgi serves this file. */
void fpga_up_write_status(const char *phase, int pct, int ret)
{
FILE *sf = fopen(FPGA_UP_STATUS_PATH, "w");
@@ -990,7 +990,7 @@ int fpga_upgrade_from_file(const char *path)
delay_ms(200);
}
g_now_only_upgrade_fpga = 0;
if(ret == 0) fpga_up_write_status("DONE", 100, 0);
if(ret == 0) fpga_up_write_status("RELINK", 100, 0);
else fpga_up_write_status("ERROR", last_pct < 0 ? 0 : last_pct, ret);
log_printf(LOG_DEBUG, I_NOUSED, "fpga upgrade: finished ret=%d lines=%d\n", ret, upState.lineCnt);
return ret;
@@ -2174,8 +2174,8 @@ void check_fpga_up_finished_reboot_sys(void)
fpga_up_sys_reboot=0;
sec_cnt=0;
/* PR10: the FPGA update image was already IPROG-loaded by reset_fpga_system() in
* check_fpga_upgrade_done(). The old reset_imx_system() reboot is a no-op on this
* board (Task10: no HW soft-reboot path). Instead re-establish RF in-place: reconfig
* check_fpga_upgrade_done(). An IMX reboot is unnecessary for an FPGA-only update.
* Re-establish RF in-place: reconfig
* the FPGA + re-handshake the JESD link (skip 9009, which stayed powered) + reload the
* DPD HOLD curve. This makes a web FPGA .mcs upgrade self-recover WITHOUT a power cycle. */
extern void hot_reinit_rf(int reload_fpga);
src/atsc_app/task/upgrade.c
+14 -5
View File
@@ -59,6 +59,7 @@ extern int g_trigger_up_start_flg;
static volatile int g_hot_relink_busy = 0; /* re-entrancy guard: only one relink at a time
* (the upgrade-completion path and the runtime
* cfg_valid poll can both request one). */
static volatile int g_fpga_upgrade_relink_pending = 0; /* web upgrade waits for RF relink */
void hot_reinit_rf(int reload_fpga)
{
extern uint8 hot_get_adpc_mode(void);
@@ -70,6 +71,8 @@ void hot_reinit_rf(int reload_fpga)
return;
}
g_hot_relink_busy = 1;
if(g_fpga_upgrade_relink_pending)
fpga_up_write_status("RELINK", 100, 0);
prev_adpc = hot_get_adpc_mode(); /* capture DPD mode BEFORE force-stop wipes it */
log_printf(LOG_INFO, I_USER_CFG, "[HOT-RESTART] begin (reload_fpga=%d, jesd-relink, skip TALISE, prev_adpc=%d)\n", reload_fpga, prev_adpc);
@@ -105,6 +108,10 @@ void hot_reinit_rf(int reload_fpga)
hot_dpd_rearm(prev_adpc);
}
log_printf(LOG_INFO, I_USER_CFG, "[HOT-RESTART] done\n");
if(g_fpga_upgrade_relink_pending){
fpga_up_write_status("READY", 100, 0);
g_fpga_upgrade_relink_pending = 0;
}
g_hot_relink_busy = 0;
}
@@ -125,10 +132,9 @@ void sys_upgrade(void)
result = atoi(msg);
//usleep(1000000);
if(result == 0){
log_printf(LOG_DEBUG,I_NOUSED,"run upgrade sh, and will reboot\n");
log_printf(LOG_DEBUG,I_NOUSED,"run upgrade sh (kernel/DTB -> reboot, userspace-only -> app restart)\n");
system(DO_UPGRADE_RUN);
log_printf(LOG_DEBUG,I_NOUSED,"system rebooting....\n");
// reboot in runme.sh
log_printf(LOG_DEBUG,I_NOUSED,"upgrade script started restart/reboot flow\n");
}
}
}
@@ -165,8 +171,11 @@ void* imx_up_thr(void * args)
atsc_adpc_force_stop_flag = TRUE;
usleep(2000000);
int fret = fpga_upgrade_from_file(FPGA_UP_MCS_PATH);
log_printf(LOG_DEBUG,I_NOUSED,"FPGA upgrade result=%d (0=ok, app will reset+reboot)\n", fret);
/* success path: check_fpga_upgrade_done() set fpga_up_sys_reboot=1 -> imx6 reboots */
if(fret == 0)
g_fpga_upgrade_relink_pending = 1;
log_printf(LOG_DEBUG,I_NOUSED,"FPGA upgrade result=%d (0=ok, app will hot-relink RF)\n", fret);
/* Success path uses fpga_up_sys_reboot as a legacy delayed-work flag;
* check_fpga_up_finished_reboot_sys() now performs an in-place RF relink. */
}
/* test hook: `touch /tmp/hot_restart_now` (or `echo 1 > ...` for reload_fpga) triggers