diff --git a/src/atsc_app/bsp/dpd_proc.c b/src/atsc_app/bsp/dpd_proc.c index f8ba5de..99751a6 100755 --- a/src/atsc_app/bsp/dpd_proc.c +++ b/src/atsc_app/bsp/dpd_proc.c @@ -1,1857 +1,1858 @@ - -#include -#include -#include -#include -#include -#include -#include - -#include "../inc/i2c_drv.h" -#include "../inc/os_task.h" -#include "../inc/type.h" -#include "../inc/lcd_task.h" -#include "../inc/sys_config.h" -#include "../inc/delay.h" -#include "../inc/fpga.h" -#include "../inc/eeprom.h" -#include "../inc/dpd_proc.h" -#include "../inc/type.h" -#include "../inc/general_api.h" -#include "../inc/flash.h" -#include "../inc/isys_com.h" - - - - -#define DPD_DATA_FILE "/aw/anywave/dpd_curve/dpd_data.dat" -#define USE_PHASE_78910 (1) - -/* 相1/相7 的 AGC 分两段跑，前半段粗调、后半段细调。 - * - * SMOD 的 FAGC 驱动的是 ADRV9009 的射频增益索引(0.43dB 量化台阶 + 2dB 死区)， - * 不是 EMV7.1 那个连续 DAC。FAGC 每跳一格，就是往 DAGC 的输入上注入一个 0.43dB - * 阶跃，DAGC 只能跟着追。两个都开到相位结束，DAGC 常常还没 settle 就被下一相冻结： - * 实测相7结束时 rx_dgain=2108 而不是标称的 2048(+0.25dB 残差)，这个残差一路带到 - * 相9/相10，最后只能靠相6/相10 的 DPD 幅度整形去补，表现为功率波动。 - * - * 所以前 FAGC_LOCK_SEC 秒 FAGC+DAGC 一起跑(粗调)，之后锁死 FAGC，把剩下的时间 - * 全留给 DAGC 单独收敛(细调)。相1/相7 各 20s，这里取中点。 - * - * boot_tsnr_update() / update_tsnr_uimd_limd() 的相7 原本只有 2~3s，切不出像样的 - * 两段，所以一并延长到 FAGC_PH7_SHORT_SEC，按 FAGC_LOCK_SEC_SHORT 切分。 - */ -#define FAGC_LOCK_SEC (10) -#define FAGC_LOCK_SEC_SHORT (2) -#define FAGC_PH7_SHORT_SEC (5) - - -enum{PHASE6_SET_SAVE=1,PHASE10_SET_SAVE,WPP_SET_SAVE}; - -//----------------------------------------- - -extern pthread_mutex_t mtx_phase78910_again; -extern int g_trigger_up_tsnr_flg; -extern int g_trigger_up_start_flg; - -extern uint32 adpc_source_udp; -extern uint32 adpc_source_web; -extern pthread_mutex_t mux_dpd_wr_ck; -extern uint8 g_remote_dpd_ctrl; - -extern char out_str[52]; -extern S_ATSC_PARA atsc_para; -extern BOOL atsc_adpc_force_stop_flag; -extern uint8 dataBuffer[LEN_ADPC_DATE_BUF+4]; -extern S_EXTEND_SYS_STATE st_extend_state; -extern volatile uint8 g_query_operate; -extern volatile uint8 g_query_save; -extern volatile uint8 g_query_skip; -extern volatile uint8 g_query_wpp_to_save; - - -extern uint32 task_resume_ignore_chk(uint32 task_id); -extern uint32 flash_get_err_time(void); -extern void set_boot_tsnr_up_state(uint8 sta); - -extern uint32 auto_update; -extern S_CHECK_SIGNAL s_check_signal; -extern S_UPDATE_AUTO_ADPC update_adpc_para_flag; - -//----------------------------------------- -u8 spi_blk_buf[SPI_BLK_LEN]; - -static U_DPDCTL_REG23 u_dpdctl_r23; -u32 dpd_total_w_cnt=0; -u32 dpd_total_r_cnt=0; -int time_start=0; -int time_stop=0; - -FILE *p_dpd_log_fp = NULL; -uint8 dpd_ck_status = CK_OK; - -char str_safe[2][2]={" ","s"}; -static uint16 g_wpp_max; //wpp保护状态 -static uint8 g_query_save_flg=0; - -//----------------------------------------- - - - -/* -Normal State: RF_AFTER + AGC_OFF + DCRM_OFF + IQB_OFF -*/ -void reset_dpd_to_normal_state(void) -{ - //printf("reset_dpd_to_normal_state\n"); - u_dpdctl_r23.u8val = 0; - u_dpdctl_r23.dpd_bt.iqb_upd = 0; - u_dpdctl_r23.dpd_bt.rf_sel = 0; //A - u_dpdctl_r23.dpd_bt.sync_mode = 1; - fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); - log_printf(LOG_DEBUG, I_USER_CFG, "reset set seg5-23 IQBval=0x%x\n",u_dpdctl_r23.u8val); - //fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, 0); -} - -void write_unit_area_addr_to_spi_blkbuf(uint8 Taddr,uint16 Iaddr,uint8 Raddr, u8 wr_rd, u8 *pblk) -{ - if(wr_rd==0)//rd - pblk[0] = 0x7f & (((Raddr&0x3)<<2) | ((Iaddr>>8)&0x3)); - else//wr - pblk[0] = 0x80 | (((Raddr&0x3)<<2) | ((Iaddr>>8)&0x3)); - - pblk[1] = Iaddr&0xff; - pblk[2] = Taddr; -} - -//---->>>>---------------------------- -//区域读数据的地址和数据长度定义--不可改动 -#define DPD_AREA0_WR_UNIT_DATA_LEN 8 -#define DPD_AREA1_WR_UNIT_DATA_LEN 32 -#define DPD_AREA3_WR_UNIT_DATA_LEN 8 -#define DPD_AREA2_WR_UNIT_EXT_DATA_LEN 32 - -//----<<<<---------------------------- -static uint8 gb_addr_auto_inc=1; - -void set_dpd_unit_area_auto_inc(uint8 inc_flg) -{ - gb_addr_auto_inc = inc_flg&0x1; -} -uint8 get_dpd_unit_area_auto_inc() -{ - return gb_addr_auto_inc; -} - - -void clear_dpd_data_file(void) -{ - char cmd[300]; - - log_printf(LOG_DEBUG, I_USER_CFG, "clear dpd_data file. %s\n", DPD_DATA_FILE); - - memset(cmd, 0, sizeof(cmd)); - sprintf(cmd, "rm -rf %s",DPD_DATA_FILE); - system(cmd); -} - -u32 usr_get_file_size(void) -{ - FILE *fp; - u32 len; - - fp = fopen(DPD_DATA_FILE, "rb"); - - fseek(fp, 0, SEEK_END); - len = ftell(fp); - - fclose(fp); - return len; -} - -int get_current_time_ms(void) -{ - struct timeval tv; - gettimeofday(&tv, NULL); - return (tv.tv_sec*1000+tv.tv_usec/1000); - //printf("time: %d.%d\n",tv.tv_sec,tv.tv_usec/1000); -} - -int usr_read_file(u8 *pbuf, u32 pos, u32 len,int *perr) -{ - FILE *fp; - u32 i; - int retLen=0; - int ret=0; - - if(len>4096)return -1; - *perr=0; - - fp = fopen(DPD_DATA_FILE, "rb"); - if(NULL == fp) - { - *perr=-2; - log_printf(LOG_ERR, I_USER_CFG, "open dpd file [%s] failed.\n", DPD_DATA_FILE); - return -2; /* 要锟斤拷锟截达拷锟斤拷锟斤拷锟?*/ - } - - //log_printf(LOG_DEBUG, I_USER_CFG, "seek pos=%d ret=%d\n",pos,ret); - - ret = fseek(fp, pos, SEEK_SET); - if(ret<0){ - log_printf(LOG_ERR, I_USER_CFG, "Read File Seek err.\n"); - *perr=-3; - } - else - { - //printf("\n\n\nseek pos=%d ret=%d\n",pos*4,ret); - retLen = fread(pbuf,sizeof(u8),len,fp); - if(retLen<0){ - *perr=-2; - log_printf(LOG_ERR, I_USER_CFG, "retLen<0\n"); - } - else if(retLen!=len) - { - if(feof(fp)){ - log_printf(LOG_ERR, I_USER_CFG, "File read end.\n"); - *perr=1; - } - else{ - log_printf(LOG_ERR, I_USER_CFG, "File read err. retLen=%d,wantLen=%d.\n",retLen, len); - *perr=-1; - } - } - else - *perr=0; - } - - fclose(fp); - - return retLen; -} - - -int usr_write_file(u8 *pbuf,u32 len) -{ - FILE *fp; - u32 i; - - fp = fopen(DPD_DATA_FILE, "ab+"); - if(NULL == fp) - { - return -2; /* 要锟斤拷锟截达拷锟斤拷锟斤拷锟?*/ - } - - fwrite(pbuf,sizeof(u8),len,fp); - fclose(fp); - - return 0; -} - -int usr_write_data_file(u8 *pbuf, u32 len, u8 *pfile_name) -{ - FILE *fp; - u32 i; - - fp = fopen(pfile_name, "ab+"); - if(NULL == fp) - { - return -2; /* 要锟斤拷锟截达拷锟斤拷锟斤拷锟?*/ - } - - fwrite(pbuf, sizeof(u8), len,fp); - fclose(fp); - - return 0; -} - - - -uint32 rw_e2rom_dpd(uint32 kind,uint32 block,uint32 addr_k_cnt,uint8 *ptr) -{ - uint8 *pData = ptr; - uint32 rw_len = 0; - uint32 address = 0; - uint16 crc = 0; - uint16 crc_read = 0; - - - uint32 retry_time = 0; - int err_sta = 0; - int fread_len; - - - int start_time; - int end_time; - - if(kind==RW_ADPC_SAVE)//保存曲线 - { - if(block==E_DPD_AREA_FIRST_4K){ - log_printf(LOG_DEBUG, I_USER_CFG, "[store] start to sotre first 4k\n"); - address = 0; - - start_time = get_current_time_ms(); - usr_write_file(pData, LEN_ADPC_DATE_BUF); - end_time = get_current_time_ms(); - log_printf(LOG_DEBUG, I_USER_CFG, "file_4k time=%d\n",end_time-start_time); - //flash_write_buf(pData,LEN_ADPC_DATE_BUF,address); - } - //-------------------------------- - else if(block==E_DPD_AREA3){ - log_printf(LOG_DEBUG, I_USER_CFG, "[store] start to sotre area3\n"); - address = 0; - - start_time = get_current_time_ms(); - usr_write_file(pData, LEN_ADPC_DATE_BUF); - end_time = get_current_time_ms(); - log_printf(LOG_DEBUG, I_USER_CFG, "area3 time=%d\n",end_time-start_time); - } - //-------------------------------- - else if(block==2) - { - //printf("[store] start to sotre other 4k\n"); - //每次存储4k数据 - //address = (addr_k_cnt+1)*4096; - usr_write_file(pData, LEN_ADPC_DATE_BUF); - } - } - else if(kind==RW_ADPC_LOAD)//读取曲线 - { - if(block==E_DPD_AREA_FIRST_4K) - { - address = 0; - - //flash_read_buf(pData,LEN_ADPC_DATE_BUF,address); - rw_len = usr_read_file(pData,address,LEN_ADPC_DATE_BUF,&err_sta); - } - //-------------------------------- - else if(block==E_DPD_AREA3) - { - address = (addr_k_cnt+1)*4096; - - //flash_read_buf(pData,LEN_ADPC_DATE_BUF,address); - rw_len = usr_read_file(pData,address,LEN_ADPC_DATE_BUF,&err_sta); - } - //-------------------------------- - else if(block==2) - { - address = (addr_k_cnt+2)*4096; // (addr_k_cnt+1)*4096 - - //flash_read_buf(pData,LEN_ADPC_DATE_BUF,address); - rw_len = usr_read_file(pData,address,LEN_ADPC_DATE_BUF,&err_sta); - } - } - return rw_len; -} - - -static void * display_save_load_percent_thr(void * args) -{ - u8 ret_code=0; - char temp_buf[20]; - static u32 x_time_cnt = 0; - printf("enter display\n"); - - x_time_cnt = 0; - while(1){ - log_printf(LOG_DEBUG, I_USER_CFG, "%02d%% \n", atsc_para.system_para.save_load_data_percent); - memset(temp_buf,0,sizeof(temp_buf)); - sprintf((char*)temp_buf,"%02d%% ",atsc_para.system_para.save_load_data_percent); - - lcd_write_string(1,15,(uint8*)temp_buf); - lcd_write_cache(); - - if(st_extend_state.display_stop==E_DISPLAY_STOP){ - ret_code=2; - break; - } - - x_time_cnt++; - if(x_time_cnt >= 200){//40/0.25 - ret_code=3; - break; - } - - usleep(250*1000); - }; - - - printf(" thr exit display %d, display_sta=%d [0-start,2-stop]\n", ret_code, st_extend_state.display_stop); - st_extend_state.display_stop = E_DISPLAY_END; -} -static int thr_display_percent_thread(void) +#include +#include +#include +#include +#include +#include +#include + +#include "../inc/i2c_drv.h" +#include "../inc/os_task.h" +#include "../inc/type.h" +#include "../inc/lcd_task.h" +#include "../inc/sys_config.h" +#include "../inc/delay.h" +#include "../inc/fpga.h" +#include "../inc/eeprom.h" +#include "../inc/dpd_proc.h" +#include "../inc/type.h" +#include "../inc/general_api.h" +#include "../inc/flash.h" +#include "../inc/isys_com.h" + + + + +#define DPD_DATA_FILE "/aw/anywave/dpd_curve/dpd_data.dat" +#define USE_PHASE_78910 (1) + +/* 相1/相7 的 AGC 分两段跑，前半段粗调、后半段细调。 + * + * SMOD 的 FAGC 驱动的是 ADRV9009 的射频增益索引(0.43dB 量化台阶 + 2dB 死区)， + * 不是 EMV7.1 那个连续 DAC。FAGC 每跳一格，就是往 DAGC 的输入上注入一个 0.43dB + * 阶跃，DAGC 只能跟着追。两个都开到相位结束，DAGC 常常还没 settle 就被下一相冻结： + * 实测相7结束时 rx_dgain=2108 而不是标称的 2048(+0.25dB 残差)，这个残差一路带到 + * 相9/相10，最后只能靠相6/相10 的 DPD 幅度整形去补，表现为功率波动。 + * + * 所以前 FAGC_LOCK_SEC 秒 FAGC+DAGC 一起跑(粗调)，之后锁死 FAGC，把剩下的时间 + * 全留给 DAGC 单独收敛(细调)。相1/相7 各 20s，这里取中点。 + * + * boot_tsnr_update() / update_tsnr_uimd_limd() 的相7 原本只有 2~3s，切不出像样的 + * 两段，所以一并延长到 FAGC_PH7_SHORT_SEC，按 FAGC_LOCK_SEC_SHORT 切分。 + */ +#define FAGC_LOCK_SEC (10) +#define FAGC_LOCK_SEC_SHORT (2) +#define FAGC_PH7_SHORT_SEC (5) + + +enum{PHASE6_SET_SAVE=1,PHASE10_SET_SAVE,WPP_SET_SAVE}; + +//----------------------------------------- + +extern pthread_mutex_t mtx_phase78910_again; +extern int g_trigger_up_tsnr_flg; +extern int g_trigger_up_start_flg; + +extern uint32 adpc_source_udp; +extern uint32 adpc_source_web; +extern pthread_mutex_t mux_dpd_wr_ck; +extern uint8 g_remote_dpd_ctrl; + +extern char out_str[52]; +extern S_ATSC_PARA atsc_para; +extern BOOL atsc_adpc_force_stop_flag; +extern uint8 dataBuffer[LEN_ADPC_DATE_BUF+4]; +extern S_EXTEND_SYS_STATE st_extend_state; +extern volatile uint8 g_query_operate; +extern volatile uint8 g_query_save; +extern volatile uint8 g_query_skip; +extern volatile uint8 g_query_wpp_to_save; + + +extern uint32 task_resume_ignore_chk(uint32 task_id); +extern uint32 flash_get_err_time(void); +extern void set_boot_tsnr_up_state(uint8 sta); + +extern uint32 auto_update; +extern S_CHECK_SIGNAL s_check_signal; +extern S_UPDATE_AUTO_ADPC update_adpc_para_flag; + +//----------------------------------------- +u8 spi_blk_buf[SPI_BLK_LEN]; + +static U_DPDCTL_REG23 u_dpdctl_r23; +u32 dpd_total_w_cnt=0; +u32 dpd_total_r_cnt=0; +int time_start=0; +int time_stop=0; + +FILE *p_dpd_log_fp = NULL; +uint8 dpd_ck_status = CK_OK; + +char str_safe[2][2]={" ","s"}; +static uint16 g_wpp_max; //wpp保护状态 +static uint8 g_query_save_flg=0; + +//----------------------------------------- + + + +/* +Normal State: RF_AFTER + AGC_OFF + DCRM_OFF + IQB_OFF +*/ +void reset_dpd_to_normal_state(void) +{ + //printf("reset_dpd_to_normal_state\n"); + u_dpdctl_r23.u8val = 0; + u_dpdctl_r23.dpd_bt.iqb_upd = 0; + u_dpdctl_r23.dpd_bt.rf_sel = DPD_RF_SEL_VALUE(E_SELECT_A); + u_dpdctl_r23.dpd_bt.sync_mode = 1; + fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); + log_printf(LOG_DEBUG, I_USER_CFG, "reset set seg5-23 IQBval=0x%x\n",u_dpdctl_r23.u8val); + //fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, 0); +} + +void write_unit_area_addr_to_spi_blkbuf(uint8 Taddr,uint16 Iaddr,uint8 Raddr, u8 wr_rd, u8 *pblk) +{ + if(wr_rd==0)//rd + pblk[0] = 0x7f & (((Raddr&0x3)<<2) | ((Iaddr>>8)&0x3)); + else//wr + pblk[0] = 0x80 | (((Raddr&0x3)<<2) | ((Iaddr>>8)&0x3)); + + pblk[1] = Iaddr&0xff; + pblk[2] = Taddr; +} + +//---->>>>---------------------------- +//区域读数据的地址和数据长度定义--不可改动 +#define DPD_AREA0_WR_UNIT_DATA_LEN 8 +#define DPD_AREA1_WR_UNIT_DATA_LEN 32 +#define DPD_AREA3_WR_UNIT_DATA_LEN 8 +#define DPD_AREA2_WR_UNIT_EXT_DATA_LEN 32 + +//----<<<<---------------------------- +static uint8 gb_addr_auto_inc=1; + +void set_dpd_unit_area_auto_inc(uint8 inc_flg) +{ + gb_addr_auto_inc = inc_flg&0x1; +} +uint8 get_dpd_unit_area_auto_inc() +{ + return gb_addr_auto_inc; +} + + +void clear_dpd_data_file(void) +{ + char cmd[300]; + + log_printf(LOG_DEBUG, I_USER_CFG, "clear dpd_data file. %s\n", DPD_DATA_FILE); + + memset(cmd, 0, sizeof(cmd)); + sprintf(cmd, "rm -rf %s",DPD_DATA_FILE); + system(cmd); +} + +u32 usr_get_file_size(void) +{ + FILE *fp; + u32 len; + + fp = fopen(DPD_DATA_FILE, "rb"); + + fseek(fp, 0, SEEK_END); + len = ftell(fp); + + fclose(fp); + return len; +} + +int get_current_time_ms(void) +{ + struct timeval tv; + gettimeofday(&tv, NULL); + return (tv.tv_sec*1000+tv.tv_usec/1000); + //printf("time: %d.%d\n",tv.tv_sec,tv.tv_usec/1000); +} + +int usr_read_file(u8 *pbuf, u32 pos, u32 len,int *perr) +{ + FILE *fp; + u32 i; + int retLen=0; + int ret=0; + + if(len>4096)return -1; + *perr=0; + + fp = fopen(DPD_DATA_FILE, "rb"); + if(NULL == fp) + { + *perr=-2; + log_printf(LOG_ERR, I_USER_CFG, "open dpd file [%s] failed.\n", DPD_DATA_FILE); + return -2; /* 要锟斤拷锟截达拷锟斤拷锟斤拷锟?*/ + } + + //log_printf(LOG_DEBUG, I_USER_CFG, "seek pos=%d ret=%d\n",pos,ret); + + ret = fseek(fp, pos, SEEK_SET); + if(ret<0){ + log_printf(LOG_ERR, I_USER_CFG, "Read File Seek err.\n"); + *perr=-3; + } + else + { + //printf("\n\n\nseek pos=%d ret=%d\n",pos*4,ret); + retLen = fread(pbuf,sizeof(u8),len,fp); + if(retLen<0){ + *perr=-2; + log_printf(LOG_ERR, I_USER_CFG, "retLen<0\n"); + } + else if(retLen!=len) + { + if(feof(fp)){ + log_printf(LOG_ERR, I_USER_CFG, "File read end.\n"); + *perr=1; + } + else{ + log_printf(LOG_ERR, I_USER_CFG, "File read err. retLen=%d,wantLen=%d.\n",retLen, len); + *perr=-1; + } + } + else + *perr=0; + } + + fclose(fp); + + return retLen; +} + + +int usr_write_file(u8 *pbuf,u32 len) +{ + FILE *fp; + u32 i; + + fp = fopen(DPD_DATA_FILE, "ab+"); + if(NULL == fp) + { + return -2; /* 要锟斤拷锟截达拷锟斤拷锟斤拷锟?*/ + } + + fwrite(pbuf,sizeof(u8),len,fp); + fclose(fp); + + return 0; +} + +int usr_write_data_file(u8 *pbuf, u32 len, u8 *pfile_name) +{ + FILE *fp; + u32 i; + + fp = fopen(pfile_name, "ab+"); + if(NULL == fp) + { + return -2; /* 要锟斤拷锟截达拷锟斤拷锟斤拷锟?*/ + } + + fwrite(pbuf, sizeof(u8), len,fp); + fclose(fp); + + return 0; +} + + + +uint32 rw_e2rom_dpd(uint32 kind,uint32 block,uint32 addr_k_cnt,uint8 *ptr) +{ + uint8 *pData = ptr; + uint32 rw_len = 0; + uint32 address = 0; + uint16 crc = 0; + uint16 crc_read = 0; + + + uint32 retry_time = 0; + int err_sta = 0; + int fread_len; + + + int start_time; + int end_time; + + if(kind==RW_ADPC_SAVE)//保存曲线 + { + if(block==E_DPD_AREA_FIRST_4K){ + log_printf(LOG_DEBUG, I_USER_CFG, "[store] start to sotre first 4k\n"); + address = 0; + + start_time = get_current_time_ms(); + usr_write_file(pData, LEN_ADPC_DATE_BUF); + end_time = get_current_time_ms(); + log_printf(LOG_DEBUG, I_USER_CFG, "file_4k time=%d\n",end_time-start_time); + //flash_write_buf(pData,LEN_ADPC_DATE_BUF,address); + } + //-------------------------------- + else if(block==E_DPD_AREA3){ + log_printf(LOG_DEBUG, I_USER_CFG, "[store] start to sotre area3\n"); + address = 0; + + start_time = get_current_time_ms(); + usr_write_file(pData, LEN_ADPC_DATE_BUF); + end_time = get_current_time_ms(); + log_printf(LOG_DEBUG, I_USER_CFG, "area3 time=%d\n",end_time-start_time); + } + //-------------------------------- + else if(block==2) + { + //printf("[store] start to sotre other 4k\n"); + //每次存储4k数据 + //address = (addr_k_cnt+1)*4096; + usr_write_file(pData, LEN_ADPC_DATE_BUF); + } + } + else if(kind==RW_ADPC_LOAD)//读取曲线 + { + if(block==E_DPD_AREA_FIRST_4K) + { + address = 0; + + //flash_read_buf(pData,LEN_ADPC_DATE_BUF,address); + rw_len = usr_read_file(pData,address,LEN_ADPC_DATE_BUF,&err_sta); + } + //-------------------------------- + else if(block==E_DPD_AREA3) + { + address = (addr_k_cnt+1)*4096; + + //flash_read_buf(pData,LEN_ADPC_DATE_BUF,address); + rw_len = usr_read_file(pData,address,LEN_ADPC_DATE_BUF,&err_sta); + } + //-------------------------------- + else if(block==2) + { + address = (addr_k_cnt+2)*4096; // (addr_k_cnt+1)*4096 + + //flash_read_buf(pData,LEN_ADPC_DATE_BUF,address); + rw_len = usr_read_file(pData,address,LEN_ADPC_DATE_BUF,&err_sta); + } + } + return rw_len; +} + + +static void * display_save_load_percent_thr(void * args) +{ + u8 ret_code=0; + char temp_buf[20]; + static u32 x_time_cnt = 0; + printf("enter display\n"); + + x_time_cnt = 0; + while(1){ + log_printf(LOG_DEBUG, I_USER_CFG, "%02d%% \n", atsc_para.system_para.save_load_data_percent); + memset(temp_buf,0,sizeof(temp_buf)); + sprintf((char*)temp_buf,"%02d%% ",atsc_para.system_para.save_load_data_percent); + + lcd_write_string(1,15,(uint8*)temp_buf); + lcd_write_cache(); + + if(st_extend_state.display_stop==E_DISPLAY_STOP){ + ret_code=2; + break; + } + + x_time_cnt++; + if(x_time_cnt >= 200){//40/0.25 + ret_code=3; + break; + } + + usleep(250*1000); + }; + + + printf(" thr exit display %d, display_sta=%d [0-start,2-stop]\n", ret_code, st_extend_state.display_stop); + st_extend_state.display_stop = E_DISPLAY_END; +} + +static int thr_display_percent_thread(void) { int ret = -1; - pthread_t display_thr_id; - int state; - pthread_attr_t attr; - + pthread_t display_thr_id; + int state; + pthread_attr_t attr; - log_printf(LOG_DEBUG,I_NOUSED,"[.thr.]->-\n"); - - pthread_attr_init(&attr); - pthread_attr_setdetachstate(&attr, PTHREAD_CREATE_DETACHED); - - ret = pthread_create(&display_thr_id, &attr, (void *)display_save_load_percent_thr, NULL);// + + log_printf(LOG_DEBUG,I_NOUSED,"[.thr.]->-\n"); + + pthread_attr_init(&attr); + pthread_attr_setdetachstate(&attr, PTHREAD_CREATE_DETACHED); + + ret = pthread_create(&display_thr_id, &attr, (void *)display_save_load_percent_thr, NULL);// if(ret != 0){ log_printf(LOG_ERR,I_NOUSED," creat thread err.\n"); return -1; } - else{ - st_extend_state.display_thr = display_thr_id; - log_printf(LOG_DEBUG,I_NOUSED," Ok. Create thr_display succeed.\n"); - } - - //printf("exit thr\n"); - //pthread_exit(st_extend_state.display_thr); + else{ + st_extend_state.display_thr = display_thr_id; + log_printf(LOG_DEBUG,I_NOUSED," Ok. Create thr_display succeed.\n"); + } + + //printf("exit thr\n"); + //pthread_exit(st_extend_state.display_thr); return 0; -} - -void calc_area_check_sum(u8 *pcheck, u8 *pbuf, u32 len) -{ - u8 check_sum=0; - - for(int j=0; jarea_imx_w_check =0; - parea_check->area_imx_r_check =0; - - parea_check->area_fpga_w_check=0; - parea_check->area_fpga_r_check=0; -} - -static int load_file_and_write_area(void) -{ - static int ret=0; - uint8 Taddr; - uint16 Iaddr; - uint16 Iaddr_Max; - uint8 Raddr; - uint8 temp_buf[20]; - uint8 Num; - - uint16 byte32Cnt=0; - uint16 saveOffset=0; - uint16 bufOffset=0; - uint32 area2_cnt=0; - - static uint8 backErr=0; - uint8 dpd_data; - u32 wait_timeout=0; - - S_CHECK_SUM area_check={0}; - - ret=0; - - atsc_para.system_para.adpc_err = DPD_LOAD_DATA; - lcd_write_string(LINE_1,0," WAIT A MOMENT .... "); - lcd_write_string(LINE_2,0," LOADING DATA... "); - lcd_write_cache(); - - //[ 0.bypass ] - fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL1, DPD_CTRL1_ALL_BYPS); - fpga_byte_write(DPD_SEG,0x41, MASK_TO_SPI_WR_RD_ENABLE); - - - //区域0+1 - if(1){ - - //for area0 + area1 - ret = rw_e2rom_dpd(RW_ADPC_LOAD, E_DPD_AREA_FIRST_4K, 0, &dataBuffer[0]);// 256 - if(ret < 0) { - printf("Err. a0 load read dpd_file failed\n"); - ret = -2; - dpd_ck_status=CK_WR_ERR; - goto CKECK_WRITE_ERR_PROC; - } - - //------------------------------------------------------------------------------- - //区域0 - log_printf(LOG_INFO, I_USER_CFG, "[area0] start write area0 data.\n"); - clear_check_sum(&area_check); - fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE|MASK_TO_FPGA_CHECK_CLEAR); - fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE); - - fpga_byte_write(DPD_SEG,0x40, MASK_DPD_DATA_AREA0_MODE); - - - //area_check.area_imx_w_check = 1; - for(Taddr=0; Taddr<=31; Taddr++){ - memset(spi_blk_buf, 0, sizeof(spi_blk_buf)); - write_unit_area_addr_to_spi_blkbuf(Taddr,0,0, E_WRITE, &spi_blk_buf[0]); - - memcpy(&spi_blk_buf[3+12], &dataBuffer[0+Taddr*DPD_AREA0_WR_UNIT_DATA_LEN], 4); - memcpy(&spi_blk_buf[3+12+16], &dataBuffer[0+Taddr*DPD_AREA0_WR_UNIT_DATA_LEN+4], 4); - - ispi_tx_big_block(spi_blk_buf, SPI_BLK_LEN); - - calc_area_u32_check_sum(&area_check.area_imx_w_check, &spi_blk_buf[3], 32); - } - - //area_check - area_check.area_fpga_w_check = read_fpga_area_u32_check_sum(E_CHECK_FOR_WIRTE); - if(area_check.area_imx_w_check != area_check.area_fpga_w_check){ - printf("Err, a0 imx_w_check not match with fpga_w_check [0x%04x 0x%04x]!\n", area_check.area_imx_w_check, area_check.area_fpga_w_check); - ret = -1; - dpd_ck_status=CK_WR_ERR; - goto CKECK_WRITE_ERR_PROC; - } - else{ - printf("a0 [u32_check]:imx_w_check and fpga_w_check [0x%04x 0x%04x]!\n", area_check.area_imx_w_check, area_check.area_fpga_w_check); - } - - fpga_byte_write(DPD_SEG,0x40,0); - log_printf(LOG_DEBUG, I_USER_CFG, "<< end area0\n"); - - - - //------------------------------------------------------------------------------- - //区域1 - log_printf(LOG_DEBUG, I_USER_CFG, "[area1] start read area1 data.\n"); - clear_check_sum(&area_check); - fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE|MASK_TO_FPGA_CHECK_CLEAR); - fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE); - - fpga_byte_write(DPD_SEG,0x40,MASK_DPD_DATA_AREA1_MODE); - - for(Taddr=0;Taddr<=15;Taddr++){ - - memset(spi_blk_buf, 0, sizeof(spi_blk_buf)); - write_unit_area_addr_to_spi_blkbuf(Taddr,0,0, E_WRITE, &spi_blk_buf[0]); - - memcpy(&spi_blk_buf[3], &dataBuffer[1024+Taddr*DPD_AREA1_WR_UNIT_DATA_LEN], DPD_AREA1_WR_UNIT_DATA_LEN); - - ispi_tx_big_block(spi_blk_buf, SPI_BLK_LEN); - - calc_area_u32_check_sum(&area_check.area_imx_w_check, &spi_blk_buf[3], 32); - } - - //area_check - area_check.area_fpga_w_check = read_fpga_area_u32_check_sum(E_CHECK_FOR_WIRTE); - if(area_check.area_imx_w_check != area_check.area_fpga_w_check){ - printf("Err, a1 imx_w_check not match with fpga_w_check [0x%04x 0x%04x]!\n", area_check.area_imx_w_check, area_check.area_fpga_w_check); - ret = -1; - dpd_ck_status=CK_WR_ERR; - goto CKECK_WRITE_ERR_PROC; - } - else{ - printf("a1 [u32_check]:imx_w_check and fpga_w_check [0x%04x 0x%04x]!\n", area_check.area_imx_w_check, area_check.area_fpga_w_check); - } - - log_printf(LOG_DEBUG, I_USER_CFG, "<< end area1\n"); - fpga_byte_write(DPD_SEG,0x40,0); - } - - - //------------------------------------------------------------------------------- - //区域3 - if(1){ - memset(&dataBuffer[0],0,sizeof(dataBuffer)); - ret = rw_e2rom_dpd(RW_ADPC_LOAD,E_DPD_AREA3,0,&dataBuffer[0]); - if(ret < 0) { - printf("Err. a3 load read dpd_file failed\n"); - ret = -2; - dpd_ck_status=CK_WR_ERR; - goto CKECK_WRITE_ERR_PROC; - } - - log_printf(LOG_DEBUG, I_USER_CFG, "[area3] start write area3 data.\n"); - clear_check_sum(&area_check); - fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE|MASK_TO_FPGA_CHECK_CLEAR); - fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE); - - fpga_byte_write(DPD_SEG,0x40,MASK_DPD_DATA_AREA3_MODE); - - for(Iaddr=0; Iaddr<=511; Iaddr++){ - - memset(spi_blk_buf, 0, sizeof(spi_blk_buf)); - write_unit_area_addr_to_spi_blkbuf(0,Iaddr,0, E_WRITE, &spi_blk_buf[0]); - - memcpy(&spi_blk_buf[3+12], &dataBuffer[Iaddr*DPD_AREA3_WR_UNIT_DATA_LEN], 4); - memcpy(&spi_blk_buf[3+12+16], &dataBuffer[Iaddr*DPD_AREA3_WR_UNIT_DATA_LEN+4], 4); - - ispi_tx_big_block(spi_blk_buf, SPI_BLK_LEN); - - calc_area_u32_check_sum(&area_check.area_imx_w_check, &spi_blk_buf[3], 32); - } - - //area_check - area_check.area_fpga_w_check = read_fpga_area_u32_check_sum(E_CHECK_FOR_WIRTE); - if(area_check.area_imx_w_check != area_check.area_fpga_w_check){ - printf("Err, a3 imx_w_check not match with fpga_w_check [0x%04x 0x%04x]!\n", area_check.area_imx_w_check, area_check.area_fpga_w_check); - ret = -1; - dpd_ck_status=CK_WR_ERR; - goto CKECK_WRITE_ERR_PROC; - } - else{ - printf("a3 [u32_check]:imx_w_check and fpga_w_check [0x%04x 0x%04x]!\n", area_check.area_imx_w_check, area_check.area_fpga_w_check); - } - - log_printf(LOG_DEBUG, I_USER_CFG, "<< end area3\n"); - fpga_byte_write(DPD_SEG,0x40,0); - } - - - //------------------------------------------------------------------------------- - //区域2 9*3*1024 - 9*1*896=19584 - st_extend_state.display_stop=E_DISPLAY_START; - atsc_para.system_para.save_load_data_percent = 0; - - printf("thr start\n"); - thr_display_percent_thread(); - printf("thr end\n"); - - if(1){ - bufOffset=0; - byte32Cnt=0; - area2_cnt=0; - - fpga_byte_write(DPD_SEG,0x40,MASK_DPD_DATA_AREA2_MODE); - - log_printf(LOG_DEBUG, I_USER_CFG, "\n\n[area2] start read area2 data.\n"); - clear_check_sum(&area_check); - fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE|MASK_TO_FPGA_CHECK_CLEAR); - fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE); - - for(Taddr=0;Taddr<=8;Taddr++) {//8 - for(Raddr=0;Raddr<=3;Raddr++) {//3 - if(Raddr==2) - continue; - - if(Raddr==3) - Iaddr_Max = 127; - else - Iaddr_Max = 1023;//1023 - - for(Iaddr=0; Iaddr<=Iaddr_Max; Iaddr++) { - area2_cnt++; - - if(bufOffset%128==0){ - memset(&dataBuffer[0],0,sizeof(dataBuffer)); - ret = rw_e2rom_dpd(RW_ADPC_LOAD,E_DPD_AREA2,saveOffset,&dataBuffer[0]);// 4kByte - if(ret < 0) { - printf("Err. a2 load read dpd_file failed\n"); - ret = -2; - dpd_ck_status=CK_WR_ERR; - goto CKECK_WRITE_ERR_PROC; - } - saveOffset++; - bufOffset=0; - atsc_para.system_para.save_load_data_percent = 100*(byte32Cnt)/(19584); - - //area_check - area_check.area_fpga_w_check = read_fpga_area_u32_check_sum(E_CHECK_FOR_WIRTE); - if(area_check.area_imx_w_check != area_check.area_fpga_w_check){ - printf("Err, a2 imx_w_check not match with fpga_w_check [0x%04x 0x%04x]!\n", area_check.area_imx_w_check, area_check.area_fpga_w_check); - ret = -1; - dpd_ck_status=CK_WR_ERR; - goto CKECK_WRITE_ERR_PROC; - } - } - - memset(spi_blk_buf, 0, sizeof(spi_blk_buf)); - write_unit_area_addr_to_spi_blkbuf(Taddr,Iaddr,Raddr, E_WRITE, &spi_blk_buf[0]); - memcpy(&spi_blk_buf[3], &dataBuffer[bufOffset*DPD_AREA2_WR_UNIT_EXT_DATA_LEN], DPD_AREA2_WR_UNIT_EXT_DATA_LEN); - - if(Raddr==3){//Iaddr(0~127)-IQ(28bit) - memset(&spi_blk_buf[3], 0, 12); - memset(&spi_blk_buf[3+16],0, 12); - spi_blk_buf[3+12] =spi_blk_buf[3+12]&0x0f; - spi_blk_buf[3+12+16] =spi_blk_buf[3+12+16]&0x0f; - } - else{//IQ(106bit) (13byte+2bit) - memset(&spi_blk_buf[3], 0, 2); - memset(&spi_blk_buf[3+16],0, 2); - spi_blk_buf[3+2] =spi_blk_buf[3+2]&0x03; - spi_blk_buf[3+2+16] =spi_blk_buf[3+2+16]&0x03; - } - - ispi_tx_big_block(spi_blk_buf, SPI_BLK_LEN); - - calc_area_u32_check_sum(&area_check.area_imx_w_check, &spi_blk_buf[3], 32); - - bufOffset++; - byte32Cnt++; - - } - } - } - atsc_para.system_para.save_load_data_percent = 100*(byte32Cnt)/(19584); - - //area_check - area_check.area_fpga_w_check = read_fpga_area_u32_check_sum(E_CHECK_FOR_WIRTE); - if(area_check.area_imx_w_check != area_check.area_fpga_w_check){ - printf("Err, a2 imx_w_check not match with fpga_w_check [0x%04x 0x%04x]!\n", area_check.area_imx_w_check, area_check.area_fpga_w_check); - ret = -1; - dpd_ck_status=CK_WR_ERR; - goto CKECK_WRITE_ERR_PROC; - } - else{ - printf("a2 [u32_check]:imx_w_check and fpga_w_check [0x%04x 0x%04x]!\n", area_check.area_imx_w_check, area_check.area_fpga_w_check); - } - - log_printf(LOG_DEBUG, I_USER_CFG, "<< end area2 [read_check]:area2_cnt=%d\n\n", area2_cnt); - fpga_byte_write(DPD_SEG,0x40,0); - } - - //------------------------------------------------------------------------------- - - //[ 7.refresh & bypass clear ] - fpga_byte_write(DPD_SEG,0x41,MASK_TO_FPGA_REFRESH_DATA); - fpga_byte_write(DPD_SEG,0x41,0); - fpga_byte_write(DPD_SEG,FPGA_ADDR_DPD_CTRL1, 0); - - printf("\n\n[area] load all finished.\n"); - - -CKECK_WRITE_ERR_PROC: - if(ret<0){ - fpga_byte_write(DPD_SEG,0x40,0); - fpga_byte_write(DPD_SEG,0x41,0); - - st_extend_state.display_stop=E_DISPLAY_STOP; - delay_ms(500); - while(1){ - - if(st_extend_state.display_stop==E_DISPLAY_END){ - printf(" mthr check display_stoped \n"); - break; - } - delay_ms(400); - printf(" mthr wait display_stop %d\n", st_extend_state.display_stop); - wait_timeout++; - if(wait_timeout>=5){ - printf("Err. timeout wait display_stop %d\n", wait_timeout); - break; - } - } - - fpga_byte_write(DPD_SEG,0x41, 0); - - lcd_write_string(LINE_1,0," ADPC data load error! [9]"); - lcd_write_string(LINE_2,0," "); - lcd_write_cache(); - delay_ms(2000); - } - else{ - st_extend_state.display_stop=E_DISPLAY_STOP; - delay_ms(500); - while(1){ - - if(st_extend_state.display_stop==E_DISPLAY_END){ - printf(" mthr check display_stoped \n"); - break; - } - delay_ms(500); - printf(" mthr wait display_stop %d\n", st_extend_state.display_stop); - wait_timeout++; - if(wait_timeout>=5){ - printf("Err. timeout wait display_stop %d\n", wait_timeout); - break; - } - } - - lcd_write_string(LINE_1,0," WAIT A MOMENT .... "); - lcd_write_string(LINE_2,0," LOADING DATA FINISHED "); - lcd_write_cache(); - delay_ms(2000); - ret = 0; - } - - return ret; -} - - - - -static int read_area_and_store_file() -{ - int ret=0; - uint8 Taddr; - uint16 Iaddr; - uint8 Raddr; - uint16 byte32Cnt=0; - uint16 saveOffset=0; - uint16 bufOffset=0; - uint32 area2_cnt=0; - static uint8 backErr=0; - int i; - uint8 Num; - uint8 temp_buf[20]; - int start_time; - int end_time; - uint8 dpd_data; - backErr = atsc_para.system_para.adpc_err; - dpd_ck_status = CK_OK; - u16 Iaddr_Max = 1023; - u32 wait_timeout=0; - S_CHECK_SUM area_check={0}; - - fpga_byte_write(DPD_SEG,0x41, MASK_TO_SPI_WR_RD_ENABLE); - - - atsc_para.system_para.adpc_err = DPD_SAVE_DATA; - lcd_write_string(LINE_1,0," WAIT A MOMENT .... "); - lcd_write_string(LINE_2,0," SAVING DATA... "); - lcd_write_cache(); - - c256_bytewrite(EEPROM_DPD_FLASH_VALID,0); - clear_dpd_data_file(); - - //区域0+1 - //---------------------------------------------------------------------------------- - - //区域0 - if(1){ - log_printf(LOG_DEBUG, I_USER_CFG, "\n\n[area0]start read area0 data.\n"); - memset(&dataBuffer[0],0,sizeof(dataBuffer)); - - fpga_byte_write(DPD_SEG,0x40, MASK_DPD_DATA_AREA0_MODE); - - clear_check_sum(&area_check); - fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE|MASK_TO_FPGA_CHECK_CLEAR); - fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE); - - for(Taddr=0;Taddr<=31;Taddr++){ - memset(spi_blk_buf, 0, sizeof(spi_blk_buf)); - write_unit_area_addr_to_spi_blkbuf(Taddr,0,0, E_READ, &spi_blk_buf[0]); - ispi_rx_big_block(spi_blk_buf, SPI_BLK_LEN); - calc_area_u32_check_sum(&area_check.area_imx_r_check, &spi_blk_buf[3], 32); - - memcpy(&dataBuffer[0+Taddr*DPD_AREA0_WR_UNIT_DATA_LEN], &spi_blk_buf[3+12], 4); - memcpy(&dataBuffer[0+Taddr*DPD_AREA0_WR_UNIT_DATA_LEN+4], &spi_blk_buf[3+12+16], 4); - } - //area_check - area_check.area_fpga_r_check = read_fpga_area_u32_check_sum(E_CHECK_FOR_RAED); - if(area_check.area_imx_r_check != area_check.area_fpga_r_check){ - printf("Err, a0 imx_r_check not match with fpga_r_check [0x%04x 0x%04x]!\n", area_check.area_imx_r_check, area_check.area_fpga_r_check); - ret = -1; - dpd_ck_status=CK_WR_ERR; - goto CKECK_READ_ERR_PROC; - } - - fpga_byte_write(DPD_SEG,0x40,0); - } - - - //---------------------------------------------------------------------------------- - //区域1 - if(1){ - log_printf(LOG_DEBUG, I_USER_CFG, "\n\n[area1]start read area1 data.\n"); - fpga_byte_write(DPD_SEG,0x40,MASK_DPD_DATA_AREA1_MODE); - - clear_check_sum(&area_check); - fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE|MASK_TO_FPGA_CHECK_CLEAR); - fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE); - - for(Taddr=0;Taddr<=15;Taddr++){ - memset(spi_blk_buf, 0, sizeof(spi_blk_buf)); - write_unit_area_addr_to_spi_blkbuf(Taddr,0,0, E_READ, &spi_blk_buf[0]); - ispi_rx_big_block(spi_blk_buf, SPI_BLK_LEN); - calc_area_u32_check_sum(&area_check.area_imx_r_check, &spi_blk_buf[3], 32); - - memcpy(&dataBuffer[1024+Taddr*DPD_AREA1_WR_UNIT_DATA_LEN], &spi_blk_buf[3], DPD_AREA1_WR_UNIT_DATA_LEN); - } - //area_check - area_check.area_fpga_r_check = read_fpga_area_u32_check_sum(E_CHECK_FOR_RAED); - if(area_check.area_imx_r_check != area_check.area_fpga_r_check){ - printf("Err, a1 imx_r_check not match with fpga_r_check [0x%04x 0x%04x]!\n", area_check.area_imx_r_check, area_check.area_fpga_r_check); - ret = -1; - dpd_ck_status=CK_WR_ERR; - goto CKECK_READ_ERR_PROC; - } - - fpga_byte_write(DPD_SEG,0x40,0); - } - - rw_e2rom_dpd(RW_ADPC_SAVE,E_DPD_AREA_FIRST_4K,0,&dataBuffer[0]); - - - //---------------------------------------------------------------------------------- - //区域3- 5个bit地址- 2^5*8 =256Byte // 32次 - if(1){ - printf("\n\n[area3]start read area3 data.\n"); - memset(&dataBuffer[0],0,sizeof(dataBuffer)); - - fpga_byte_write(DPD_SEG,0x40, MASK_DPD_DATA_AREA3_MODE); - - clear_check_sum(&area_check); - fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE|MASK_TO_FPGA_CHECK_CLEAR); - fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE); - - for(Iaddr=0;Iaddr<=511;Iaddr++){ - memset(spi_blk_buf, 0, sizeof(spi_blk_buf)); - write_unit_area_addr_to_spi_blkbuf(0,Iaddr,0, E_READ, &spi_blk_buf[0]); - ispi_rx_big_block(spi_blk_buf, SPI_BLK_LEN); - calc_area_u32_check_sum(&area_check.area_imx_r_check, &spi_blk_buf[3], 32); - - memcpy(&dataBuffer[Iaddr*DPD_AREA3_WR_UNIT_DATA_LEN], &spi_blk_buf[3+12], 4); - memcpy(&dataBuffer[Iaddr*DPD_AREA3_WR_UNIT_DATA_LEN+4], &spi_blk_buf[3+12+16], 4); - } - //area_check - area_check.area_fpga_r_check = read_fpga_area_u32_check_sum(E_CHECK_FOR_RAED); - if(area_check.area_imx_r_check != area_check.area_fpga_r_check){ - printf("Err, a3 imx_r_check not match with fpga_r_check [0x%04x 0x%04x]!\n", area_check.area_imx_r_check, area_check.area_fpga_r_check); - ret = -1; - dpd_ck_status=CK_WR_ERR; - goto CKECK_READ_ERR_PROC; - } - - fpga_byte_write(DPD_SEG,0x40,0); - rw_e2rom_dpd(RW_ADPC_SAVE,E_DPD_AREA3,0,&dataBuffer[0]); - } - - - - st_extend_state.display_stop=E_DISPLAY_START; - atsc_para.system_para.save_load_data_percent = 0; - - printf("thr start\n"); - thr_display_percent_thread(); - printf("thr end\n"); - - //---------------------------------------------------------------------------------- - //区域2- 9*4*1024*28=1032192Byte=1008KByte - if(1){ - - log_printf(LOG_DEBUG,I_NOUSED,"\n\n[area2]start read area2 data.\n"); - memset(&dataBuffer[0],0,sizeof(dataBuffer)); - area2_cnt =0; - byte32Cnt =0; - saveOffset =0;//存储4k计数 - bufOffset =0;//数据缓冲区偏移 - - Iaddr_Max = 1023; - fpga_byte_write(DPD_SEG,0x40, MASK_DPD_DATA_AREA2_MODE); - - clear_check_sum(&area_check); - fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE|MASK_TO_FPGA_CHECK_CLEAR); - fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE); - - for(Taddr=0; Taddr<=8; Taddr++){ - for(Raddr=0; Raddr<=3; Raddr++){ - if(Raddr==2) - continue; - - if(Raddr==3) - Iaddr_Max = 127; - else - Iaddr_Max = 1023; - - for(Iaddr=0; Iaddr<=Iaddr_Max; Iaddr++){ - area2_cnt++; - - start_time = get_current_time_ms(); - - memset(spi_blk_buf, 0, sizeof(spi_blk_buf)); - write_unit_area_addr_to_spi_blkbuf(Taddr,Iaddr,Raddr, E_READ, &spi_blk_buf[0]); - ispi_rx_big_block(spi_blk_buf, SPI_BLK_LEN); - - calc_area_u32_check_sum(&area_check.area_imx_r_check, &spi_blk_buf[3], 32); - - memcpy(&dataBuffer[bufOffset*DPD_AREA2_WR_UNIT_EXT_DATA_LEN], &spi_blk_buf[3], DPD_AREA2_WR_UNIT_EXT_DATA_LEN); - - end_time = get_current_time_ms(); - - byte32Cnt++; - bufOffset++; - - if(bufOffset%128==0){//32*128=4096 // 4KByte数据 - bufOffset=0; - - rw_e2rom_dpd(RW_ADPC_SAVE,E_DPD_AREA2,saveOffset,&dataBuffer[0]);// 4kByte - - memset(&dataBuffer[0],0,sizeof(dataBuffer)); - saveOffset++; - - Num=100*byte32Cnt/(19584); - - //sprintf((char*)temp_buf,"%02d%% %d",Num,flash_get_err_time()); - //log_printf(LOG_DEBUG,I_NOUSED,"%02d%% 4kByte-write to file\n",Num); - atsc_para.system_para.save_load_data_percent = Num; - - //area_check - area_check.area_fpga_r_check = read_fpga_area_u32_check_sum(E_CHECK_FOR_RAED); - if(area_check.area_imx_r_check != area_check.area_fpga_r_check){ - printf("Err, a2 imx_r_check not match with fpga_r_check [0x%04x 0x%04x]!\n", area_check.area_imx_r_check, area_check.area_fpga_r_check); - ret = -1; - dpd_ck_status=CK_WR_ERR; - goto CKECK_READ_ERR_PROC; - } - } - - } - } - } - - if(bufOffset%128!=0){ - rw_e2rom_dpd(RW_ADPC_SAVE,E_DPD_AREA2,saveOffset,&dataBuffer[0]);// 1024Byte - - //area_check - area_check.area_fpga_r_check = read_fpga_area_u32_check_sum(E_CHECK_FOR_RAED); - if(area_check.area_imx_r_check != area_check.area_fpga_r_check){ - printf("Err, a2 imx_r_check not match with fpga_r_check [0x%04x 0x%04x]!\n", area_check.area_imx_r_check, area_check.area_fpga_r_check); - ret = -1; - dpd_ck_status=CK_WR_ERR; - goto CKECK_READ_ERR_PROC; - } - } - - atsc_para.system_para.save_load_data_percent = 100*(byte32Cnt)/(19584); - printf("[read-end]read finished. area2_cnt=%d\n",area2_cnt); - fpga_byte_write(DPD_SEG,0x40, 0); - } - - - //---------------------------------------------------------------------------------- - - fpga_byte_write(DPD_SEG,0x40, 0); - fpga_byte_write(DPD_SEG,0x41, 0); - - c256_bytewrite(EEPROM_DPD_FLASH_VALID,1); - system("sync"); - - //sync display - st_extend_state.display_stop=E_DISPLAY_STOP; - delay_ms(500); - while(1){ - - if(st_extend_state.display_stop==E_DISPLAY_END){ - printf(" mthr check display_stoped \n"); - break; - } - delay_ms(500); - printf(" mthr wait display_stop %d\n", st_extend_state.display_stop); - wait_timeout++; - if(wait_timeout>=5){ - printf("Err. timeout mthr wait display_stop %d\n", wait_timeout); - break; - } - } - - -CKECK_READ_ERR_PROC: - if(dpd_ck_status==CK_WR_ERR){ - fpga_byte_write(DPD_SEG,0x40, 0); - fpga_byte_write(DPD_SEG,0x41, 0); - - //sync display - st_extend_state.display_stop=E_DISPLAY_STOP; - delay_ms(500); - while(1){ - - if(st_extend_state.display_stop==E_DISPLAY_END){ - printf(" mthr check display_stoped \n"); - break; - } - delay_ms(500); - printf(" mthr wait display_stop %d\n", st_extend_state.display_stop); - wait_timeout++; - if(wait_timeout>=5){ - printf("Err. timeout wait display_stop %d\n", wait_timeout); - break; - } - } - - //lcd_write_string(LINE_1,0," DPD READ FPGA CHECK ERROR ! "); - lcd_write_string(LINE_1,0," ADPC data save error! [8] "); - lcd_write_string(LINE_2,0," "); - lcd_write_cache(); - log_printf(LOG_DEBUG,I_NOUSED,"CKECK_READ_ERR_PROC\n"); - delay_ms(2000); - } - - log_printf(LOG_DEBUG,I_NOUSED,"exit read area and store file\n"); - - return ret; -} - - -int dpd_curve_proc(uint8 proc_mode) -{ - u32 u_size; - int ret = 0; - static uint8 backErr=0; - backErr = atsc_para.system_para.adpc_err; - st_extend_state.load_store_curve_flg=1; - - if(proc_mode == E_LOAD_TO_MCU) - { - dpd_total_w_cnt = 0; - dpd_total_r_cnt = 0; - time_start = 0; - time_stop = 0; - clear_dpd_data_file(); - time_start = get_current_time_ms(); - - //store - ret = read_area_and_store_file(); - if(ret != 0){ - log_printf(LOG_ERR, I_SYS_STATUS, "read_area_and_store_file abort!\n"); - } - - time_stop = get_current_time_ms(); - log_printf(LOG_INFO, I_SYS_STATUS, "{time cal to mcu} total_time=%ds ret=%d\n",(time_stop-time_start)/1000, ret); - - //u_size = usr_get_file_size(); - //log_printf(LOG_DEBUG, I_USER_CFG, "file size=%d\n",u_size); - - } - else if(proc_mode == E_LOAD_TO_FPGA) - { - //fpga_byte_write(0x01, 0x26, 0); // RF set OFF ; 此开关顺序宋博要求关闭,因客户不接受射频关掉. - //printf("OFF RF\n"); - dpd_total_w_cnt=0; - dpd_total_r_cnt=0; - time_start=0; - time_stop =0; - time_start = get_current_time_ms(); - - //load - ret = load_file_and_write_area(); - if(ret!=0){ - log_printf(LOG_ERR, I_SYS_STATUS, "load_file_and_write_area abort! %d\n", ret); - } - - time_stop = get_current_time_ms(); - log_printf(LOG_INFO, I_SYS_STATUS, "{time_cal to FPGA} total_time=%ds ret=%d\n",(time_stop-time_start)/1000, ret); - - - //fpga_byte_write(0x01, 0x26, 1); // RF set ON - //printf("ON RF\n"); - } - - if(ret!=0){ - atsc_para.system_para.adpc_err = ret; - if(atsc_para.system_para.adpc==ADPC_HOLD){ - atsc_para.system_para.adpc = ADPC_OFF; - c256_bytewrite(EEPROM_DPD_ADDR, ADPC_OFF); - log_printf(LOG_WARN, I_SYS_STATUS, "adpc curve err, force set adpc to off\n"); - } - } - else - atsc_para.system_para.adpc_err = backErr; - - st_extend_state.load_store_curve_flg=0; - - return ret; -} - -uint8 get_fpga_dpd_check(void) -{ - return dpd_ck_status; -} - -void dpd_exit(void)// 关闭dpd -{ - // ctrl 顺序必须是: 2 - 1 - 3 - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, 0); - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL1, DPD_CTRL1_ALL_BYPS|DPD_CTRL1_DPD_ALLCLR); - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, 0); - u_dpdctl_r23.u8val=0; - fpga_byte_write(5,FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); - reset_dpd_to_normal_state(); - - fpga_byte_write(5,FPGA_ADDR_WPP_EN_CLR, 0); - fpga_byte_write(5,FPGA_ADDR_WPP_EN_CLR, MASK_WPP_CLR); - fpga_byte_write(5,FPGA_ADDR_WPP_EN_CLR, 0); - - delay_ms(1000); - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL1, DPD_CTRL1_ALL_BYPS); -} - -void dpd_set_clr(void)// 清除曲线 -{ - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL1, DPD_CTRL1_ALL_BYPS|DPD_CTRL1_DPD_ALLCLR); - delay_ms(1000); - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL1, 0); -} - -void clear_wpp_max(void) -{ - g_wpp_max=0; -} -void remote_set_dpd_clr(void) -{ - dpd_set_clr(); - dpd_exit(); - //dpd_boot_run_init(); - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL1, DPD_CTRL1_ALL_BYPS); -} -static uint8 g_tsnr_up_flg=0; -void set_tsnr_update_flg(uint8 up_flg) -{ - g_tsnr_up_flg = up_flg&0x1; -} -uint8 get_tsnr_update_flg(void) -{ - return g_tsnr_up_flg; -} - - -int boot_tsnr_update(uint8 rst_flg) -{ - static uint8 up_phase = 7; // 实际上就是dpd的7、8、9、10步需要配置的内容 - static uint8 phase_in_flag= 0; - static uint8 sec_cnt = 0; - static uint8 s_fagc_locked= 0; // 相7: 前半段过后锁死FAGC的一次性标志 - uint8 dpd_ctl2_reg = 0; - uint8 dpd_ctl3_reg = 0 ; - uint8 rd_state = 0 ; - int ret_state = 0; - - if(atsc_para.system_para.adpc >= ADPC_UPDATE1) // 正在校正就返回 - return 1; - - - if(rst_flg) { - up_phase = 7; - sec_cnt = 0; - phase_in_flag = 1; - log_printf(LOG_DEBUG,I_NOUSED,"boot_tsnr_update start.\n"); - } - - - switch(up_phase) // 各个phase（阶段）需要进行的处理 - { - case 7: - up_phase=7; - if(phase_in_flag) //进入phase时执行一次的初始化操作 - { - phase_in_flag = 0; - dpd_ctl2_reg = 0; - - dpd_ctl3_reg = (DPD_CTRL3_SYNC_RESTART | DPD_CTRL3_FAGC_UPDATE | DPD_CTRL3_DAGC_UPDATE | DPD_CTRL3_DCRM_UPDATE); - fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); - fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); - - u_dpdctl_r23.u8val = 0; - u_dpdctl_r23.dpd_bt.iqb_upd = 0; - u_dpdctl_r23.dpd_bt.sync_mode = 1; - u_dpdctl_r23.dpd_bt.rf_sel = 0; - log_printf(LOG_DEBUG,I_NOUSED,"[state] phase 7 ---------------A- 0x%x\n", u_dpdctl_r23.u8val); - fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); - - s_fagc_locked = 0; - } - - // 前半段跑完, 锁死射频AGC, 后半段只留数字AGC收敛 - if(!s_fagc_locked && sec_cnt >= FAGC_LOCK_SEC_SHORT) - { - s_fagc_locked = 1; - // 只清 FAGC_UPDATE(bit0), SYNC_RESTART 保持到相8才放开 - dpd_ctl3_reg = (DPD_CTRL3_SYNC_RESTART | DPD_CTRL3_DAGC_UPDATE | DPD_CTRL3_DCRM_UPDATE); - fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); - log_printf(LOG_DEBUG,I_NOUSED,"[state] phase 7: FAGC locked at %ds, CTRL3=0x%02x\n", - sec_cnt, dpd_ctl3_reg); - } - - // out - if(sec_cnt >= FAGC_PH7_SHORT_SEC){ - up_phase = 8; - sec_cnt = 0; - phase_in_flag = 1; - } - break; - - case 8: - up_phase = 8; - if(phase_in_flag) //进入phase时执行一次的初始化操作 - { - phase_in_flag = 0; - dpd_ctl2_reg = 0; - dpd_ctl3_reg = (DPD_CTRL3_SYNC_UPDATE | DPD_CTRL3_DCRM_UPDATE); - fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); - fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); - log_printf(LOG_DEBUG,I_NOUSED,"[state] phase 8\n"); - } - //out - rd_state = fpga_byte_read(0x05, FPGA_ADDR_DPD_STATUS1); - if(rd_state & MASK_DPD_TRX_SYNC_OK) // 读取到dpd_trx_sync_ok状态为1时进入下一阶段 - { - log_printf(LOG_DEBUG,I_NOUSED,"[state] phase 8 state: TX RX sync OK\n"); - // set fix delay - up_phase = 9; - sec_cnt = 0; - phase_in_flag = 1; - } - else if(sec_cnt >= 15)// 80 超过80秒未读到sync ok， 同步失败，退出校正 - { - log_printf(LOG_DEBUG,I_NOUSED,"[state] phase 8 state: TX RX sync failed\n"); - - //超时处理 - up_phase = 9; - sec_cnt = 0; - phase_in_flag = 1; - } - break; - - case 9: - up_phase = 9; - if(phase_in_flag) - { - phase_in_flag = 0; - - dpd_ctl2_reg = 0; - fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); - - // FAGC 已在相7锁死, 这里不能再放开: 它会和 DAGC 一起跑, 又把 0.43dB - // 的射频台阶注回 DAGC 的输入(主状态机的相9 本来就没有 FAGC, 这里对齐) - dpd_ctl3_reg = DPD_CTRL3_DAGC_UPDATE| DPD_CTRL3_DAGC_SLOWDN | DPD_CTRL3_ROT_UPDATE; - fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); - - u_dpdctl_r23.dpd_bt.iqb_upd = 1; - u_dpdctl_r23.dpd_bt.sync_mode = 1; - u_dpdctl_r23.dpd_bt.rf_sel = 0;// A - log_printf(LOG_DEBUG,I_NOUSED,"[state] phase 9 ---------------A- 0x%x\n", u_dpdctl_r23.u8val); - fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); - } - - // out - if(sec_cnt >= 3) - { - up_phase = 10; - sec_cnt = 0; - phase_in_flag = 1; - } - break; - - case 10: - // in - up_phase = 10; - if(phase_in_flag) { - phase_in_flag = 0; - - dpd_ctl2_reg = DPD_CTRL2_RXEQ_UPDATE; - fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); - - dpd_ctl3_reg = DPD_CTRL3_FAGC_UPDATE|DPD_CTRL3_FAGC_SLOWDN; - fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); - - u_dpdctl_r23.dpd_bt.iqb_upd = 0; - fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); - log_printf(LOG_DEBUG,I_NOUSED,"[state] phase 10 --- 0x%x\n", u_dpdctl_r23.u8val); - } - - // out - g_query_operate = 0; - up_phase = 0xff;// left must 0xff - sec_cnt = 0; - phase_in_flag = 0; - ret_state = 1; // left must 1 - log_printf(LOG_DEBUG,I_NOUSED,"boot_tsnr_update end.\n"); - break; - - default: - break; - } - - sec_cnt++; - - return ret_state; -} -//static uint8 t_oneshot_flg=0; -int update_tsnr_uimd_limd(uint8 rst_flg, uint8 *p_phase) -{ - static uint8 up_phase = 7; // 实际上就是dpd的7、8、9、10步需要配置的内容 - static uint8 phase_in_flag= 0; - static uint8 sec_cnt = 0; - static uint8 s_fagc_locked= 0; // 相7: 前半段过后锁死FAGC的一次性标志 - uint8 dpd_ctl2_reg; - uint8 dpd_ctl3_reg; - uint8 rd_state; - int ret_state = 0; - - if(atsc_para.system_para.adpc >= ADPC_UPDATE1) // 正在校正就返回 - return 1; - - if(rst_flg){ - up_phase = 7; - sec_cnt = 0; - phase_in_flag = 1; - log_printf(LOG_DEBUG, I_USER_CFG, "sta.update_tsnr_uimd_limd in new menu.\n"); - } - - *p_phase = up_phase; - switch(up_phase) // 各个phase（阶段）需要进行的处理 - { - case 7: - up_phase=7; - if(phase_in_flag) //进入phase时执行一次的初始化操作 - { - phase_in_flag = 0; - dpd_ctl2_reg = 0; - - dpd_ctl3_reg = (DPD_CTRL3_SYNC_RESTART | - DPD_CTRL3_FAGC_UPDATE | - DPD_CTRL3_DAGC_UPDATE | - DPD_CTRL3_DCRM_UPDATE); - fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); - fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); - - u_dpdctl_r23.u8val=0; - u_dpdctl_r23.dpd_bt.iqb_upd = 0; - u_dpdctl_r23.dpd_bt.sync_mode = 1; - u_dpdctl_r23.dpd_bt.rf_sel = 0; - fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); - log_printf(LOG_DEBUG, I_USER_CFG, "[state] phase 7 in---------------A- 0x%x\n", u_dpdctl_r23.u8val); - - s_fagc_locked = 0; - } - - // 前半段跑完, 锁死射频AGC, 后半段只留数字AGC收敛 - if(!s_fagc_locked && sec_cnt >= FAGC_LOCK_SEC_SHORT) - { - s_fagc_locked = 1; - // 只清 FAGC_UPDATE(bit0), SYNC_RESTART 保持到相8才放开 - dpd_ctl3_reg = (DPD_CTRL3_SYNC_RESTART | DPD_CTRL3_DAGC_UPDATE | DPD_CTRL3_DCRM_UPDATE); - fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); - log_printf(LOG_DEBUG, I_USER_CFG, "[state] phase 7: FAGC locked at %ds, CTRL3=0x%02x\n", - sec_cnt, dpd_ctl3_reg); - } - - // out - if(sec_cnt >= FAGC_PH7_SHORT_SEC){ - up_phase = 8; - sec_cnt = 0; - phase_in_flag = 1; - log_printf(LOG_DEBUG, I_USER_CFG, "[state] phase 7 out \n"); - } - break; - - case 8: - up_phase = 8; - if(phase_in_flag) //进入phase时执行一次的初始化操作 - { - phase_in_flag = 0; - dpd_ctl2_reg = 0; - dpd_ctl3_reg = (DPD_CTRL3_SYNC_UPDATE| - DPD_CTRL3_DCRM_UPDATE| - DPD_CTRL3_FAGC_UPDATE); - fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); - fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); - log_printf(LOG_DEBUG, I_USER_CFG, "[state] phase 8 in\n"); - } - //out - rd_state = fpga_byte_read(0x05, FPGA_ADDR_DPD_STATUS1); - if(rd_state & MASK_DPD_TRX_SYNC_OK) // 读取到dpd_trx_sync_ok状态为1时进入下一阶段 - { - log_printf(LOG_DEBUG, I_USER_CFG, "[state] phase 8 out, state: TX RX sync OK\n"); - // set fix delay - up_phase = 9; - sec_cnt = 0; - phase_in_flag = 1; - } - else if(sec_cnt >= 15)// 80 超过80秒未读到sync ok， 同步失败，退出校正 - { - //超时处理 - up_phase = 9; - sec_cnt = 0; - phase_in_flag = 1; - log_printf(LOG_DEBUG, I_USER_CFG, "[state] phase 8 out, state: TX RX sync failed\n"); - } - break; - - case 9: - up_phase = 9; - if(phase_in_flag) - { - phase_in_flag = 0; - - dpd_ctl2_reg = 0; - fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); - - dpd_ctl3_reg = DPD_CTRL3_ROT_UPDATE|DPD_CTRL3_FAGC_UPDATE; - fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); - - u_dpdctl_r23.dpd_bt.iqb_upd = 1; - u_dpdctl_r23.dpd_bt.sync_mode = 1; - u_dpdctl_r23.dpd_bt.rf_sel = 0;// A - fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); - log_printf(LOG_DEBUG, I_USER_CFG, "[state] phase 9 in---------------A- 0x%x\n", u_dpdctl_r23.u8val); - } - - // out - if(sec_cnt >= 3) // 7 - { - up_phase = 10; - sec_cnt = 0; - phase_in_flag = 1; - log_printf(LOG_DEBUG, I_USER_CFG, "[state] phase 9 out \n"); - } - break; - - case 10: - // in - up_phase = 10; - if(phase_in_flag) { - phase_in_flag = 0; - - dpd_ctl2_reg = DPD_CTRL2_RXEQ_UPDATE; - fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); - - dpd_ctl3_reg = DPD_CTRL3_FAGC_UPDATE; - fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); - - u_dpdctl_r23.dpd_bt.iqb_upd = 0; - fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); - log_printf(LOG_DEBUG, I_USER_CFG, "[state] phase 10 in --- 0x%x\n", u_dpdctl_r23.u8val); - } - - // out - if(sec_cnt >= 2) // 7 - { - g_query_operate = 0; - up_phase = 0xff;// left must 0xff - sec_cnt = 0; - phase_in_flag = 0; - ret_state = 1; // left must 1 - log_printf(LOG_DEBUG, I_USER_CFG, "[state] phase 10 out. \n"); - } - break; - - default: - break; - } - - sec_cnt++; - return ret_state; -} - - -int dpd_log_trig(int trig_enable) -{ -#if DPD_LOG_ENABLE - if(trig_enable>1 || trig_enable<0){ - log_printf(LOG_DEBUG, I_USER_CFG, "trig_enable err, set 0\n"); - trig_enable = 0; - } - - fpga_byte_write(5, FPGA_ADDR_DPD_LOG_TRIG, trig_enable); -#endif - return 0; -} -int dpd_log_file_open(void) -{ - /* - * w+ : 打开一个文本文件，允许读写文件。 - 如果文件已存在，则文件会被截断为零长度， - 如果文件不存在，则会创建一个新文件。 - */ -#if DPD_LOG_ENABLE - if(p_dpd_log_fp != NULL){ - log_printf(LOG_ERR, I_USER_CFG, "dpd log has opened.\n"); - return 0; - } - - p_dpd_log_fp = fopen(DPD_LOG_FILE, "w+"); - if (p_dpd_log_fp == NULL){ - log_printf(LOG_ERR, I_USER_CFG, "dpd log file open failed.\n"); - return -1; - }else - log_printf(LOG_DEBUG, I_USER_CFG, "dpd log file open success.\n"); - - - struct tm tmBJ; - get_beijing_time(&tmBJ); - fprintf(p_dpd_log_fp, "[%04d-%02d-%02d %02d:%02d:%02d] open %s success.\n\n", - tmBJ.tm_year, tmBJ.tm_mon, tmBJ.tm_mday, tmBJ.tm_hour, tmBJ.tm_min, tmBJ.tm_sec, DPD_LOG_FILE); -#endif - return 0; -} - -int dpd_log_file_close( char *whyclose) -{ -#if DPD_LOG_ENABLE - - if(p_dpd_log_fp == NULL || whyclose == NULL) { - log_printf(LOG_ERR, I_USER_CFG, "[%s] null or whyclose null\n", DPD_LOG_FILE); - return -1; - } - - struct tm tmBJ; - get_beijing_time(&tmBJ); - - fprintf(p_dpd_log_fp, "\n\n[%04d-%02d-%02d %02d:%02d:%02d] close %s, case [%s]\n\n", - tmBJ.tm_year, tmBJ.tm_mon, tmBJ.tm_mday, tmBJ.tm_hour, tmBJ.tm_min, tmBJ.tm_sec, DPD_LOG_FILE, whyclose); - - if(p_dpd_log_fp != NULL) - fclose(p_dpd_log_fp); - - log_printf(LOG_DEBUG, I_USER_CFG, "dpd log file close success\n"); - p_dpd_log_fp = NULL; -#endif - return 0; -} - - - -int dpd_log_read_and_save(int phase) -{ -#if DPD_LOG_ENABLE - uint8 log_data[24] = {0}; - S_DPD_LOG_TYPE ldata; - struct tm tmBJ; - static int bak_phase = 0; - int i = 0; - - if(p_dpd_log_fp == NULL) { - log_printf(LOG_ERR, I_USER_CFG, "%s null\n", DPD_LOG_FILE); - return -1; - } - - dpd_log_trig(1); - - // read data from FPGA segment 5 [0x20--0x37] - fpga_byte_reads(5, FPGA_ADDR_DPD_CTRL1, log_data, 24); - - ldata.rx_fgain_cw_i = (log_data[0] << 0) + (log_data[1] << 8); - ldata.rx_dgain_i = (log_data[2] << 0) + (log_data[3] << 8); - ldata.txpow_cur_i = (log_data[4] << 0) + (log_data[5] << 8); - ldata.txaveamp_i = (log_data[6] << 0) + (log_data[7] << 8); - ldata.ob_wpp_max_i = (log_data[8] << 0) + (log_data[9] << 8); - ldata.rx_data_iq_i = (log_data[10] << 0) + (log_data[11] << 8) + (log_data[12] << 16) + (log_data[13] << 24); - ldata.tx_data_iq_i = (log_data[14] << 0) + (log_data[15] << 8) + (log_data[16] << 16) + (log_data[17] << 24); - ldata.dpd_dynamic_gain_i = (log_data[18] << 0) + (log_data[19] << 8); - ldata.ob_b_pwr_i = (log_data[20] << 0) + (log_data[21] << 8); - ldata.ob_a_pwr_i = (log_data[22] << 0) + (log_data[23] << 8); - - if(bak_phase != phase) { - get_beijing_time(&tmBJ); - fprintf(p_dpd_log_fp, "[%02d:%02d:%02d]************* phase %d ****************\n",tmBJ.tm_hour, tmBJ.tm_min, tmBJ.tm_sec, phase); - bak_phase = phase; - } - - fprintf(p_dpd_log_fp, "tx_data_iq_i = 0x%08x\n", ldata.tx_data_iq_i); - fprintf(p_dpd_log_fp, "rx_data_iq_i = 0x%08x\n", ldata.rx_data_iq_i); - fprintf(p_dpd_log_fp, "ob_wpp_max_i = 0x%04x\n", ldata.ob_wpp_max_i); - fprintf(p_dpd_log_fp, "txaveamp_i = 0x%04x\n", ldata.txaveamp_i); - fprintf(p_dpd_log_fp, "txpow_cur_i = 0x%04x\n", ldata.txpow_cur_i); - fprintf(p_dpd_log_fp, "rx_dgain_i = 0x%04x\n", ldata.rx_dgain_i); - fprintf(p_dpd_log_fp, "rx_fgain_cw_i = 0x%04x\n", ldata.rx_fgain_cw_i); - fprintf(p_dpd_log_fp, "dpd_dynamic_gain_i = 0x%04x\n", ldata.dpd_dynamic_gain_i); - fprintf(p_dpd_log_fp, "ob_b_pwr_i = 0x%04x\n", ldata.ob_b_pwr_i); - fprintf(p_dpd_log_fp, "ob_a_pwr_i = 0x%04x\n\n\n", ldata.ob_a_pwr_i); - - dpd_log_trig(0); - -#endif - return 0; -} - -int dpd_log_read_and_save_end(char * say) -{ -#if DPD_LOG_ENABLE - uint8 log_data[24] = {0}; - S_DPD_LOG_TYPE ldata; - struct tm tmBJ; - int i = 0; - - if(p_dpd_log_fp == NULL) { - log_printf(LOG_ERR, I_USER_CFG, "%s null\n", DPD_LOG_FILE); - return -1; - } - - dpd_log_trig(1); - - // read data from FPGA segment 5 [0x20--0x37] - fpga_byte_reads(5, FPGA_ADDR_DPD_CTRL1, log_data, 24); - - ldata.rx_fgain_cw_i = (log_data[0] << 0) + (log_data[1] << 8); - ldata.rx_dgain_i = (log_data[2] << 0) + (log_data[3] << 8); - ldata.txpow_cur_i = (log_data[4] << 0) + (log_data[5] << 8); - ldata.txaveamp_i = (log_data[6] << 0) + (log_data[7] << 8); - ldata.ob_wpp_max_i = (log_data[8] << 0) + (log_data[9] << 8); - ldata.rx_data_iq_i = (log_data[10] << 0) + (log_data[11] << 8) + (log_data[12] << 16) + (log_data[13] << 24); - ldata.tx_data_iq_i = (log_data[14] << 0) + (log_data[15] << 8) + (log_data[16] << 16) + (log_data[17] << 24); - ldata.dpd_dynamic_gain_i = (log_data[18] << 0) + (log_data[19] << 8); - ldata.ob_b_pwr_i = (log_data[20] << 0) + (log_data[21] << 8); - ldata.ob_a_pwr_i = (log_data[22] << 0) + (log_data[23] << 8); - - - get_beijing_time(&tmBJ); - fprintf(p_dpd_log_fp, "[%02d:%02d:%02d]************* will end ****************\n", tmBJ.tm_hour, tmBJ.tm_min, tmBJ.tm_sec); - if(say != NULL) - fprintf(p_dpd_log_fp, " %s \n", say); - - fprintf(p_dpd_log_fp, "tx_data_iq_i = 0x%08x\n", ldata.tx_data_iq_i); - fprintf(p_dpd_log_fp, "rx_data_iq_i = 0x%08x\n", ldata.rx_data_iq_i); - fprintf(p_dpd_log_fp, "ob_wpp_max_i = 0x%04x\n", ldata.ob_wpp_max_i); - fprintf(p_dpd_log_fp, "txaveamp_i = 0x%04x\n", ldata.txaveamp_i); - fprintf(p_dpd_log_fp, "txpow_cur_i = 0x%04x\n", ldata.txpow_cur_i); - fprintf(p_dpd_log_fp, "rx_dgain_i = 0x%04x\n", ldata.rx_dgain_i); - fprintf(p_dpd_log_fp, "rx_fgain_cw_i = 0x%04x\n", ldata.rx_fgain_cw_i); - fprintf(p_dpd_log_fp, "dpd_dynamic_gain_i = 0x%04x\n", ldata.dpd_dynamic_gain_i); - fprintf(p_dpd_log_fp, "ob_b_pwr_i = 0x%04x\n", ldata.ob_b_pwr_i); - fprintf(p_dpd_log_fp, "ob_a_pwr_i = 0x%04x\n\n\n", ldata.ob_a_pwr_i); - - dpd_log_trig(0); - -#endif - return 0; -} - -int dpd_log_string_save(char* string) -{ -#if DPD_LOG_ENABLE - - if(p_dpd_log_fp == NULL) { - log_printf(LOG_ERR, I_USER_CFG, "dpd_log_string_save [%s] fp is null\n", DPD_LOG_FILE); - return -1; - } - - if(string != NULL) - fprintf(p_dpd_log_fp, " %s \n", string); -#endif - return 0; -} - -uint8 conv_adpc_err_output(uint8 raw_dpd_err) -{ - uint8 output_err=0; - - switch(raw_dpd_err) - { - case DPD_STATE_ERR: - output_err=1; //DPD stop,PA protection - break; - case DPD_STATE_POWER_HIGH: - output_err=2; //DPD fail,Feedback high - break; - case DPD_STATE_POWER_LOW: - output_err=3; //DPD fail,Feedback low - break; - case DPD_STATE_POWER_TOO_HIGH: - output_err=4; //DPD fail,Feedback high - break; - case DPD_STATE_POWER_TOO_LOW: - output_err=5; //DPD fail,Feedback low - break; - case DPD_STATE_ERR_OVER_RANGE: - output_err=6; //DPD stop, Over distortion or DPD stop, Check RF filter - break; - case DPD_CHECK_WPP_ERR_EXIT_HOLD: - output_err=7; //DPD stop,PA protection - break; - case DPD_READ_CKECK_ERR: - output_err=8; //DPD data save error - break; - case DPD_WRITE_CHECK_ERR: - output_err=9; //DPD data load error - break; - case DPD_SYNC_TIMEOUT: - output_err=10; //DPD SYNC_TIMEOUT - break; - default: - break; - } - - return output_err; -} - - -void set_ab_switch(E_AB_SEL ab_val) -{ - u_dpdctl_r23.dpd_bt.rf_sel = ab_val; // 1 : B , 0 : A - fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); -} - -void little_balance(S_SYSTEM_PARA * psys) -{ - S_SYS_TIME bak_time = {0xff,};//本地时间 - S_SYS_TIME now_time = {0,}; - int ret = 0; - uint8 reset_up = 1; - uint8 uuu_phase = 0; - uint8 old_phase = 0; - char show_perc[5] = {0}; - psys->final_stage = 3; - - while(1) - { - get_sys_time(&now_time); - - if(bak_time.sec != now_time.sec) { - pthread_mutex_lock(&mtx_phase78910_again); - ret = update_tsnr_uimd_limd(reset_up,&uuu_phase); - if(reset_up) - reset_up = 0; - if(uuu_phase!=old_phase){ - psys->final_stage = 10-uuu_phase; - old_phase = uuu_phase; - } - - if(ret == 1) { - pthread_mutex_unlock(&mtx_phase78910_again); - break; - } - pthread_mutex_unlock(&mtx_phase78910_again); - - get_sys_time(&bak_time); - } - usleep(20000);// 20ms - } - - reset_dpd_to_normal_state(); - psys->final_stage = 0xff; - -} - - -void refresh_waiting(void *parg,void *parv) -{ - uint8 retime = atsc_para.system_para.final_stage; - char show_perc[5] = {0}; - - lcd_write_string(LINE_1,0," WAIT A MOMENT .... "); - lcd_write_string(LINE_2,0," FINAL STAGE "); - - if(retime != 0xff){ - sprintf(show_perc, "%d ", retime); - lcd_write_string(LINE_2, 15, show_perc); - } -} - -void refresh_update_dpd(void *parg,void *parv) -{ - S_SYSTEM_PARA *psys = &atsc_para.system_para; - uint16 dpd_disp_step = 0; +} + +void calc_area_check_sum(u8 *pcheck, u8 *pbuf, u32 len) +{ + u8 check_sum=0; + + for(int j=0; jarea_imx_w_check =0; + parea_check->area_imx_r_check =0; + + parea_check->area_fpga_w_check=0; + parea_check->area_fpga_r_check=0; +} + +static int load_file_and_write_area(void) +{ + static int ret=0; + uint8 Taddr; + uint16 Iaddr; + uint16 Iaddr_Max; + uint8 Raddr; + uint8 temp_buf[20]; + uint8 Num; + + uint16 byte32Cnt=0; + uint16 saveOffset=0; + uint16 bufOffset=0; + uint32 area2_cnt=0; + + static uint8 backErr=0; + uint8 dpd_data; + u32 wait_timeout=0; + + S_CHECK_SUM area_check={0}; + + ret=0; + + atsc_para.system_para.adpc_err = DPD_LOAD_DATA; + lcd_write_string(LINE_1,0," WAIT A MOMENT .... "); + lcd_write_string(LINE_2,0," LOADING DATA... "); + lcd_write_cache(); + + //[ 0.bypass ] + fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL1, DPD_CTRL1_ALL_BYPS); + fpga_byte_write(DPD_SEG,0x41, MASK_TO_SPI_WR_RD_ENABLE); + + + //区域0+1 + if(1){ + + //for area0 + area1 + ret = rw_e2rom_dpd(RW_ADPC_LOAD, E_DPD_AREA_FIRST_4K, 0, &dataBuffer[0]);// 256 + if(ret < 0) { + printf("Err. a0 load read dpd_file failed\n"); + ret = -2; + dpd_ck_status=CK_WR_ERR; + goto CKECK_WRITE_ERR_PROC; + } + + //------------------------------------------------------------------------------- + //区域0 + log_printf(LOG_INFO, I_USER_CFG, "[area0] start write area0 data.\n"); + clear_check_sum(&area_check); + fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE|MASK_TO_FPGA_CHECK_CLEAR); + fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE); + + fpga_byte_write(DPD_SEG,0x40, MASK_DPD_DATA_AREA0_MODE); + + + //area_check.area_imx_w_check = 1; + for(Taddr=0; Taddr<=31; Taddr++){ + memset(spi_blk_buf, 0, sizeof(spi_blk_buf)); + write_unit_area_addr_to_spi_blkbuf(Taddr,0,0, E_WRITE, &spi_blk_buf[0]); + + memcpy(&spi_blk_buf[3+12], &dataBuffer[0+Taddr*DPD_AREA0_WR_UNIT_DATA_LEN], 4); + memcpy(&spi_blk_buf[3+12+16], &dataBuffer[0+Taddr*DPD_AREA0_WR_UNIT_DATA_LEN+4], 4); + + ispi_tx_big_block(spi_blk_buf, SPI_BLK_LEN); + + calc_area_u32_check_sum(&area_check.area_imx_w_check, &spi_blk_buf[3], 32); + } + + //area_check + area_check.area_fpga_w_check = read_fpga_area_u32_check_sum(E_CHECK_FOR_WIRTE); + if(area_check.area_imx_w_check != area_check.area_fpga_w_check){ + printf("Err, a0 imx_w_check not match with fpga_w_check [0x%04x 0x%04x]!\n", area_check.area_imx_w_check, area_check.area_fpga_w_check); + ret = -1; + dpd_ck_status=CK_WR_ERR; + goto CKECK_WRITE_ERR_PROC; + } + else{ + printf("a0 [u32_check]:imx_w_check and fpga_w_check [0x%04x 0x%04x]!\n", area_check.area_imx_w_check, area_check.area_fpga_w_check); + } + + fpga_byte_write(DPD_SEG,0x40,0); + log_printf(LOG_DEBUG, I_USER_CFG, "<< end area0\n"); + + + + //------------------------------------------------------------------------------- + //区域1 + log_printf(LOG_DEBUG, I_USER_CFG, "[area1] start read area1 data.\n"); + clear_check_sum(&area_check); + fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE|MASK_TO_FPGA_CHECK_CLEAR); + fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE); + + fpga_byte_write(DPD_SEG,0x40,MASK_DPD_DATA_AREA1_MODE); + + for(Taddr=0;Taddr<=15;Taddr++){ + + memset(spi_blk_buf, 0, sizeof(spi_blk_buf)); + write_unit_area_addr_to_spi_blkbuf(Taddr,0,0, E_WRITE, &spi_blk_buf[0]); + + memcpy(&spi_blk_buf[3], &dataBuffer[1024+Taddr*DPD_AREA1_WR_UNIT_DATA_LEN], DPD_AREA1_WR_UNIT_DATA_LEN); + + ispi_tx_big_block(spi_blk_buf, SPI_BLK_LEN); + + calc_area_u32_check_sum(&area_check.area_imx_w_check, &spi_blk_buf[3], 32); + } + + //area_check + area_check.area_fpga_w_check = read_fpga_area_u32_check_sum(E_CHECK_FOR_WIRTE); + if(area_check.area_imx_w_check != area_check.area_fpga_w_check){ + printf("Err, a1 imx_w_check not match with fpga_w_check [0x%04x 0x%04x]!\n", area_check.area_imx_w_check, area_check.area_fpga_w_check); + ret = -1; + dpd_ck_status=CK_WR_ERR; + goto CKECK_WRITE_ERR_PROC; + } + else{ + printf("a1 [u32_check]:imx_w_check and fpga_w_check [0x%04x 0x%04x]!\n", area_check.area_imx_w_check, area_check.area_fpga_w_check); + } + + log_printf(LOG_DEBUG, I_USER_CFG, "<< end area1\n"); + fpga_byte_write(DPD_SEG,0x40,0); + } + + + //------------------------------------------------------------------------------- + //区域3 + if(1){ + memset(&dataBuffer[0],0,sizeof(dataBuffer)); + ret = rw_e2rom_dpd(RW_ADPC_LOAD,E_DPD_AREA3,0,&dataBuffer[0]); + if(ret < 0) { + printf("Err. a3 load read dpd_file failed\n"); + ret = -2; + dpd_ck_status=CK_WR_ERR; + goto CKECK_WRITE_ERR_PROC; + } + + log_printf(LOG_DEBUG, I_USER_CFG, "[area3] start write area3 data.\n"); + clear_check_sum(&area_check); + fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE|MASK_TO_FPGA_CHECK_CLEAR); + fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE); + + fpga_byte_write(DPD_SEG,0x40,MASK_DPD_DATA_AREA3_MODE); + + for(Iaddr=0; Iaddr<=511; Iaddr++){ + + memset(spi_blk_buf, 0, sizeof(spi_blk_buf)); + write_unit_area_addr_to_spi_blkbuf(0,Iaddr,0, E_WRITE, &spi_blk_buf[0]); + + memcpy(&spi_blk_buf[3+12], &dataBuffer[Iaddr*DPD_AREA3_WR_UNIT_DATA_LEN], 4); + memcpy(&spi_blk_buf[3+12+16], &dataBuffer[Iaddr*DPD_AREA3_WR_UNIT_DATA_LEN+4], 4); + + ispi_tx_big_block(spi_blk_buf, SPI_BLK_LEN); + + calc_area_u32_check_sum(&area_check.area_imx_w_check, &spi_blk_buf[3], 32); + } + + //area_check + area_check.area_fpga_w_check = read_fpga_area_u32_check_sum(E_CHECK_FOR_WIRTE); + if(area_check.area_imx_w_check != area_check.area_fpga_w_check){ + printf("Err, a3 imx_w_check not match with fpga_w_check [0x%04x 0x%04x]!\n", area_check.area_imx_w_check, area_check.area_fpga_w_check); + ret = -1; + dpd_ck_status=CK_WR_ERR; + goto CKECK_WRITE_ERR_PROC; + } + else{ + printf("a3 [u32_check]:imx_w_check and fpga_w_check [0x%04x 0x%04x]!\n", area_check.area_imx_w_check, area_check.area_fpga_w_check); + } + + log_printf(LOG_DEBUG, I_USER_CFG, "<< end area3\n"); + fpga_byte_write(DPD_SEG,0x40,0); + } + + + //------------------------------------------------------------------------------- + //区域2 9*3*1024 - 9*1*896=19584 + st_extend_state.display_stop=E_DISPLAY_START; + atsc_para.system_para.save_load_data_percent = 0; + + printf("thr start\n"); + thr_display_percent_thread(); + printf("thr end\n"); + + if(1){ + bufOffset=0; + byte32Cnt=0; + area2_cnt=0; + + fpga_byte_write(DPD_SEG,0x40,MASK_DPD_DATA_AREA2_MODE); + + log_printf(LOG_DEBUG, I_USER_CFG, "\n\n[area2] start read area2 data.\n"); + clear_check_sum(&area_check); + fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE|MASK_TO_FPGA_CHECK_CLEAR); + fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE); + + for(Taddr=0;Taddr<=8;Taddr++) {//8 + for(Raddr=0;Raddr<=3;Raddr++) {//3 + if(Raddr==2) + continue; + + if(Raddr==3) + Iaddr_Max = 127; + else + Iaddr_Max = 1023;//1023 + + for(Iaddr=0; Iaddr<=Iaddr_Max; Iaddr++) { + area2_cnt++; + + if(bufOffset%128==0){ + memset(&dataBuffer[0],0,sizeof(dataBuffer)); + ret = rw_e2rom_dpd(RW_ADPC_LOAD,E_DPD_AREA2,saveOffset,&dataBuffer[0]);// 4kByte + if(ret < 0) { + printf("Err. a2 load read dpd_file failed\n"); + ret = -2; + dpd_ck_status=CK_WR_ERR; + goto CKECK_WRITE_ERR_PROC; + } + saveOffset++; + bufOffset=0; + atsc_para.system_para.save_load_data_percent = 100*(byte32Cnt)/(19584); + + //area_check + area_check.area_fpga_w_check = read_fpga_area_u32_check_sum(E_CHECK_FOR_WIRTE); + if(area_check.area_imx_w_check != area_check.area_fpga_w_check){ + printf("Err, a2 imx_w_check not match with fpga_w_check [0x%04x 0x%04x]!\n", area_check.area_imx_w_check, area_check.area_fpga_w_check); + ret = -1; + dpd_ck_status=CK_WR_ERR; + goto CKECK_WRITE_ERR_PROC; + } + } + + memset(spi_blk_buf, 0, sizeof(spi_blk_buf)); + write_unit_area_addr_to_spi_blkbuf(Taddr,Iaddr,Raddr, E_WRITE, &spi_blk_buf[0]); + memcpy(&spi_blk_buf[3], &dataBuffer[bufOffset*DPD_AREA2_WR_UNIT_EXT_DATA_LEN], DPD_AREA2_WR_UNIT_EXT_DATA_LEN); + + if(Raddr==3){//Iaddr(0~127)-IQ(28bit) + memset(&spi_blk_buf[3], 0, 12); + memset(&spi_blk_buf[3+16],0, 12); + spi_blk_buf[3+12] =spi_blk_buf[3+12]&0x0f; + spi_blk_buf[3+12+16] =spi_blk_buf[3+12+16]&0x0f; + } + else{//IQ(106bit) (13byte+2bit) + memset(&spi_blk_buf[3], 0, 2); + memset(&spi_blk_buf[3+16],0, 2); + spi_blk_buf[3+2] =spi_blk_buf[3+2]&0x03; + spi_blk_buf[3+2+16] =spi_blk_buf[3+2+16]&0x03; + } + + ispi_tx_big_block(spi_blk_buf, SPI_BLK_LEN); + + calc_area_u32_check_sum(&area_check.area_imx_w_check, &spi_blk_buf[3], 32); + + bufOffset++; + byte32Cnt++; + + } + } + } + atsc_para.system_para.save_load_data_percent = 100*(byte32Cnt)/(19584); + + //area_check + area_check.area_fpga_w_check = read_fpga_area_u32_check_sum(E_CHECK_FOR_WIRTE); + if(area_check.area_imx_w_check != area_check.area_fpga_w_check){ + printf("Err, a2 imx_w_check not match with fpga_w_check [0x%04x 0x%04x]!\n", area_check.area_imx_w_check, area_check.area_fpga_w_check); + ret = -1; + dpd_ck_status=CK_WR_ERR; + goto CKECK_WRITE_ERR_PROC; + } + else{ + printf("a2 [u32_check]:imx_w_check and fpga_w_check [0x%04x 0x%04x]!\n", area_check.area_imx_w_check, area_check.area_fpga_w_check); + } + + log_printf(LOG_DEBUG, I_USER_CFG, "<< end area2 [read_check]:area2_cnt=%d\n\n", area2_cnt); + fpga_byte_write(DPD_SEG,0x40,0); + } + + //------------------------------------------------------------------------------- + + //[ 7.refresh & bypass clear ] + fpga_byte_write(DPD_SEG,0x41,MASK_TO_FPGA_REFRESH_DATA); + fpga_byte_write(DPD_SEG,0x41,0); + fpga_byte_write(DPD_SEG,FPGA_ADDR_DPD_CTRL1, 0); + + printf("\n\n[area] load all finished.\n"); + + +CKECK_WRITE_ERR_PROC: + if(ret<0){ + fpga_byte_write(DPD_SEG,0x40,0); + fpga_byte_write(DPD_SEG,0x41,0); + + st_extend_state.display_stop=E_DISPLAY_STOP; + delay_ms(500); + while(1){ + + if(st_extend_state.display_stop==E_DISPLAY_END){ + printf(" mthr check display_stoped \n"); + break; + } + delay_ms(400); + printf(" mthr wait display_stop %d\n", st_extend_state.display_stop); + wait_timeout++; + if(wait_timeout>=5){ + printf("Err. timeout wait display_stop %d\n", wait_timeout); + break; + } + } + + fpga_byte_write(DPD_SEG,0x41, 0); + + lcd_write_string(LINE_1,0," ADPC data load error! [9]"); + lcd_write_string(LINE_2,0," "); + lcd_write_cache(); + delay_ms(2000); + } + else{ + st_extend_state.display_stop=E_DISPLAY_STOP; + delay_ms(500); + while(1){ + + if(st_extend_state.display_stop==E_DISPLAY_END){ + printf(" mthr check display_stoped \n"); + break; + } + delay_ms(500); + printf(" mthr wait display_stop %d\n", st_extend_state.display_stop); + wait_timeout++; + if(wait_timeout>=5){ + printf("Err. timeout wait display_stop %d\n", wait_timeout); + break; + } + } + + lcd_write_string(LINE_1,0," WAIT A MOMENT .... "); + lcd_write_string(LINE_2,0," LOADING DATA FINISHED "); + lcd_write_cache(); + delay_ms(2000); + ret = 0; + } + + return ret; +} + + + + +static int read_area_and_store_file() +{ + int ret=0; + uint8 Taddr; + uint16 Iaddr; + uint8 Raddr; + uint16 byte32Cnt=0; + uint16 saveOffset=0; + uint16 bufOffset=0; + uint32 area2_cnt=0; + static uint8 backErr=0; + int i; + uint8 Num; + uint8 temp_buf[20]; + int start_time; + int end_time; + uint8 dpd_data; + backErr = atsc_para.system_para.adpc_err; + dpd_ck_status = CK_OK; + u16 Iaddr_Max = 1023; + u32 wait_timeout=0; + S_CHECK_SUM area_check={0}; + + fpga_byte_write(DPD_SEG,0x41, MASK_TO_SPI_WR_RD_ENABLE); + + + atsc_para.system_para.adpc_err = DPD_SAVE_DATA; + lcd_write_string(LINE_1,0," WAIT A MOMENT .... "); + lcd_write_string(LINE_2,0," SAVING DATA... "); + lcd_write_cache(); + + c256_bytewrite(EEPROM_DPD_FLASH_VALID,0); + clear_dpd_data_file(); + + //区域0+1 + //---------------------------------------------------------------------------------- + + //区域0 + if(1){ + log_printf(LOG_DEBUG, I_USER_CFG, "\n\n[area0]start read area0 data.\n"); + memset(&dataBuffer[0],0,sizeof(dataBuffer)); + + fpga_byte_write(DPD_SEG,0x40, MASK_DPD_DATA_AREA0_MODE); + + clear_check_sum(&area_check); + fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE|MASK_TO_FPGA_CHECK_CLEAR); + fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE); + + for(Taddr=0;Taddr<=31;Taddr++){ + memset(spi_blk_buf, 0, sizeof(spi_blk_buf)); + write_unit_area_addr_to_spi_blkbuf(Taddr,0,0, E_READ, &spi_blk_buf[0]); + ispi_rx_big_block(spi_blk_buf, SPI_BLK_LEN); + calc_area_u32_check_sum(&area_check.area_imx_r_check, &spi_blk_buf[3], 32); + + memcpy(&dataBuffer[0+Taddr*DPD_AREA0_WR_UNIT_DATA_LEN], &spi_blk_buf[3+12], 4); + memcpy(&dataBuffer[0+Taddr*DPD_AREA0_WR_UNIT_DATA_LEN+4], &spi_blk_buf[3+12+16], 4); + } + //area_check + area_check.area_fpga_r_check = read_fpga_area_u32_check_sum(E_CHECK_FOR_RAED); + if(area_check.area_imx_r_check != area_check.area_fpga_r_check){ + printf("Err, a0 imx_r_check not match with fpga_r_check [0x%04x 0x%04x]!\n", area_check.area_imx_r_check, area_check.area_fpga_r_check); + ret = -1; + dpd_ck_status=CK_WR_ERR; + goto CKECK_READ_ERR_PROC; + } + + fpga_byte_write(DPD_SEG,0x40,0); + } + + + //---------------------------------------------------------------------------------- + //区域1 + if(1){ + log_printf(LOG_DEBUG, I_USER_CFG, "\n\n[area1]start read area1 data.\n"); + fpga_byte_write(DPD_SEG,0x40,MASK_DPD_DATA_AREA1_MODE); + + clear_check_sum(&area_check); + fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE|MASK_TO_FPGA_CHECK_CLEAR); + fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE); + + for(Taddr=0;Taddr<=15;Taddr++){ + memset(spi_blk_buf, 0, sizeof(spi_blk_buf)); + write_unit_area_addr_to_spi_blkbuf(Taddr,0,0, E_READ, &spi_blk_buf[0]); + ispi_rx_big_block(spi_blk_buf, SPI_BLK_LEN); + calc_area_u32_check_sum(&area_check.area_imx_r_check, &spi_blk_buf[3], 32); + + memcpy(&dataBuffer[1024+Taddr*DPD_AREA1_WR_UNIT_DATA_LEN], &spi_blk_buf[3], DPD_AREA1_WR_UNIT_DATA_LEN); + } + //area_check + area_check.area_fpga_r_check = read_fpga_area_u32_check_sum(E_CHECK_FOR_RAED); + if(area_check.area_imx_r_check != area_check.area_fpga_r_check){ + printf("Err, a1 imx_r_check not match with fpga_r_check [0x%04x 0x%04x]!\n", area_check.area_imx_r_check, area_check.area_fpga_r_check); + ret = -1; + dpd_ck_status=CK_WR_ERR; + goto CKECK_READ_ERR_PROC; + } + + fpga_byte_write(DPD_SEG,0x40,0); + } + + rw_e2rom_dpd(RW_ADPC_SAVE,E_DPD_AREA_FIRST_4K,0,&dataBuffer[0]); + + + //---------------------------------------------------------------------------------- + //区域3- 5个bit地址- 2^5*8 =256Byte // 32次 + if(1){ + printf("\n\n[area3]start read area3 data.\n"); + memset(&dataBuffer[0],0,sizeof(dataBuffer)); + + fpga_byte_write(DPD_SEG,0x40, MASK_DPD_DATA_AREA3_MODE); + + clear_check_sum(&area_check); + fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE|MASK_TO_FPGA_CHECK_CLEAR); + fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE); + + for(Iaddr=0;Iaddr<=511;Iaddr++){ + memset(spi_blk_buf, 0, sizeof(spi_blk_buf)); + write_unit_area_addr_to_spi_blkbuf(0,Iaddr,0, E_READ, &spi_blk_buf[0]); + ispi_rx_big_block(spi_blk_buf, SPI_BLK_LEN); + calc_area_u32_check_sum(&area_check.area_imx_r_check, &spi_blk_buf[3], 32); + + memcpy(&dataBuffer[Iaddr*DPD_AREA3_WR_UNIT_DATA_LEN], &spi_blk_buf[3+12], 4); + memcpy(&dataBuffer[Iaddr*DPD_AREA3_WR_UNIT_DATA_LEN+4], &spi_blk_buf[3+12+16], 4); + } + //area_check + area_check.area_fpga_r_check = read_fpga_area_u32_check_sum(E_CHECK_FOR_RAED); + if(area_check.area_imx_r_check != area_check.area_fpga_r_check){ + printf("Err, a3 imx_r_check not match with fpga_r_check [0x%04x 0x%04x]!\n", area_check.area_imx_r_check, area_check.area_fpga_r_check); + ret = -1; + dpd_ck_status=CK_WR_ERR; + goto CKECK_READ_ERR_PROC; + } + + fpga_byte_write(DPD_SEG,0x40,0); + rw_e2rom_dpd(RW_ADPC_SAVE,E_DPD_AREA3,0,&dataBuffer[0]); + } + + + + st_extend_state.display_stop=E_DISPLAY_START; + atsc_para.system_para.save_load_data_percent = 0; + + printf("thr start\n"); + thr_display_percent_thread(); + printf("thr end\n"); + + //---------------------------------------------------------------------------------- + //区域2- 9*4*1024*28=1032192Byte=1008KByte + if(1){ + + log_printf(LOG_DEBUG,I_NOUSED,"\n\n[area2]start read area2 data.\n"); + memset(&dataBuffer[0],0,sizeof(dataBuffer)); + area2_cnt =0; + byte32Cnt =0; + saveOffset =0;//存储4k计数 + bufOffset =0;//数据缓冲区偏移 + + Iaddr_Max = 1023; + fpga_byte_write(DPD_SEG,0x40, MASK_DPD_DATA_AREA2_MODE); + + clear_check_sum(&area_check); + fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE|MASK_TO_FPGA_CHECK_CLEAR); + fpga_byte_write(DPD_SEG, 0x41, MASK_TO_SPI_WR_RD_ENABLE); + + for(Taddr=0; Taddr<=8; Taddr++){ + for(Raddr=0; Raddr<=3; Raddr++){ + if(Raddr==2) + continue; + + if(Raddr==3) + Iaddr_Max = 127; + else + Iaddr_Max = 1023; + + for(Iaddr=0; Iaddr<=Iaddr_Max; Iaddr++){ + area2_cnt++; + + start_time = get_current_time_ms(); + + memset(spi_blk_buf, 0, sizeof(spi_blk_buf)); + write_unit_area_addr_to_spi_blkbuf(Taddr,Iaddr,Raddr, E_READ, &spi_blk_buf[0]); + ispi_rx_big_block(spi_blk_buf, SPI_BLK_LEN); + + calc_area_u32_check_sum(&area_check.area_imx_r_check, &spi_blk_buf[3], 32); + + memcpy(&dataBuffer[bufOffset*DPD_AREA2_WR_UNIT_EXT_DATA_LEN], &spi_blk_buf[3], DPD_AREA2_WR_UNIT_EXT_DATA_LEN); + + end_time = get_current_time_ms(); + + byte32Cnt++; + bufOffset++; + + if(bufOffset%128==0){//32*128=4096 // 4KByte数据 + bufOffset=0; + + rw_e2rom_dpd(RW_ADPC_SAVE,E_DPD_AREA2,saveOffset,&dataBuffer[0]);// 4kByte + + memset(&dataBuffer[0],0,sizeof(dataBuffer)); + saveOffset++; + + Num=100*byte32Cnt/(19584); + + //sprintf((char*)temp_buf,"%02d%% %d",Num,flash_get_err_time()); + //log_printf(LOG_DEBUG,I_NOUSED,"%02d%% 4kByte-write to file\n",Num); + atsc_para.system_para.save_load_data_percent = Num; + + //area_check + area_check.area_fpga_r_check = read_fpga_area_u32_check_sum(E_CHECK_FOR_RAED); + if(area_check.area_imx_r_check != area_check.area_fpga_r_check){ + printf("Err, a2 imx_r_check not match with fpga_r_check [0x%04x 0x%04x]!\n", area_check.area_imx_r_check, area_check.area_fpga_r_check); + ret = -1; + dpd_ck_status=CK_WR_ERR; + goto CKECK_READ_ERR_PROC; + } + } + + } + } + } + + if(bufOffset%128!=0){ + rw_e2rom_dpd(RW_ADPC_SAVE,E_DPD_AREA2,saveOffset,&dataBuffer[0]);// 1024Byte + + //area_check + area_check.area_fpga_r_check = read_fpga_area_u32_check_sum(E_CHECK_FOR_RAED); + if(area_check.area_imx_r_check != area_check.area_fpga_r_check){ + printf("Err, a2 imx_r_check not match with fpga_r_check [0x%04x 0x%04x]!\n", area_check.area_imx_r_check, area_check.area_fpga_r_check); + ret = -1; + dpd_ck_status=CK_WR_ERR; + goto CKECK_READ_ERR_PROC; + } + } + + atsc_para.system_para.save_load_data_percent = 100*(byte32Cnt)/(19584); + printf("[read-end]read finished. area2_cnt=%d\n",area2_cnt); + fpga_byte_write(DPD_SEG,0x40, 0); + } + + + //---------------------------------------------------------------------------------- + + fpga_byte_write(DPD_SEG,0x40, 0); + fpga_byte_write(DPD_SEG,0x41, 0); + + c256_bytewrite(EEPROM_DPD_FLASH_VALID,1); + system("sync"); + + //sync display + st_extend_state.display_stop=E_DISPLAY_STOP; + delay_ms(500); + while(1){ + + if(st_extend_state.display_stop==E_DISPLAY_END){ + printf(" mthr check display_stoped \n"); + break; + } + delay_ms(500); + printf(" mthr wait display_stop %d\n", st_extend_state.display_stop); + wait_timeout++; + if(wait_timeout>=5){ + printf("Err. timeout mthr wait display_stop %d\n", wait_timeout); + break; + } + } + + +CKECK_READ_ERR_PROC: + if(dpd_ck_status==CK_WR_ERR){ + fpga_byte_write(DPD_SEG,0x40, 0); + fpga_byte_write(DPD_SEG,0x41, 0); + + //sync display + st_extend_state.display_stop=E_DISPLAY_STOP; + delay_ms(500); + while(1){ + + if(st_extend_state.display_stop==E_DISPLAY_END){ + printf(" mthr check display_stoped \n"); + break; + } + delay_ms(500); + printf(" mthr wait display_stop %d\n", st_extend_state.display_stop); + wait_timeout++; + if(wait_timeout>=5){ + printf("Err. timeout wait display_stop %d\n", wait_timeout); + break; + } + } + + //lcd_write_string(LINE_1,0," DPD READ FPGA CHECK ERROR ! "); + lcd_write_string(LINE_1,0," ADPC data save error! [8] "); + lcd_write_string(LINE_2,0," "); + lcd_write_cache(); + log_printf(LOG_DEBUG,I_NOUSED,"CKECK_READ_ERR_PROC\n"); + delay_ms(2000); + } + + log_printf(LOG_DEBUG,I_NOUSED,"exit read area and store file\n"); + + return ret; +} + + +int dpd_curve_proc(uint8 proc_mode) +{ + u32 u_size; + int ret = 0; + static uint8 backErr=0; + backErr = atsc_para.system_para.adpc_err; + st_extend_state.load_store_curve_flg=1; + + if(proc_mode == E_LOAD_TO_MCU) + { + dpd_total_w_cnt = 0; + dpd_total_r_cnt = 0; + time_start = 0; + time_stop = 0; + clear_dpd_data_file(); + time_start = get_current_time_ms(); + + //store + ret = read_area_and_store_file(); + if(ret != 0){ + log_printf(LOG_ERR, I_SYS_STATUS, "read_area_and_store_file abort!\n"); + } + + time_stop = get_current_time_ms(); + log_printf(LOG_INFO, I_SYS_STATUS, "{time cal to mcu} total_time=%ds ret=%d\n",(time_stop-time_start)/1000, ret); + + //u_size = usr_get_file_size(); + //log_printf(LOG_DEBUG, I_USER_CFG, "file size=%d\n",u_size); + + } + else if(proc_mode == E_LOAD_TO_FPGA) + { + //fpga_byte_write(0x01, 0x26, 0); // RF set OFF ; 此开关顺序宋博要求关闭,因客户不接受射频关掉. + //printf("OFF RF\n"); + dpd_total_w_cnt=0; + dpd_total_r_cnt=0; + time_start=0; + time_stop =0; + time_start = get_current_time_ms(); + + //load + ret = load_file_and_write_area(); + if(ret!=0){ + log_printf(LOG_ERR, I_SYS_STATUS, "load_file_and_write_area abort! %d\n", ret); + } + + time_stop = get_current_time_ms(); + log_printf(LOG_INFO, I_SYS_STATUS, "{time_cal to FPGA} total_time=%ds ret=%d\n",(time_stop-time_start)/1000, ret); + + + //fpga_byte_write(0x01, 0x26, 1); // RF set ON + //printf("ON RF\n"); + } + + if(ret!=0){ + atsc_para.system_para.adpc_err = ret; + if(atsc_para.system_para.adpc==ADPC_HOLD){ + atsc_para.system_para.adpc = ADPC_OFF; + c256_bytewrite(EEPROM_DPD_ADDR, ADPC_OFF); + log_printf(LOG_WARN, I_SYS_STATUS, "adpc curve err, force set adpc to off\n"); + } + } + else + atsc_para.system_para.adpc_err = backErr; + + st_extend_state.load_store_curve_flg=0; + + return ret; +} + +uint8 get_fpga_dpd_check(void) +{ + return dpd_ck_status; +} + +void dpd_exit(void)// 关闭dpd +{ + // ctrl 顺序必须是: 2 - 1 - 3 + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, 0); + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL1, DPD_CTRL1_ALL_BYPS|DPD_CTRL1_DPD_ALLCLR); + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, 0); + u_dpdctl_r23.u8val=0; + u_dpdctl_r23.dpd_bt.rf_sel = DPD_RF_SEL_VALUE(E_SELECT_A); + fpga_byte_write(5,FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); + reset_dpd_to_normal_state(); + + fpga_byte_write(5,FPGA_ADDR_WPP_EN_CLR, 0); + fpga_byte_write(5,FPGA_ADDR_WPP_EN_CLR, MASK_WPP_CLR); + fpga_byte_write(5,FPGA_ADDR_WPP_EN_CLR, 0); + + delay_ms(1000); + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL1, DPD_CTRL1_ALL_BYPS); +} + +void dpd_set_clr(void)// 清除曲线 +{ + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL1, DPD_CTRL1_ALL_BYPS|DPD_CTRL1_DPD_ALLCLR); + delay_ms(1000); + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL1, 0); +} + +void clear_wpp_max(void) +{ + g_wpp_max=0; +} +void remote_set_dpd_clr(void) +{ + dpd_set_clr(); + dpd_exit(); + //dpd_boot_run_init(); + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL1, DPD_CTRL1_ALL_BYPS); +} +static uint8 g_tsnr_up_flg=0; +void set_tsnr_update_flg(uint8 up_flg) +{ + g_tsnr_up_flg = up_flg&0x1; +} +uint8 get_tsnr_update_flg(void) +{ + return g_tsnr_up_flg; +} + + +int boot_tsnr_update(uint8 rst_flg) +{ + static uint8 up_phase = 7; // 实际上就是dpd的7、8、9、10步需要配置的内容 + static uint8 phase_in_flag= 0; + static uint8 sec_cnt = 0; + static uint8 s_fagc_locked= 0; // 相7: 前半段过后锁死FAGC的一次性标志 + uint8 dpd_ctl2_reg = 0; + uint8 dpd_ctl3_reg = 0 ; + uint8 rd_state = 0 ; + int ret_state = 0; + + if(atsc_para.system_para.adpc >= ADPC_UPDATE1) // 正在校正就返回 + return 1; + + + if(rst_flg) { + up_phase = 7; + sec_cnt = 0; + phase_in_flag = 1; + log_printf(LOG_DEBUG,I_NOUSED,"boot_tsnr_update start.\n"); + } + + + switch(up_phase) // 各个phase（阶段）需要进行的处理 + { + case 7: + up_phase=7; + if(phase_in_flag) //进入phase时执行一次的初始化操作 + { + phase_in_flag = 0; + dpd_ctl2_reg = 0; + + dpd_ctl3_reg = (DPD_CTRL3_SYNC_RESTART | DPD_CTRL3_FAGC_UPDATE | DPD_CTRL3_DAGC_UPDATE | DPD_CTRL3_DCRM_UPDATE); + fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); + fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); + + u_dpdctl_r23.u8val = 0; + u_dpdctl_r23.dpd_bt.iqb_upd = 0; + u_dpdctl_r23.dpd_bt.sync_mode = 1; + u_dpdctl_r23.dpd_bt.rf_sel = DPD_RF_SEL_VALUE(E_SELECT_A); + log_printf(LOG_DEBUG,I_NOUSED,"[state] phase 7 ---------------A- 0x%x\n", u_dpdctl_r23.u8val); + fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); + + s_fagc_locked = 0; + } + + // 前半段跑完, 锁死射频AGC, 后半段只留数字AGC收敛 + if(!s_fagc_locked && sec_cnt >= FAGC_LOCK_SEC_SHORT) + { + s_fagc_locked = 1; + // 只清 FAGC_UPDATE(bit0), SYNC_RESTART 保持到相8才放开 + dpd_ctl3_reg = (DPD_CTRL3_SYNC_RESTART | DPD_CTRL3_DAGC_UPDATE | DPD_CTRL3_DCRM_UPDATE); + fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); + log_printf(LOG_DEBUG,I_NOUSED,"[state] phase 7: FAGC locked at %ds, CTRL3=0x%02x\n", + sec_cnt, dpd_ctl3_reg); + } + + // out + if(sec_cnt >= FAGC_PH7_SHORT_SEC){ + up_phase = 8; + sec_cnt = 0; + phase_in_flag = 1; + } + break; + + case 8: + up_phase = 8; + if(phase_in_flag) //进入phase时执行一次的初始化操作 + { + phase_in_flag = 0; + dpd_ctl2_reg = 0; + dpd_ctl3_reg = (DPD_CTRL3_SYNC_UPDATE | DPD_CTRL3_DCRM_UPDATE); + fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); + fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); + log_printf(LOG_DEBUG,I_NOUSED,"[state] phase 8\n"); + } + //out + rd_state = fpga_byte_read(0x05, FPGA_ADDR_DPD_STATUS1); + if(rd_state & MASK_DPD_TRX_SYNC_OK) // 读取到dpd_trx_sync_ok状态为1时进入下一阶段 + { + log_printf(LOG_DEBUG,I_NOUSED,"[state] phase 8 state: TX RX sync OK\n"); + // set fix delay + up_phase = 9; + sec_cnt = 0; + phase_in_flag = 1; + } + else if(sec_cnt >= 15)// 80 超过80秒未读到sync ok， 同步失败，退出校正 + { + log_printf(LOG_DEBUG,I_NOUSED,"[state] phase 8 state: TX RX sync failed\n"); + + //超时处理 + up_phase = 9; + sec_cnt = 0; + phase_in_flag = 1; + } + break; + + case 9: + up_phase = 9; + if(phase_in_flag) + { + phase_in_flag = 0; + + dpd_ctl2_reg = 0; + fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); + + // FAGC 已在相7锁死, 这里不能再放开: 它会和 DAGC 一起跑, 又把 0.43dB + // 的射频台阶注回 DAGC 的输入(主状态机的相9 本来就没有 FAGC, 这里对齐) + dpd_ctl3_reg = DPD_CTRL3_DAGC_UPDATE| DPD_CTRL3_DAGC_SLOWDN | DPD_CTRL3_ROT_UPDATE; + fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); + + u_dpdctl_r23.dpd_bt.iqb_upd = 1; + u_dpdctl_r23.dpd_bt.sync_mode = 1; + u_dpdctl_r23.dpd_bt.rf_sel = DPD_RF_SEL_VALUE(E_SELECT_A); + log_printf(LOG_DEBUG,I_NOUSED,"[state] phase 9 ---------------A- 0x%x\n", u_dpdctl_r23.u8val); + fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); + } + + // out + if(sec_cnt >= 3) + { + up_phase = 10; + sec_cnt = 0; + phase_in_flag = 1; + } + break; + + case 10: + // in + up_phase = 10; + if(phase_in_flag) { + phase_in_flag = 0; + + dpd_ctl2_reg = DPD_CTRL2_RXEQ_UPDATE; + fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); + + dpd_ctl3_reg = DPD_CTRL3_FAGC_UPDATE|DPD_CTRL3_FAGC_SLOWDN; + fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); + + u_dpdctl_r23.dpd_bt.iqb_upd = 0; + fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); + log_printf(LOG_DEBUG,I_NOUSED,"[state] phase 10 --- 0x%x\n", u_dpdctl_r23.u8val); + } + + // out + g_query_operate = 0; + up_phase = 0xff;// left must 0xff + sec_cnt = 0; + phase_in_flag = 0; + ret_state = 1; // left must 1 + log_printf(LOG_DEBUG,I_NOUSED,"boot_tsnr_update end.\n"); + break; + + default: + break; + } + + sec_cnt++; + + return ret_state; +} +//static uint8 t_oneshot_flg=0; +int update_tsnr_uimd_limd(uint8 rst_flg, uint8 *p_phase) +{ + static uint8 up_phase = 7; // 实际上就是dpd的7、8、9、10步需要配置的内容 + static uint8 phase_in_flag= 0; + static uint8 sec_cnt = 0; + static uint8 s_fagc_locked= 0; // 相7: 前半段过后锁死FAGC的一次性标志 + uint8 dpd_ctl2_reg; + uint8 dpd_ctl3_reg; + uint8 rd_state; + int ret_state = 0; + + if(atsc_para.system_para.adpc >= ADPC_UPDATE1) // 正在校正就返回 + return 1; + + if(rst_flg){ + up_phase = 7; + sec_cnt = 0; + phase_in_flag = 1; + log_printf(LOG_DEBUG, I_USER_CFG, "sta.update_tsnr_uimd_limd in new menu.\n"); + } + + *p_phase = up_phase; + switch(up_phase) // 各个phase（阶段）需要进行的处理 + { + case 7: + up_phase=7; + if(phase_in_flag) //进入phase时执行一次的初始化操作 + { + phase_in_flag = 0; + dpd_ctl2_reg = 0; + + dpd_ctl3_reg = (DPD_CTRL3_SYNC_RESTART | + DPD_CTRL3_FAGC_UPDATE | + DPD_CTRL3_DAGC_UPDATE | + DPD_CTRL3_DCRM_UPDATE); + fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); + fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); + + u_dpdctl_r23.u8val=0; + u_dpdctl_r23.dpd_bt.iqb_upd = 0; + u_dpdctl_r23.dpd_bt.sync_mode = 1; + u_dpdctl_r23.dpd_bt.rf_sel = DPD_RF_SEL_VALUE(E_SELECT_A); + fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); + log_printf(LOG_DEBUG, I_USER_CFG, "[state] phase 7 in---------------A- 0x%x\n", u_dpdctl_r23.u8val); + + s_fagc_locked = 0; + } + + // 前半段跑完, 锁死射频AGC, 后半段只留数字AGC收敛 + if(!s_fagc_locked && sec_cnt >= FAGC_LOCK_SEC_SHORT) + { + s_fagc_locked = 1; + // 只清 FAGC_UPDATE(bit0), SYNC_RESTART 保持到相8才放开 + dpd_ctl3_reg = (DPD_CTRL3_SYNC_RESTART | DPD_CTRL3_DAGC_UPDATE | DPD_CTRL3_DCRM_UPDATE); + fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); + log_printf(LOG_DEBUG, I_USER_CFG, "[state] phase 7: FAGC locked at %ds, CTRL3=0x%02x\n", + sec_cnt, dpd_ctl3_reg); + } + + // out + if(sec_cnt >= FAGC_PH7_SHORT_SEC){ + up_phase = 8; + sec_cnt = 0; + phase_in_flag = 1; + log_printf(LOG_DEBUG, I_USER_CFG, "[state] phase 7 out \n"); + } + break; + + case 8: + up_phase = 8; + if(phase_in_flag) //进入phase时执行一次的初始化操作 + { + phase_in_flag = 0; + dpd_ctl2_reg = 0; + dpd_ctl3_reg = (DPD_CTRL3_SYNC_UPDATE| + DPD_CTRL3_DCRM_UPDATE| + DPD_CTRL3_FAGC_UPDATE); + fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); + fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); + log_printf(LOG_DEBUG, I_USER_CFG, "[state] phase 8 in\n"); + } + //out + rd_state = fpga_byte_read(0x05, FPGA_ADDR_DPD_STATUS1); + if(rd_state & MASK_DPD_TRX_SYNC_OK) // 读取到dpd_trx_sync_ok状态为1时进入下一阶段 + { + log_printf(LOG_DEBUG, I_USER_CFG, "[state] phase 8 out, state: TX RX sync OK\n"); + // set fix delay + up_phase = 9; + sec_cnt = 0; + phase_in_flag = 1; + } + else if(sec_cnt >= 15)// 80 超过80秒未读到sync ok， 同步失败，退出校正 + { + //超时处理 + up_phase = 9; + sec_cnt = 0; + phase_in_flag = 1; + log_printf(LOG_DEBUG, I_USER_CFG, "[state] phase 8 out, state: TX RX sync failed\n"); + } + break; + + case 9: + up_phase = 9; + if(phase_in_flag) + { + phase_in_flag = 0; + + dpd_ctl2_reg = 0; + fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); + + dpd_ctl3_reg = DPD_CTRL3_ROT_UPDATE|DPD_CTRL3_FAGC_UPDATE; + fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); + + u_dpdctl_r23.dpd_bt.iqb_upd = 1; + u_dpdctl_r23.dpd_bt.sync_mode = 1; + u_dpdctl_r23.dpd_bt.rf_sel = DPD_RF_SEL_VALUE(E_SELECT_A); + fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); + log_printf(LOG_DEBUG, I_USER_CFG, "[state] phase 9 in---------------A- 0x%x\n", u_dpdctl_r23.u8val); + } + + // out + if(sec_cnt >= 3) // 7 + { + up_phase = 10; + sec_cnt = 0; + phase_in_flag = 1; + log_printf(LOG_DEBUG, I_USER_CFG, "[state] phase 9 out \n"); + } + break; + + case 10: + // in + up_phase = 10; + if(phase_in_flag) { + phase_in_flag = 0; + + dpd_ctl2_reg = DPD_CTRL2_RXEQ_UPDATE; + fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); + + dpd_ctl3_reg = DPD_CTRL3_FAGC_UPDATE; + fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); + + u_dpdctl_r23.dpd_bt.iqb_upd = 0; + fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); + log_printf(LOG_DEBUG, I_USER_CFG, "[state] phase 10 in --- 0x%x\n", u_dpdctl_r23.u8val); + } + + // out + if(sec_cnt >= 2) // 7 + { + g_query_operate = 0; + up_phase = 0xff;// left must 0xff + sec_cnt = 0; + phase_in_flag = 0; + ret_state = 1; // left must 1 + log_printf(LOG_DEBUG, I_USER_CFG, "[state] phase 10 out. \n"); + } + break; + + default: + break; + } + + sec_cnt++; + return ret_state; +} + + +int dpd_log_trig(int trig_enable) +{ +#if DPD_LOG_ENABLE + if(trig_enable>1 || trig_enable<0){ + log_printf(LOG_DEBUG, I_USER_CFG, "trig_enable err, set 0\n"); + trig_enable = 0; + } + + fpga_byte_write(5, FPGA_ADDR_DPD_LOG_TRIG, trig_enable); +#endif + return 0; +} +int dpd_log_file_open(void) +{ + /* + * w+ : 打开一个文本文件，允许读写文件。 + 如果文件已存在，则文件会被截断为零长度， + 如果文件不存在，则会创建一个新文件。 + */ +#if DPD_LOG_ENABLE + if(p_dpd_log_fp != NULL){ + log_printf(LOG_ERR, I_USER_CFG, "dpd log has opened.\n"); + return 0; + } + + p_dpd_log_fp = fopen(DPD_LOG_FILE, "w+"); + if (p_dpd_log_fp == NULL){ + log_printf(LOG_ERR, I_USER_CFG, "dpd log file open failed.\n"); + return -1; + }else + log_printf(LOG_DEBUG, I_USER_CFG, "dpd log file open success.\n"); + + + struct tm tmBJ; + get_beijing_time(&tmBJ); + fprintf(p_dpd_log_fp, "[%04d-%02d-%02d %02d:%02d:%02d] open %s success.\n\n", + tmBJ.tm_year, tmBJ.tm_mon, tmBJ.tm_mday, tmBJ.tm_hour, tmBJ.tm_min, tmBJ.tm_sec, DPD_LOG_FILE); +#endif + return 0; +} + +int dpd_log_file_close( char *whyclose) +{ +#if DPD_LOG_ENABLE + + if(p_dpd_log_fp == NULL || whyclose == NULL) { + log_printf(LOG_ERR, I_USER_CFG, "[%s] null or whyclose null\n", DPD_LOG_FILE); + return -1; + } + + struct tm tmBJ; + get_beijing_time(&tmBJ); + + fprintf(p_dpd_log_fp, "\n\n[%04d-%02d-%02d %02d:%02d:%02d] close %s, case [%s]\n\n", + tmBJ.tm_year, tmBJ.tm_mon, tmBJ.tm_mday, tmBJ.tm_hour, tmBJ.tm_min, tmBJ.tm_sec, DPD_LOG_FILE, whyclose); + + if(p_dpd_log_fp != NULL) + fclose(p_dpd_log_fp); + + log_printf(LOG_DEBUG, I_USER_CFG, "dpd log file close success\n"); + p_dpd_log_fp = NULL; +#endif + return 0; +} + + + +int dpd_log_read_and_save(int phase) +{ +#if DPD_LOG_ENABLE + uint8 log_data[24] = {0}; + S_DPD_LOG_TYPE ldata; + struct tm tmBJ; + static int bak_phase = 0; + int i = 0; + + if(p_dpd_log_fp == NULL) { + log_printf(LOG_ERR, I_USER_CFG, "%s null\n", DPD_LOG_FILE); + return -1; + } + + dpd_log_trig(1); + + // read data from FPGA segment 5 [0x20--0x37] + fpga_byte_reads(5, FPGA_ADDR_DPD_CTRL1, log_data, 24); + + ldata.rx_fgain_cw_i = (log_data[0] << 0) + (log_data[1] << 8); + ldata.rx_dgain_i = (log_data[2] << 0) + (log_data[3] << 8); + ldata.txpow_cur_i = (log_data[4] << 0) + (log_data[5] << 8); + ldata.txaveamp_i = (log_data[6] << 0) + (log_data[7] << 8); + ldata.ob_wpp_max_i = (log_data[8] << 0) + (log_data[9] << 8); + ldata.rx_data_iq_i = (log_data[10] << 0) + (log_data[11] << 8) + (log_data[12] << 16) + (log_data[13] << 24); + ldata.tx_data_iq_i = (log_data[14] << 0) + (log_data[15] << 8) + (log_data[16] << 16) + (log_data[17] << 24); + ldata.dpd_dynamic_gain_i = (log_data[18] << 0) + (log_data[19] << 8); + ldata.ob_b_pwr_i = (log_data[20] << 0) + (log_data[21] << 8); + ldata.ob_a_pwr_i = (log_data[22] << 0) + (log_data[23] << 8); + + if(bak_phase != phase) { + get_beijing_time(&tmBJ); + fprintf(p_dpd_log_fp, "[%02d:%02d:%02d]************* phase %d ****************\n",tmBJ.tm_hour, tmBJ.tm_min, tmBJ.tm_sec, phase); + bak_phase = phase; + } + + fprintf(p_dpd_log_fp, "tx_data_iq_i = 0x%08x\n", ldata.tx_data_iq_i); + fprintf(p_dpd_log_fp, "rx_data_iq_i = 0x%08x\n", ldata.rx_data_iq_i); + fprintf(p_dpd_log_fp, "ob_wpp_max_i = 0x%04x\n", ldata.ob_wpp_max_i); + fprintf(p_dpd_log_fp, "txaveamp_i = 0x%04x\n", ldata.txaveamp_i); + fprintf(p_dpd_log_fp, "txpow_cur_i = 0x%04x\n", ldata.txpow_cur_i); + fprintf(p_dpd_log_fp, "rx_dgain_i = 0x%04x\n", ldata.rx_dgain_i); + fprintf(p_dpd_log_fp, "rx_fgain_cw_i = 0x%04x\n", ldata.rx_fgain_cw_i); + fprintf(p_dpd_log_fp, "dpd_dynamic_gain_i = 0x%04x\n", ldata.dpd_dynamic_gain_i); + fprintf(p_dpd_log_fp, "ob_b_pwr_i = 0x%04x\n", ldata.ob_b_pwr_i); + fprintf(p_dpd_log_fp, "ob_a_pwr_i = 0x%04x\n\n\n", ldata.ob_a_pwr_i); + + dpd_log_trig(0); + +#endif + return 0; +} + +int dpd_log_read_and_save_end(char * say) +{ +#if DPD_LOG_ENABLE + uint8 log_data[24] = {0}; + S_DPD_LOG_TYPE ldata; + struct tm tmBJ; + int i = 0; + + if(p_dpd_log_fp == NULL) { + log_printf(LOG_ERR, I_USER_CFG, "%s null\n", DPD_LOG_FILE); + return -1; + } + + dpd_log_trig(1); + + // read data from FPGA segment 5 [0x20--0x37] + fpga_byte_reads(5, FPGA_ADDR_DPD_CTRL1, log_data, 24); + + ldata.rx_fgain_cw_i = (log_data[0] << 0) + (log_data[1] << 8); + ldata.rx_dgain_i = (log_data[2] << 0) + (log_data[3] << 8); + ldata.txpow_cur_i = (log_data[4] << 0) + (log_data[5] << 8); + ldata.txaveamp_i = (log_data[6] << 0) + (log_data[7] << 8); + ldata.ob_wpp_max_i = (log_data[8] << 0) + (log_data[9] << 8); + ldata.rx_data_iq_i = (log_data[10] << 0) + (log_data[11] << 8) + (log_data[12] << 16) + (log_data[13] << 24); + ldata.tx_data_iq_i = (log_data[14] << 0) + (log_data[15] << 8) + (log_data[16] << 16) + (log_data[17] << 24); + ldata.dpd_dynamic_gain_i = (log_data[18] << 0) + (log_data[19] << 8); + ldata.ob_b_pwr_i = (log_data[20] << 0) + (log_data[21] << 8); + ldata.ob_a_pwr_i = (log_data[22] << 0) + (log_data[23] << 8); + + + get_beijing_time(&tmBJ); + fprintf(p_dpd_log_fp, "[%02d:%02d:%02d]************* will end ****************\n", tmBJ.tm_hour, tmBJ.tm_min, tmBJ.tm_sec); + if(say != NULL) + fprintf(p_dpd_log_fp, " %s \n", say); + + fprintf(p_dpd_log_fp, "tx_data_iq_i = 0x%08x\n", ldata.tx_data_iq_i); + fprintf(p_dpd_log_fp, "rx_data_iq_i = 0x%08x\n", ldata.rx_data_iq_i); + fprintf(p_dpd_log_fp, "ob_wpp_max_i = 0x%04x\n", ldata.ob_wpp_max_i); + fprintf(p_dpd_log_fp, "txaveamp_i = 0x%04x\n", ldata.txaveamp_i); + fprintf(p_dpd_log_fp, "txpow_cur_i = 0x%04x\n", ldata.txpow_cur_i); + fprintf(p_dpd_log_fp, "rx_dgain_i = 0x%04x\n", ldata.rx_dgain_i); + fprintf(p_dpd_log_fp, "rx_fgain_cw_i = 0x%04x\n", ldata.rx_fgain_cw_i); + fprintf(p_dpd_log_fp, "dpd_dynamic_gain_i = 0x%04x\n", ldata.dpd_dynamic_gain_i); + fprintf(p_dpd_log_fp, "ob_b_pwr_i = 0x%04x\n", ldata.ob_b_pwr_i); + fprintf(p_dpd_log_fp, "ob_a_pwr_i = 0x%04x\n\n\n", ldata.ob_a_pwr_i); + + dpd_log_trig(0); + +#endif + return 0; +} + +int dpd_log_string_save(char* string) +{ +#if DPD_LOG_ENABLE + + if(p_dpd_log_fp == NULL) { + log_printf(LOG_ERR, I_USER_CFG, "dpd_log_string_save [%s] fp is null\n", DPD_LOG_FILE); + return -1; + } + + if(string != NULL) + fprintf(p_dpd_log_fp, " %s \n", string); +#endif + return 0; +} + +uint8 conv_adpc_err_output(uint8 raw_dpd_err) +{ + uint8 output_err=0; + + switch(raw_dpd_err) + { + case DPD_STATE_ERR: + output_err=1; //DPD stop,PA protection + break; + case DPD_STATE_POWER_HIGH: + output_err=2; //DPD fail,Feedback high + break; + case DPD_STATE_POWER_LOW: + output_err=3; //DPD fail,Feedback low + break; + case DPD_STATE_POWER_TOO_HIGH: + output_err=4; //DPD fail,Feedback high + break; + case DPD_STATE_POWER_TOO_LOW: + output_err=5; //DPD fail,Feedback low + break; + case DPD_STATE_ERR_OVER_RANGE: + output_err=6; //DPD stop, Over distortion or DPD stop, Check RF filter + break; + case DPD_CHECK_WPP_ERR_EXIT_HOLD: + output_err=7; //DPD stop,PA protection + break; + case DPD_READ_CKECK_ERR: + output_err=8; //DPD data save error + break; + case DPD_WRITE_CHECK_ERR: + output_err=9; //DPD data load error + break; + case DPD_SYNC_TIMEOUT: + output_err=10; //DPD SYNC_TIMEOUT + break; + default: + break; + } + + return output_err; +} + + +void set_ab_switch(E_AB_SEL ab_val) +{ + u_dpdctl_r23.dpd_bt.rf_sel = DPD_RF_SEL_VALUE(ab_val); + fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); +} + +void little_balance(S_SYSTEM_PARA * psys) +{ + S_SYS_TIME bak_time = {0xff,};//本地时间 + S_SYS_TIME now_time = {0,}; + int ret = 0; + uint8 reset_up = 1; + uint8 uuu_phase = 0; + uint8 old_phase = 0; + char show_perc[5] = {0}; + psys->final_stage = 3; + + while(1) + { + get_sys_time(&now_time); + + if(bak_time.sec != now_time.sec) { + pthread_mutex_lock(&mtx_phase78910_again); + ret = update_tsnr_uimd_limd(reset_up,&uuu_phase); + if(reset_up) + reset_up = 0; + if(uuu_phase!=old_phase){ + psys->final_stage = 10-uuu_phase; + old_phase = uuu_phase; + } + + if(ret == 1) { + pthread_mutex_unlock(&mtx_phase78910_again); + break; + } + pthread_mutex_unlock(&mtx_phase78910_again); + + get_sys_time(&bak_time); + } + usleep(20000);// 20ms + } + + reset_dpd_to_normal_state(); + psys->final_stage = 0xff; + +} + + +void refresh_waiting(void *parg,void *parv) +{ + uint8 retime = atsc_para.system_para.final_stage; + char show_perc[5] = {0}; + + lcd_write_string(LINE_1,0," WAIT A MOMENT .... "); + lcd_write_string(LINE_2,0," FINAL STAGE "); + + if(retime != 0xff){ + sprintf(show_perc, "%d ", retime); + lcd_write_string(LINE_2, 15, show_perc); + } +} + +void refresh_update_dpd(void *parg,void *parv) +{ + S_SYSTEM_PARA *psys = &atsc_para.system_para; + uint16 dpd_disp_step = 0; //static int dpd_phase = 0; static int phase_in_flag = 0; static int sec_cnt = 0; @@ -1859,92 +1860,92 @@ void refresh_update_dpd(void *parg,void *parv) static uint32 disp_sec = 0; //uint8 l_imd=0,u_imd=0; uint16 tx_pow,err_pow; - uint16 dpow_limit,dpow_cur; - uint16 u16_tsnr; - uint16 wpp_max=0; //wpp保护状态 - uint8 wpp_abort=0; - float f_tsnr; - uint8 rd_reg; - uint8 dpd_ctl1_reg, dpd_ctl2_reg, dpd_ctl3_reg; - uint8 dpd_sat_flg = 0; - static uint8 st_check_wpp_en=1; - - static uint16 s_ms200_cnt=0; - static uint16 g_skip_next_dly =20; - static uint8 g_prompt_skip_wpp=0; - static uint8 pflg=0; + uint16 dpow_limit,dpow_cur; + uint16 u16_tsnr; + uint16 wpp_max=0; //wpp保护状态 + uint8 wpp_abort=0; + float f_tsnr; + uint8 rd_reg; + uint8 dpd_ctl1_reg, dpd_ctl2_reg, dpd_ctl3_reg; + uint8 dpd_sat_flg = 0; + static uint8 st_check_wpp_en=1; + + static uint16 s_ms200_cnt=0; + static uint16 g_skip_next_dly =20; + static uint8 g_prompt_skip_wpp=0; + static uint8 pflg=0; static uint8 g_pow_state_check=0; static uint8 stc_insert_step=0; - static uint8 s_fagc_locked=0; // 相1/相7: 前半段过后锁死FAGC的一次性标志 - struct timeval now_tv; + static uint8 s_fagc_locked=0; // 相1/相7: 前半段过后锁死FAGC的一次性标志 + struct timeval now_tv; uint32 now_sec; - - disp_sec++; - - //配置初始化并启动 - if(psys->adpc_step == 1) - { - log_printf(LOG_DEBUG, I_USER_CFG, "\r\n ******** start dpd process ***************\r\n"); - dpd_log_file_open(); - - /* 3 每次矫正开始之前清除一下曲线 */ - /*dpd_set_clr();//SPL_CURV_LOAD_STORE - */ + + disp_sec++; + + //配置初始化并启动 + if(psys->adpc_step == 1) + { + log_printf(LOG_DEBUG, I_USER_CFG, "\r\n ******** start dpd process ***************\r\n"); + dpd_log_file_open(); + + /* 3 每次矫正开始之前清除一下曲线 */ + /*dpd_set_clr();//SPL_CURV_LOAD_STORE + */ //初始为phase 1 phase_in_flag = 1; sec_cnt = 0; last_sec_tick = 0; wpp_max = 0; s_ms200_cnt = 0; - - set_force_stop_adpc(FALSE); - set_boot_tsnr_up_state(E_STA_BOOT_TRIGGER_END); - - psys->adpc_err = DPD_STATUS_UPDATING; - u_dpdctl_r23.u8val=0; - - psys->final_stage = 0xff; - - if(psys->adpc == ADPC_UPDATE2) - psys->dpd_phase = 7; - else - psys->dpd_phase = 1; - - log_printf(LOG_DEBUG, I_USER_CFG, "adpc=%d, start from dpd_phase %d\n", psys->adpc, psys->dpd_phase); - - - g_query_save = 0; - g_query_operate = 0; - g_query_skip = E_QUERY; - dpd_ck_status = CK_OK; - g_prompt_skip_wpp = 0; - g_query_wpp_to_save = 0; - st_check_wpp_en =1; - clear_wpp_max(); - g_skip_next_dly = 20; - g_pow_state_check = 0; - s_fagc_locked = 0; - - fpga_byte_write(5,FPGA_ADDR_DPD_CFG_STEP, 0); - fpga_byte_write(5,0x25, 0xff); // 更新间隔 - fpga_byte_write(5,0x26, 0); // 更新间隔 - - //初始化配置，所有的 “控制”寄存器全部置0, !!! 2 - 1 - 3 - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, 0); - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL1, 0); - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, 0); - - fpga_byte_write(5,FPGA_ADDR_WPP_EN_CLR, 0); - fpga_byte_write(5,FPGA_ADDR_WPP_EN_CLR, MASK_WPP_CLR); - fpga_byte_write(5,FPGA_ADDR_WPP_EN_CLR, MASK_WPP_ENABLE); - - dpd_ctl1_reg = DPD_CTRL1_DPD_START; - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL1, dpd_ctl1_reg); - - psys->adpc_step=2; - } - - //循环检测状态，正常时才执行dpd过程的循环，错误时退出 + + set_force_stop_adpc(FALSE); + set_boot_tsnr_up_state(E_STA_BOOT_TRIGGER_END); + + psys->adpc_err = DPD_STATUS_UPDATING; + u_dpdctl_r23.u8val=0; + + psys->final_stage = 0xff; + + if(psys->adpc == ADPC_UPDATE2) + psys->dpd_phase = 7; + else + psys->dpd_phase = 1; + + log_printf(LOG_DEBUG, I_USER_CFG, "adpc=%d, start from dpd_phase %d\n", psys->adpc, psys->dpd_phase); + + + g_query_save = 0; + g_query_operate = 0; + g_query_skip = E_QUERY; + dpd_ck_status = CK_OK; + g_prompt_skip_wpp = 0; + g_query_wpp_to_save = 0; + st_check_wpp_en =1; + clear_wpp_max(); + g_skip_next_dly = 20; + g_pow_state_check = 0; + s_fagc_locked = 0; + + fpga_byte_write(5,FPGA_ADDR_DPD_CFG_STEP, 0); + fpga_byte_write(5,0x25, 0xff); // 更新间隔 + fpga_byte_write(5,0x26, 0); // 更新间隔 + + //初始化配置，所有的 “控制”寄存器全部置0, !!! 2 - 1 - 3 + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, 0); + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL1, 0); + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, 0); + + fpga_byte_write(5,FPGA_ADDR_WPP_EN_CLR, 0); + fpga_byte_write(5,FPGA_ADDR_WPP_EN_CLR, MASK_WPP_CLR); + fpga_byte_write(5,FPGA_ADDR_WPP_EN_CLR, MASK_WPP_ENABLE); + + dpd_ctl1_reg = DPD_CTRL1_DPD_START; + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL1, dpd_ctl1_reg); + + psys->adpc_step=2; + } + + //循环检测状态，正常时才执行dpd过程的循环，错误时退出 while(psys->adpc_step == 2) { if(atsc_adpc_force_stop_flag == TRUE) { @@ -1953,959 +1954,960 @@ void refresh_update_dpd(void *parg,void *parv) dpow_limit = (fpga_byte_read(0x05,0x14)<<8)|fpga_byte_read(0x05,0x13); dpow_cur = (fpga_byte_read(0x05,0x16)<<8)|fpga_byte_read(0x05,0x15); - - tx_pow = (fpga_byte_read(0x05,0x03)<<8)|fpga_byte_read(0x05,0x02); - err_pow = (fpga_byte_read(0x05,0x05)<<8)|fpga_byte_read(0x05,0x04); - - f_tsnr = 10*log10(tx_pow*64.0/err_pow)*100+TSNR_FIX;//放大100 - if(f_tsnr < 0) - f_tsnr = 0; - - u16_tsnr = (uint16)f_tsnr; - - (void)check_lcd_light(TYPE_KEY); //确保屏幕不灭 - - if(st_check_wpp_en==1){ - wpp_abort = fpga_byte_read(0x05,0x0d); - } - wpp_max = (fpga_byte_read(0x05,0x0f)<<8)|fpga_byte_read(0x05,0x0e); - - #if 1 - if(wpp_abort&0x01){//dpd由于脉冲功率过大导致保护 @20210907调整为出现该保护，提示结束及保持曲线确认 - - // 0. if checked wpp at phase 6, then clr wpp status and disable wpp check, auto skip to phase 7 - if(psys->dpd_phase==6) - { - if(atsc_para.wj_para.ctl_dpd==E_DPD_NSAVE_FLITER ||atsc_para.wj_para.ctl_dpd==E_DPD_SAVE_FLITER){ - // 1.clr wpp status - wpp_max = (fpga_byte_read(0x05,0x0f)<<8)|fpga_byte_read(0x05,0x0e); - log_printf(LOG_DEBUG, I_USER_CFG, "ph6 before clr maxwpp=%d,wppabort=%d\n",wpp_max,wpp_abort&0x01); - g_wpp_max = wpp_max; - - fpga_byte_write(5,FPGA_ADDR_WPP_EN_CLR, 0); - fpga_byte_write(5,FPGA_ADDR_WPP_EN_CLR, MASK_WPP_CLR); - fpga_byte_write(5,FPGA_ADDR_WPP_EN_CLR, MASK_WPP_ENABLE); - - wpp_max = (fpga_byte_read(0x05,0x0f)<<8)|fpga_byte_read(0x05,0x0e); - log_printf(LOG_DEBUG, I_USER_CFG, "ph6 after clr maxwpp=%d,wppabort=%d\n",wpp_max,wpp_abort&0x01); - - g_query_wpp_to_save=0; - - // 2.disable wpp check - st_check_wpp_en = 0; - - // 3.prompt skip to next - g_prompt_skip_wpp=1; - log_printf(LOG_DEBUG, I_USER_CFG, "sta-%d wpp to next\n",psys->dpd_phase); - } - else{ - // 3.prompt err - g_wpp_max = wpp_max; - g_prompt_skip_wpp=1; - } - } - else{ - - g_wpp_max = wpp_max; - psys->adpc_err=DPD_CHECK_WPP_ERR_EXIT_HOLD;//DPD_CHECK_WPP_ERR_EXIT - log_printf(LOG_DEBUG, I_USER_CFG, "sta-%d esc wpp maxwpp=%d,wppabort=%d\n",psys->dpd_phase,wpp_max,wpp_abort&0x01); - - goto DPD_END;//DPD_SAVE_PROC; - } - - } - #endif - - /* 读取状态 >>>> *///------------------------------------- - rd_reg = fpga_byte_read(5,FPGA_ADDR_DPD_STATUS1); - - if(rd_reg & MASK_DPD_SAT_FLG){ - dpd_sat_flg = 1;//只做显示 - } - else{ - dpd_sat_flg = 0; - } - if(rd_reg & MASK_DPD_ERR)//bit-0 //出现 DPD error状态 - { - psys->adpc_err = DPD_STATE_ERR; - log_printf(LOG_DEBUG, I_USER_CFG, "\b DPD caused tx power rise too much\r\n"); - dpd_log_string_save("Step 2. DPD caused tx power rise too much. Will DPD_END"); - goto DPD_END; - } - - if(rd_reg & MASK_DPD_ERR_ABORT)//bit-3 //出现 adpc_err_aborto 状态 - { - psys->adpc_err = DPD_STATE_ERR_OVER_RANGE; - log_printf(LOG_DEBUG, I_USER_CFG, "\b DPD Abort due to large errors\r\n"); - dpd_log_string_save( "Step 2. DPD Abort due to large errors. Will DPD_END"); - goto DPD_END; - } - - if(g_pow_state_check) - { - if(rd_reg & MASK_DPD_PWRLOW)//bit-2 //出现 dpd_powerislow状态 - { - psys->adpc_err = DPD_STATE_POWER_LOW; - log_printf(LOG_DEBUG, I_USER_CFG, "\b Feedback power is low\r\n"); - dpd_log_string_save( "Step 2. Feedback power is low. Will DPD_END"); - goto DPD_END; - } - if(rd_reg & MASK_DPD_PWRHIGH)//bit-1 //出现 dpd_powerishigh状态 - { - psys->adpc_err = DPD_STATE_POWER_HIGH; - log_printf(LOG_DEBUG, I_USER_CFG, "\b Feedback power is high\r\n"); - dpd_log_string_save( "Step 2. Feedback power is high. Will DPD_END"); - goto DPD_END; - } - } - - if(psys->dpd_phase>1){ // 过了phase1以后才检测的状态 - if(rd_reg & MASK_DPD_DAGC_TOOLOW) //bit-6 - { - psys->adpc_err = DPD_STATE_POWER_TOO_LOW; - log_printf(LOG_DEBUG, I_USER_CFG, "\b DPD Abort due to DAGC input LOW\r\n"); - dpd_log_string_save( "Step 2. DPD Abort due to DAGC input LOW. Will DPD_END"); - goto DPD_END; - } - - if(rd_reg & MASK_DPD_DAGC_TOOHIGH)//bit-5 - { - psys->adpc_err = DPD_STATE_POWER_TOO_HIGH; - log_printf(LOG_DEBUG, I_USER_CFG, "\b DPD Abort due to DAGC input HIGH\r\n"); - dpd_log_string_save( "Step 2. DPD Abort due to DAGC input HIGH. Will DPD_END"); - goto DPD_END; - } - } - - /* 读取状态 <<<< *///------------------------------------- - - - - - //校正过程 - switch(psys->dpd_phase) // 各个phase（阶段）需要进行的处理 - { - case 1: - ////////////// 1.AGC - // in - psys->dpd_phase=1; - if(phase_in_flag) //进入phase时执行一次的初始化操作 - { - phase_in_flag = 0; - - dpd_ctl2_reg = 0; - dpd_ctl3_reg = (DPD_CTRL3_SYNC_RESTART | DPD_CTRL3_FAGC_UPDATE | DPD_CTRL3_DAGC_UPDATE | DPD_CTRL3_DCRM_UPDATE ); // - fpga_byte_write(0x05,FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); - fpga_byte_write(0x05,FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); - - fpga_byte_write(0x05, FPGA_ADDR_WPP_EN_CLR, 0); // 关闭WPP保护 - fpga_byte_write(0x05, FPGA_ADDR_WPP_EN_CLR, MASK_WPP_CLR); // 清除MAXP - fpga_byte_write(0x05, FPGA_ADDR_WPP_EN_CLR, MASK_WPP_ENABLE); //打开WPP保护 - - u_dpdctl_r23.u8val = 0; - u_dpdctl_r23.dpd_bt.iqb_upd = 1; - u_dpdctl_r23.dpd_bt.sync_mode = 0; - u_dpdctl_r23.dpd_bt.rf_sel = 1; - fpga_byte_write(5,FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); - log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 1: 0x%x\n", u_dpdctl_r23.u8val); - - s_fagc_locked = 0; - } - - // 前半段跑完, 锁死射频AGC, 后半段只留数字AGC收敛(见 FAGC_LOCK_SEC 注释) - if(!s_fagc_locked && sec_cnt >= FAGC_LOCK_SEC) - { - s_fagc_locked = 1; - // 只清 FAGC_UPDATE(bit0), SYNC_RESTART 必须继续保持到相2才放开 - dpd_ctl3_reg = (DPD_CTRL3_SYNC_RESTART | DPD_CTRL3_DAGC_UPDATE | DPD_CTRL3_DCRM_UPDATE); - fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); - log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 1: FAGC locked at %ds, CTRL3=0x%02x\n", - sec_cnt, dpd_ctl3_reg); - dpd_log_string_save("phase 1. FAGC locked, DAGC only"); - } - - // Keep the same raw FPGA signal trace used by phases 3-10 so - // the FAGC-to-DAGC handover can be analysed end-to-end. - dpd_log_read_and_save(psys->dpd_phase); - - // out - if(sec_cnt >= 20 || g_query_skip == E_QUERY_SKIP){ // 计时超过20秒离开phase1 - g_pow_state_check = 1; - - if(g_query_skip == E_QUERY_SKIP)g_query_skip=E_QUERY; - psys->dpd_phase=2; // 离开前进行的操作 - sec_cnt = 0; - phase_in_flag = 1; - } - break; - - case 2: - ////////////// 2.TX RX SYNC - // in - psys->dpd_phase=2; - if(phase_in_flag) //进入phase时执行一次的初始化操作 - { - phase_in_flag = 0; - dpd_ctl2_reg = 0; - dpd_ctl3_reg = (DPD_CTRL3_SYNC_UPDATE | DPD_CTRL3_DCRM_UPDATE); - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); - } - - // Phase 2 can be short when TX/RX sync is already locked, so - // sample on every state-machine pass instead of entry only. - dpd_log_read_and_save(psys->dpd_phase); - - //out - if(rd_reg & MASK_DPD_TRX_SYNC_OK || g_query_skip == E_QUERY_SKIP) // 读取到dpd_trx_sync_ok状态为1时进入下一阶段 - { - if(g_query_skip == E_QUERY_SKIP)g_query_skip=E_QUERY; - - // set fix delay - psys->dpd_phase=3; - sec_cnt = 0; - phase_in_flag = 1; - } - else if(sec_cnt >= 80)// 超过80秒为读到sync ok， 同步失败，退出校正 - { - log_printf(LOG_DEBUG, I_USER_CFG, "\b TX RX sync failed\r\n"); - psys->adpc_err = DPD_SYNC_TIMEOUT; - goto DPD_END; - } - break; - - - case 3: - ////////////// 3.ROT - // in - psys->dpd_phase=3; - if(phase_in_flag) - { - phase_in_flag = 0; - dpd_ctl2_reg = 0; - //dpd_ctl3_reg = DPD_CTRL3_ROT_UPDATE; - dpd_ctl3_reg = DPD_CTRL3_DAGC_UPDATE|DPD_CTRL3_DAGC_SLOWDN|DPD_CTRL3_ROT_UPDATE; - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); - } - dpd_log_read_and_save( psys->dpd_phase); - // out - if(sec_cnt >= 30 || g_query_skip == E_QUERY_SKIP) // 计时到15秒进入下一阶段 - { - if(g_query_skip == E_QUERY_SKIP) { - g_query_skip = E_QUERY; - sec_cnt=0xffff; - } - dpd_log_read_and_save( psys->dpd_phase); - if(atsc_para.dpd_para.dpd_mode==E_DPD_MODE_MANUAL) {//MANUAL - if(g_query_operate==0) - g_query_operate = E_QUERY; - if(g_query_operate == E_QUERY_UP_STOP) { - g_query_operate = 0; - sec_cnt = 0; - psys->adpc_step = 3; - atsc_para.system_para.adpc = ADPC_OFF; - c256_bytewrite(EEPROM_DPD_ADDR,ADPC_OFF); - dpd_log_string_save( "phase 3. MANUAL E_QUERY_SKIP. Will DPD_SUCCESS"); - goto DPD_SUCCESS; - } - else if(g_query_operate==E_QUERY_OK_CONTINUE) { - g_query_operate=0; - psys->dpd_phase=4; - sec_cnt = 0; - phase_in_flag = 1; - dpd_log_string_save("phase 3. MANUAL E_QUERY_OK_CONTINUE. Will enter phase 4"); - } - else if(g_query_operate==E_QUERY_ESC_EXIT) { - g_query_operate=0; - sec_cnt = 0; - phase_in_flag = 1; - psys->adpc_err=DPD_PROC_EXIT; - dpd_log_string_save("phase 3. MANUAL E_QUERY_ESC_EXIT. Will DPD_END"); - goto DPD_END; - } - - } - else{//AUTO - dpd_log_read_and_save( psys->dpd_phase); - g_query_operate=0; - psys->dpd_phase=4; - sec_cnt = 0; - phase_in_flag = 1; - dpd_log_string_save("phase 3. AUTO. Will enter phase 4"); - } - } - break; - - case 4: - ////////////// 4.Linear update - // in - psys->dpd_phase = 4; - if(phase_in_flag) - { - stc_insert_step = 0; - phase_in_flag = 0; - dpd_ctl2_reg = (DPD_CTRL2_LIN_UPDATE | DPD_CTRL2_AMP_CHK ); - - fpga_byte_write(5,0x25, 0xff); - fpga_byte_write(5,0x26, 0x08); - - u_dpdctl_r23.dpd_bt.iqb_upd = 0; - fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); - log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 4: 0x%x\n", u_dpdctl_r23.u8val); - - log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 4 0x26-0x08\n"); - dpd_log_string_save("phase 4 0x26-0x08"); - - dpd_ctl3_reg = (DPD_CTRL3_DAGC_UPDATE|DPD_CTRL3_DAGC_SLOWDN); - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); - } - dpd_log_read_and_save(psys->dpd_phase); - // out - if(sec_cnt >= 90 || g_query_skip == E_QUERY_SKIP) { - if(g_query_skip == E_QUERY_SKIP){g_query_skip=E_QUERY;sec_cnt=0xffff;} - - if(atsc_para.dpd_para.dpd_mode == E_DPD_MODE_MANUAL) - {//MANUAL - if(g_query_operate == 0) - g_query_operate = E_QUERY; - - if(g_query_operate == E_QUERY_UP_STOP) { - g_query_operate = 0; - sec_cnt = 0; - psys->adpc_step = 3; - atsc_para.system_para.adpc = ADPC_OFF; - c256_bytewrite(EEPROM_DPD_ADDR,ADPC_OFF); - dpd_log_string_save( "phase 4.(MANUAL) E_QUERY_SKIP. Will DPD_SUCCESS"); - goto DPD_SUCCESS; - } - else if(g_query_operate==E_QUERY_OK_CONTINUE) - { - g_query_operate=0; - psys->dpd_phase=5; - sec_cnt = 0; - phase_in_flag = 1; - dpd_log_string_save( "phase 4.(MANUAL) E_QUERY_OK_CONTINUE. Will enter phase 5"); - } - else if(g_query_operate==E_QUERY_ESC_EXIT) - { - g_query_operate=0; - sec_cnt = 0; - phase_in_flag = 1; - psys->adpc_err=DPD_PROC_EXIT; - dpd_log_string_save( "phase 4.(MANUAL) E_QUERY_ESC_EXIT. Will DPD_END"); - goto DPD_END; - } - - } - else{//AUTO - if(stc_insert_step==0){ - stc_insert_step = 1; - - //1. 在4结束后，lin_update_set = 0, 同时把0x21的bit7 设置为1。其它都不动； - dpd_ctl2_reg = (DPD_CTRL2_AMP_CHK | DPD_CTRL2_POLYESTI_UPDATE); - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg);//0x21 - printf("phase4 end-5s set Reg0x21=0x%x\n", dpd_ctl2_reg); - } - - if(sec_cnt >= 90+5){ - - //2. 过个5秒左右，0x21 的bit7 设置为0，然后进入状态5； - dpd_ctl2_reg = (DPD_CTRL2_AMP_CHK ); - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg);//0x21 - printf("phase4 end set Reg0x21=0x%x\n", dpd_ctl2_reg); - - g_query_operate=0; - psys->dpd_phase=5; - sec_cnt = 0; - phase_in_flag = 1; - dpd_log_string_save( "phase 4.(AUTO) Will enter phase 5"); - } - } - } - - break; - case 5: - ////////////////// 5.POLY update - // in - psys->dpd_phase=5; - if(phase_in_flag) { - phase_in_flag = 0; - - dpd_ctl2_reg = (DPD_CTRL2_NONLIN_UPDATE | DPD_CTRL2_SET_NONLIN_UDP_MOD(1) | DPD_CTRL2_AMP_CHK); // - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); - - dpd_ctl3_reg = ((DPD_CTRL3_DAGC_UPDATE|DPD_CTRL3_DAGC_SLOWDN) | (DPD_CTRL3_DCRM_UPDATE)); - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); - log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 5: in\n"); - } - - dpd_log_read_and_save( psys->dpd_phase); - - // out - if(sec_cnt >= 90 || g_query_skip == E_QUERY_SKIP) { - - if(g_query_skip == E_QUERY_SKIP) { - g_query_skip = E_QUERY; - sec_cnt = 0xffff; - } - - if(atsc_para.dpd_para.dpd_mode == E_DPD_MODE_MANUAL) {//MANUAL - if(g_query_operate==0) - g_query_operate = E_QUERY; - if(g_query_operate == E_QUERY_UP_STOP) { - g_query_operate = 0; - sec_cnt = 0; - psys->adpc_step = 3; - atsc_para.system_para.adpc = ADPC_OFF; - c256_bytewrite(EEPROM_DPD_ADDR,ADPC_OFF); - dpd_log_string_save( "phase 5.MANUAL E_QUERY_SKIP. Will DPD_SUCCESS"); - goto DPD_SUCCESS; - } - else if(g_query_operate==E_QUERY_OK_CONTINUE) - { - g_query_operate=0; - psys->dpd_phase=6; - sec_cnt = 0; - phase_in_flag = 1; - dpd_log_string_save( "phase 5. MANUAL E_QUERY_OK_CONTINUE. Will enter phase 6"); - } - else if(g_query_operate==E_QUERY_ESC_EXIT) - { - g_query_operate=0; - sec_cnt = 0; - phase_in_flag = 1; - psys->adpc_err=DPD_PROC_EXIT; - dpd_log_string_save( "phase 5. MANUAL E_QUERY_ESC_EXIT. Will DPD_END"); - goto DPD_END; - } - - } - else{//AUTO - - g_query_operate=0; - psys->dpd_phase=6; - sec_cnt = 0; - phase_in_flag = 1; - dpd_log_string_save( "phase 5. auto, Will enter phase 6"); - - } - } - break; - case 6: - //check wpp then skip to next - if(g_prompt_skip_wpp==1) { - s_ms200_cnt++; - if(s_ms200_cnt >= 5) { - s_ms200_cnt = 0; - if(g_skip_next_dly) - g_skip_next_dly--; - } - - if(g_skip_next_dly) { - break; - } - else{ - if(atsc_para.wj_para.ctl_dpd==E_DPD_NSAVE_NFLITER)//no save - { - g_prompt_skip_wpp=0; - g_query_save_flg = PHASE6_SET_SAVE; - g_query_save = E_QUERY_CANCEL; - log_printf(LOG_DEBUG, I_USER_CFG, "sta-6.wpp no save, no fliter\n"); - dpd_log_string_save( "phase 6.Checked WPP ,exit and no save"); - goto DPD_SAVE_PROC; - } - else if(atsc_para.wj_para.ctl_dpd==E_DPD_SAVE_NFLITER) - { - g_prompt_skip_wpp=0; - g_query_save_flg = PHASE6_SET_SAVE; - g_query_save = E_QUERY_CONFIRM; - log_printf(LOG_DEBUG, I_USER_CFG, "sta-6.wpp save, no fliter\n"); - dpd_log_string_save( "phase 6.Checked WPP ,exit and save"); - goto DPD_SAVE_PROC; - } - else if(atsc_para.wj_para.ctl_dpd==E_DPD_NSAVE_FLITER ||atsc_para.wj_para.ctl_dpd==E_DPD_SAVE_FLITER){ - g_prompt_skip_wpp=0; - // 4.skip to phase 7 - g_skip_next_dly=0; - g_query_operate=0; - psys->dpd_phase=7; - sec_cnt = 0; - phase_in_flag = 1; - log_printf(LOG_DEBUG, I_USER_CFG, "sta-6.wpp save, fliter\n"); - dpd_log_string_save( "phase 6.Checked WPP AUTO E_QUERY_RF_FLITER. Will enter phase 7"); - goto DPD_SAVE_PROC; - } - - log_printf(LOG_DEBUG, I_USER_CFG, "sta-6. out ctrl\n"); - g_prompt_skip_wpp=0; - } - } - - ////////////////// 6.CRST update - // in - psys->dpd_phase = 6; - if(phase_in_flag) { - phase_in_flag = 0; - dpd_ctl2_reg = (DPD_CTRL2_NONLIN_UPDATE | DPD_CTRL2_SET_NONLIN_UDP_MOD(3) | DPD_CTRL2_AMP_CHK ); - fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); - - dpd_ctl3_reg = DPD_CTRL3_DAGC_UPDATE | DPD_CTRL3_DAGC_SLOWDN | DPD_CTRL3_DCRM_UPDATE; - fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); - - fpga_byte_write(0x05, FPGA_ADDR_DPD_CFG_STEP, 0); - fpga_byte_write(0x05, 0x25, 0xff); - - fpga_byte_write(0x05, 0x26, 0); - log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 6: in, will do %d mins dpd_mode=%d,ctl_dpd=0x%02X\n", - atsc_para.dpd_para.phase6_minute, - atsc_para.dpd_para.dpd_mode, - atsc_para.wj_para.ctl_dpd); - } - - if(sec_cnt == 31) { - fpga_byte_write(0x05, FPGA_ADDR_DPD_CFG_STEP, 1); - fpga_byte_write(0x05, 0x25, 0xff); - fpga_byte_write(0x05, 0x26, 0); - } - dpd_log_read_and_save( psys->dpd_phase); - - - // out - if((sec_cnt >= atsc_para.dpd_para.phase6_minute*60) || (g_query_skip == E_QUERY_SKIP)) { - #if USE_PHASE_78910 - if(g_query_skip == E_QUERY_SKIP) { - g_query_skip = E_QUERY; - sec_cnt = 0xffff; - log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 6: out, g_query_skip = E_QUERY_SKIP\n"); - } - - if(atsc_para.dpd_para.dpd_mode==E_DPD_MODE_MANUAL) {//MANUAL - log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 6: out, dpd_mode = E_DPD_MODE_MANUAL,g_query_operate=%d\n",g_query_operate); - - if(g_query_operate==0) - g_query_operate=E_QUERY; - - if(g_query_operate == E_QUERY_UP_STOP) { - g_query_operate = 0; - sec_cnt = 0; - psys->adpc_step = 3; - atsc_para.system_para.adpc = ADPC_OFF; - c256_bytewrite(EEPROM_DPD_ADDR,ADPC_OFF); - dpd_log_string_save( "phase 6.MANUAL E_QUERY_SKIP. Will DPD_SUCCESS"); - log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase6: MANUAL E_QUERY_SKIP. Will DPD_SUCCESS\n"); - goto DPD_SUCCESS; - } - else if(g_query_operate==E_QUERY_OK_CONTINUE) - { - g_query_operate=0; - psys->dpd_phase=7; - sec_cnt = 0; - phase_in_flag = 1; - dpd_log_string_save( "phase 6.MANUAL E_QUERY_OK_CONTINUE. Will enter phase 7"); - } - else if(g_query_operate==E_QUERY_ESC_EXIT) - { - g_query_operate=0; - sec_cnt = 0; - phase_in_flag = 1; - psys->adpc_err=DPD_PROC_EXIT; - dpd_log_string_save( "phase 6.MANUAL E_QUERY_ESC_EXIT. Will DPD_END"); - goto DPD_END; - } - - } - else{//AUTO - - #if USE_REMOTE_DPD - //for udp - if(adpc_source_udp){ - adpc_source_udp = 0; - g_query_save_flg= 0; - g_query_save = 0; - psys->adpc_step = 3; - atsc_para.system_para.adpc = ADPC_HOLD;//断电失效 - c256_bytewrite(EEPROM_DPD_ADDR,ADPC_OFF); - dpd_log_string_save( " adpc_source_udp = 1. set STEP = 3., Will DPD_END"); - log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 6: adpc_source_udp = 1. set STEP = 3., Will DPD_END\n"); - goto DPD_END; - } - //for web and uart - if(adpc_source_web){ - g_query_operate = E_QUERY_RF_FLITER; - log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 6:---- E_QUERY_RF_FLITER\n"); - } - #endif - - //normal-exe - if(atsc_para.wj_para.ctl_dpd==E_DPD_NSAVE_NFLITER) - { - g_query_save_flg = PHASE6_SET_SAVE; - g_query_save = E_QUERY_CANCEL; - log_printf(LOG_DEBUG, I_USER_CFG, "sta-6.normal no save, no fliter\n"); - } - else if(atsc_para.wj_para.ctl_dpd==E_DPD_SAVE_NFLITER) - { - g_query_save_flg = PHASE6_SET_SAVE; - g_query_save = E_QUERY_CONFIRM; - log_printf(LOG_DEBUG, I_USER_CFG, "sta-6.normal save, no fliter\n"); - } - else if(atsc_para.wj_para.ctl_dpd==E_DPD_NSAVE_FLITER||atsc_para.wj_para.ctl_dpd==E_DPD_SAVE_FLITER) - { - if(psys->adpc==ADPC_UPDATE3) { - g_query_operate=0; - //psys->dpd_phase=0; - sec_cnt = 0xFFFF; - phase_in_flag = 0; - g_query_save = E_QUERY_CONFIRM; - g_query_save_flg = PHASE6_SET_SAVE; - log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase6: done, will save data..........\n"); - dpd_log_string_save( "phase 6.AUTO E_QUERY_RF_FLITER. Will enter save data"); - goto DPD_SAVE_PROC; - - } else { - - g_query_operate=0; - psys->dpd_phase=7; - sec_cnt = 0; - phase_in_flag = 1; - log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 7:------Will enter phase 7 \n"); - - if(atsc_para.wj_para.ctl_dpd==E_DPD_SAVE_FLITER) - log_printf(LOG_DEBUG, I_USER_CFG, "sta-6.normal save, fliter\n"); - else if(atsc_para.wj_para.ctl_dpd==E_DPD_NSAVE_FLITER) - log_printf(LOG_DEBUG, I_USER_CFG, "sta-6.normal no save, fliter\n"); - dpd_log_string_save( "phase 6.AUTO E_QUERY_RF_FLITER. Will enter phase 7"); - } - } - else{ - - if(g_query_operate == 0){//query fliter - g_query_operate = E_QUERY2; - log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase6: E_QUERY2\n"); - } - else if(g_query_operate == E_QUERY_ESC_SAVE) {//query save - g_query_save_flg = PHASE6_SET_SAVE;// p6 - log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase6: E_QUERY_ESC_SAVE PHASE6_SET_SAVE\n"); - dpd_log_string_save( "phase 6.AUTO E_QUERY_ESC_SAVE ,PHASE6_SET_SAVE "); - } - else if(g_query_operate==E_QUERY_RF_FLITER) { - if(psys->adpc==ADPC_UPDATE3) { - g_query_operate=0; - psys->dpd_phase=0; - sec_cnt = 0; - phase_in_flag = 0; - g_query_save =E_QUERY_CONFIRM; - g_query_save_flg = PHASE6_SET_SAVE; - log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase6: done, will save data.\n"); - dpd_log_string_save( "phase 6.AUTO E_QUERY_RF_FLITER. Will enter save data"); - goto DPD_SAVE_PROC; - - }else{ - g_query_operate=0; - psys->dpd_phase=7; - sec_cnt = 0; - phase_in_flag = 1; - log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase6: AUTO E_QUERY_RF_FLITER. Will enter phase 7\n"); - dpd_log_string_save( "phase 6.AUTO E_QUERY_RF_FLITER. Will enter phase 7"); - } - - } - } - - } - #endif - } - - break; - - - case 7: - ////////////// 7-2-AGC - // in - psys->dpd_phase=7; - if(phase_in_flag) //进入phase时执行一次的初始化操作 - { - dpd_log_string_save( "phase 7. in :"); - dpd_log_read_and_save( psys->dpd_phase); - phase_in_flag = 0; - dpd_log_string_save( "dpd rf sel: after"); - - dpd_ctl2_reg = 0; - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); - - dpd_ctl3_reg = (DPD_CTRL3_SYNC_RESTART | DPD_CTRL3_FAGC_UPDATE | DPD_CTRL3_DAGC_UPDATE | DPD_CTRL3_DCRM_UPDATE ); - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); - - u_dpdctl_r23.dpd_bt.iqb_upd =0; - u_dpdctl_r23.dpd_bt.sync_mode=1; - u_dpdctl_r23.dpd_bt.rf_sel =0; - fpga_byte_write(5,FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); - log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 7: 0x%x\n", u_dpdctl_r23.u8val); - - s_fagc_locked = 0; - } - - // 前半段跑完, 锁死射频AGC, 后半段只留数字AGC收敛(见 FAGC_LOCK_SEC 注释) - if(!s_fagc_locked && sec_cnt >= FAGC_LOCK_SEC) - { - s_fagc_locked = 1; - // 只清 FAGC_UPDATE(bit0), SYNC_RESTART 必须继续保持到相8才放开 - dpd_ctl3_reg = (DPD_CTRL3_SYNC_RESTART | DPD_CTRL3_DAGC_UPDATE | DPD_CTRL3_DCRM_UPDATE); - fpga_byte_write(5, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); - log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 7: FAGC locked at %ds, CTRL3=0x%02x\n", - sec_cnt, dpd_ctl3_reg); - dpd_log_string_save("phase 7. FAGC locked, DAGC only"); - } - - dpd_log_read_and_save( psys->dpd_phase); - - // out - if(sec_cnt >= 20 || g_query_skip == E_QUERY_SKIP){ // 计时超过20秒离开phase7 - if(g_query_skip == E_QUERY_SKIP) - g_query_skip=E_QUERY; - - g_pow_state_check = 1; - psys->dpd_phase=8; // 离开前进行的操作 - sec_cnt = 0; - phase_in_flag = 1; - dpd_log_string_save("phase 7. E_QUERY_SKIP will enter phase 8"); - } - break; - - case 8: - ////////////// 8-3-TX RX SYNC - // in - - psys->dpd_phase=8; - if(phase_in_flag) //进入phase时执行一次的初始化操作 - { - dpd_log_string_save( "phase 8. in :"); - dpd_log_read_and_save( psys->dpd_phase); - phase_in_flag = 0; - dpd_ctl2_reg = 0; - dpd_ctl3_reg = (DPD_CTRL3_SYNC_UPDATE | DPD_CTRL3_DCRM_UPDATE); - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); - } - dpd_log_read_and_save( psys->dpd_phase); - //out - if(rd_reg & MASK_DPD_TRX_SYNC_OK || g_query_skip == E_QUERY_SKIP) // 读取到dpd_trx_sync_ok状态为1时进入下一阶段 - { - if(g_query_skip == E_QUERY_SKIP) - g_query_skip = E_QUERY; - - // set fix delay - psys->dpd_phase=9; - sec_cnt = 0; - phase_in_flag = 1; - dpd_log_string_save( "Phase 8. out , Will enter phase 9"); - } - else if(sec_cnt >= 80)// 超过80秒未读到sync ok， 同步失败，退出校正 - { - log_printf(LOG_DEBUG, I_USER_CFG, "[update] TX RX sync failed\r\n"); - dpd_log_string_save( "Phase 8. TX RX sync failed, Will DPD_END"); - psys->adpc_err = DPD_SYNC_TIMEOUT; - goto DPD_END; - } - break; - - case 9: - ////////////// 9-4-ROT - // in - psys->dpd_phase=9; - if(phase_in_flag) { - dpd_log_string_save( "phase 9. in :"); - dpd_log_read_and_save( psys->dpd_phase); - phase_in_flag = 0; - dpd_ctl2_reg = 0; - - - dpd_ctl3_reg = ((DPD_CTRL3_DAGC_UPDATE|DPD_CTRL3_DAGC_SLOWDN) | (DPD_CTRL3_ROT_UPDATE)); - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); - - u_dpdctl_r23.dpd_bt.iqb_upd =1; - log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 9 --- 0x%x\n", u_dpdctl_r23.u8val); - fpga_byte_write(5,FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); - } - - dpd_log_read_and_save( psys->dpd_phase); - - // out - if(sec_cnt >= 30 || g_query_skip == E_QUERY_SKIP) // 计时到15秒进入下一阶段 - { - if(g_query_skip == E_QUERY_SKIP){g_query_skip=E_QUERY;sec_cnt=15;} - if(atsc_para.dpd_para.dpd_mode==E_DPD_MODE_MANUAL) - {//MANUAL - if(g_query_operate==0)g_query_operate=E_QUERY; - if(g_query_operate == E_QUERY_UP_STOP) - { - g_query_operate = 0; - sec_cnt = 0; - psys->adpc_step = 3; - atsc_para.system_para.adpc = ADPC_OFF; - c256_bytewrite(EEPROM_DPD_ADDR,ADPC_OFF); - dpd_log_string_save( "Phase 9. MANUAL E_QUERY_SKIP, Will DPD_SUCCESS"); - goto DPD_SUCCESS; - } - else if(g_query_operate==E_QUERY_OK_CONTINUE) - { - g_query_operate=0; - psys->dpd_phase=10; - sec_cnt = 0; - phase_in_flag = 1; - dpd_log_string_save( "Phase 9.MANUAL E_QUERY_OK_CONTINUE, Will enter phase 10"); - } - else if(g_query_operate==E_QUERY_ESC_EXIT) - { - g_query_operate=0; - sec_cnt = 0; - phase_in_flag = 1; - psys->adpc_err=DPD_PROC_EXIT; - dpd_log_string_save( "Phase 9.MANUAL E_QUERY_ESC_EXIT, Will DPD_END"); - goto DPD_END; - } - - } - else{//AUTO - g_query_operate=0; - psys->dpd_phase=10; - sec_cnt = 0; - phase_in_flag = 1; - dpd_log_string_save( "Phase 9.auto Will enter phase 10"); - } - } - break; - case 10: - ////////////// 10-4-Linear update - // in - psys->dpd_phase = 10; - if(phase_in_flag) { - log_printf(LOG_DEBUG, I_USER_CFG, "ph10_time = %d min\n",atsc_para.wj_para.ph10_time); - dpd_log_string_save( "Phase 10 in"); - dpd_log_read_and_save( psys->dpd_phase); - - fpga_byte_write(5,FPGA_ADDR_DPD_CFG_STEP, 0); - fpga_byte_write(5,0x25, 0xff); - fpga_byte_write(5,0x26, 0x04); - - phase_in_flag = 0; - dpd_ctl2_reg = (DPD_CTRL2_PRL_UPDATE|DPD_CTRL2_AMP_CHK); - dpd_ctl3_reg = 0; // oneshu remove dags - - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); - - u_dpdctl_r23.dpd_bt.iqb_upd = 0; - fpga_byte_write(5,FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); - log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 10 --- 0x%x\n", u_dpdctl_r23.u8val); - } - dpd_log_read_and_save( psys->dpd_phase); - // out - if(sec_cnt >= atsc_para.wj_para.ph10_time*60 || g_query_skip == E_QUERY_SKIP) // 300 - { - //note web set first - if(atsc_para.wj_para.ctl_dpd==E_DPD_SAVE_FLITER){ - g_query_save =E_QUERY_CONFIRM; - log_printf(LOG_DEBUG, I_USER_CFG, "sta-10.save, fliter\n"); - } - else if(atsc_para.wj_para.ctl_dpd==E_DPD_NSAVE_FLITER){ - g_query_save =E_QUERY_CANCEL; - log_printf(LOG_DEBUG, I_USER_CFG, "sta-10.no save, no fliter\n"); - } - else{ - g_query_save =E_QUERY_CANCEL; - } - - #if USE_REMOTE_DPD - //for web and uart - if(adpc_source_web){ - adpc_source_web = 0; - g_query_save =E_QUERY_CONFIRM; - } - #endif - - if(g_query_skip == E_QUERY_SKIP) { - g_query_skip=E_QUERY; - sec_cnt=0xffff; - } - //printf("\r\n step finished, finish the dpd process? >> "); - - g_query_save_flg = PHASE10_SET_SAVE;// p10 - dpd_log_string_save( "Phase 10 out, PHASE10_SET_SAVE"); - - - } - break; - default: - break; - } - - -#if 1 -DPD_SAVE_PROC: - if(g_query_save_flg != 0) { - /*if(g_query_save == 0) - g_query_save = E_QUERY;*/ - - if(g_query_save==E_QUERY_CONFIRM) { - if(g_query_save_flg == PHASE6_SET_SAVE) - g_query_operate = 0; - - g_query_save_flg = 0; - g_query_save = 0; - //初始化配置，所有的 “控制”寄存器全部置0, 在ctrl123均配置0时,顺序应为2 1 3. - fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL2, 0); - fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL1, 0); - fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, 0); - - u_dpdctl_r23.u8val = 0; - fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); - log_printf(LOG_DEBUG, I_USER_CFG, "[update] save data --- 0x%x\n", u_dpdctl_r23.u8val); - - - fpga_byte_write(0x05, FPGA_ADDR_WPP_EN_CLR, 0); - fpga_byte_write(0x05, FPGA_ADDR_WPP_EN_CLR, MASK_WPP_CLR); - fpga_byte_write(0x05, FPGA_ADDR_WPP_EN_CLR, 0); - - dpd_curve_proc(E_LOAD_TO_MCU); - if(dpd_ck_status==CK_OK){ - psys->adpc_step = 3; - atsc_para.system_para.adpc = ADPC_HOLD;//断电保持 - c256_bytewrite(EEPROM_DPD_ADDR, ADPC_HOLD); - c256_bytewrite(EEPROM_DPD_FLASH_VALID, 1); - log_printf(LOG_DEBUG, I_USER_CFG, "dpd load to mcu ok\n"); - dpd_log_string_save("g_query_save E_QUERY_CONFIRM CK_OK, will DPD_SUCCESS"); - goto DPD_SUCCESS; - } - else{ - atsc_para.system_para.adpc = ADPC_OFF; - c256_bytewrite(EEPROM_DPD_ADDR, ADPC_OFF); - psys->adpc_err = DPD_READ_CKECK_ERR; - log_printf(LOG_DEBUG, I_USER_CFG, "dpd load to mcu err\n"); - dpd_log_string_save("g_query_save E_QUERY_CONFIRM !CK_OK, will DPD_END"); - goto DPD_END; - } - } - else if(g_query_save==E_QUERY_CANCEL) - { - if(g_query_save_flg==PHASE6_SET_SAVE) - g_query_operate=0; - - g_query_save_flg=0; - g_query_save=0; - psys->adpc_step = 3; - atsc_para.system_para.adpc = ADPC_HOLD;//断电失效 - c256_bytewrite(EEPROM_DPD_ADDR,ADPC_OFF); - dpd_log_string_save("g_query_save E_QUERY_CANCEL , will DPD_SUCCESS"); - goto DPD_SUCCESS; - } - } -#endif - - + + tx_pow = (fpga_byte_read(0x05,0x03)<<8)|fpga_byte_read(0x05,0x02); + err_pow = (fpga_byte_read(0x05,0x05)<<8)|fpga_byte_read(0x05,0x04); + + f_tsnr = 10*log10(tx_pow*64.0/err_pow)*100+TSNR_FIX;//放大100 + if(f_tsnr < 0) + f_tsnr = 0; + + u16_tsnr = (uint16)f_tsnr; + + (void)check_lcd_light(TYPE_KEY); //确保屏幕不灭 + + if(st_check_wpp_en==1){ + wpp_abort = fpga_byte_read(0x05,0x0d); + } + wpp_max = (fpga_byte_read(0x05,0x0f)<<8)|fpga_byte_read(0x05,0x0e); + + #if 1 + if(wpp_abort&0x01){//dpd由于脉冲功率过大导致保护 @20210907调整为出现该保护，提示结束及保持曲线确认 + + // 0. if checked wpp at phase 6, then clr wpp status and disable wpp check, auto skip to phase 7 + if(psys->dpd_phase==6) + { + if(atsc_para.wj_para.ctl_dpd==E_DPD_NSAVE_FLITER ||atsc_para.wj_para.ctl_dpd==E_DPD_SAVE_FLITER){ + // 1.clr wpp status + wpp_max = (fpga_byte_read(0x05,0x0f)<<8)|fpga_byte_read(0x05,0x0e); + log_printf(LOG_DEBUG, I_USER_CFG, "ph6 before clr maxwpp=%d,wppabort=%d\n",wpp_max,wpp_abort&0x01); + g_wpp_max = wpp_max; + + fpga_byte_write(5,FPGA_ADDR_WPP_EN_CLR, 0); + fpga_byte_write(5,FPGA_ADDR_WPP_EN_CLR, MASK_WPP_CLR); + fpga_byte_write(5,FPGA_ADDR_WPP_EN_CLR, MASK_WPP_ENABLE); + + wpp_max = (fpga_byte_read(0x05,0x0f)<<8)|fpga_byte_read(0x05,0x0e); + log_printf(LOG_DEBUG, I_USER_CFG, "ph6 after clr maxwpp=%d,wppabort=%d\n",wpp_max,wpp_abort&0x01); + + g_query_wpp_to_save=0; + + // 2.disable wpp check + st_check_wpp_en = 0; + + // 3.prompt skip to next + g_prompt_skip_wpp=1; + log_printf(LOG_DEBUG, I_USER_CFG, "sta-%d wpp to next\n",psys->dpd_phase); + } + else{ + // 3.prompt err + g_wpp_max = wpp_max; + g_prompt_skip_wpp=1; + } + } + else{ + + g_wpp_max = wpp_max; + psys->adpc_err=DPD_CHECK_WPP_ERR_EXIT_HOLD;//DPD_CHECK_WPP_ERR_EXIT + log_printf(LOG_DEBUG, I_USER_CFG, "sta-%d esc wpp maxwpp=%d,wppabort=%d\n",psys->dpd_phase,wpp_max,wpp_abort&0x01); + + goto DPD_END;//DPD_SAVE_PROC; + } + + } + #endif + + /* 读取状态 >>>> *///------------------------------------- + rd_reg = fpga_byte_read(5,FPGA_ADDR_DPD_STATUS1); + + if(rd_reg & MASK_DPD_SAT_FLG){ + dpd_sat_flg = 1;//只做显示 + } + else{ + dpd_sat_flg = 0; + } + if(rd_reg & MASK_DPD_ERR)//bit-0 //出现 DPD error状态 + { + psys->adpc_err = DPD_STATE_ERR; + log_printf(LOG_DEBUG, I_USER_CFG, "\b DPD caused tx power rise too much\r\n"); + dpd_log_string_save("Step 2. DPD caused tx power rise too much. Will DPD_END"); + goto DPD_END; + } + + if(rd_reg & MASK_DPD_ERR_ABORT)//bit-3 //出现 adpc_err_aborto 状态 + { + psys->adpc_err = DPD_STATE_ERR_OVER_RANGE; + log_printf(LOG_DEBUG, I_USER_CFG, "\b DPD Abort due to large errors\r\n"); + dpd_log_string_save( "Step 2. DPD Abort due to large errors. Will DPD_END"); + goto DPD_END; + } + + if(g_pow_state_check) + { + if(rd_reg & MASK_DPD_PWRLOW)//bit-2 //出现 dpd_powerislow状态 + { + psys->adpc_err = DPD_STATE_POWER_LOW; + log_printf(LOG_DEBUG, I_USER_CFG, "\b Feedback power is low\r\n"); + dpd_log_string_save( "Step 2. Feedback power is low. Will DPD_END"); + goto DPD_END; + } + if(rd_reg & MASK_DPD_PWRHIGH)//bit-1 //出现 dpd_powerishigh状态 + { + psys->adpc_err = DPD_STATE_POWER_HIGH; + log_printf(LOG_DEBUG, I_USER_CFG, "\b Feedback power is high\r\n"); + dpd_log_string_save( "Step 2. Feedback power is high. Will DPD_END"); + goto DPD_END; + } + } + + if(psys->dpd_phase>1){ // 过了phase1以后才检测的状态 + if(rd_reg & MASK_DPD_DAGC_TOOLOW) //bit-6 + { + psys->adpc_err = DPD_STATE_POWER_TOO_LOW; + log_printf(LOG_DEBUG, I_USER_CFG, "\b DPD Abort due to DAGC input LOW\r\n"); + dpd_log_string_save( "Step 2. DPD Abort due to DAGC input LOW. Will DPD_END"); + goto DPD_END; + } + + if(rd_reg & MASK_DPD_DAGC_TOOHIGH)//bit-5 + { + psys->adpc_err = DPD_STATE_POWER_TOO_HIGH; + log_printf(LOG_DEBUG, I_USER_CFG, "\b DPD Abort due to DAGC input HIGH\r\n"); + dpd_log_string_save( "Step 2. DPD Abort due to DAGC input HIGH. Will DPD_END"); + goto DPD_END; + } + } + + /* 读取状态 <<<< *///------------------------------------- + + + + + //校正过程 + switch(psys->dpd_phase) // 各个phase（阶段）需要进行的处理 + { + case 1: + ////////////// 1.AGC + // in + psys->dpd_phase=1; + if(phase_in_flag) //进入phase时执行一次的初始化操作 + { + phase_in_flag = 0; + + dpd_ctl2_reg = 0; + dpd_ctl3_reg = (DPD_CTRL3_SYNC_RESTART | DPD_CTRL3_FAGC_UPDATE | DPD_CTRL3_DAGC_UPDATE | DPD_CTRL3_DCRM_UPDATE ); // + fpga_byte_write(0x05,FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); + fpga_byte_write(0x05,FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); + + fpga_byte_write(0x05, FPGA_ADDR_WPP_EN_CLR, 0); // 关闭WPP保护 + fpga_byte_write(0x05, FPGA_ADDR_WPP_EN_CLR, MASK_WPP_CLR); // 清除MAXP + fpga_byte_write(0x05, FPGA_ADDR_WPP_EN_CLR, MASK_WPP_ENABLE); //打开WPP保护 + + u_dpdctl_r23.u8val = 0; + u_dpdctl_r23.dpd_bt.iqb_upd = 1; + u_dpdctl_r23.dpd_bt.sync_mode = 0; + u_dpdctl_r23.dpd_bt.rf_sel = DPD_RF_SEL_VALUE(E_SELECT_B); + fpga_byte_write(5,FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); + log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 1: 0x%x\n", u_dpdctl_r23.u8val); + + s_fagc_locked = 0; + } + + // 前半段跑完, 锁死射频AGC, 后半段只留数字AGC收敛(见 FAGC_LOCK_SEC 注释) + if(!s_fagc_locked && sec_cnt >= FAGC_LOCK_SEC) + { + s_fagc_locked = 1; + // 只清 FAGC_UPDATE(bit0), SYNC_RESTART 必须继续保持到相2才放开 + dpd_ctl3_reg = (DPD_CTRL3_SYNC_RESTART | DPD_CTRL3_DAGC_UPDATE | DPD_CTRL3_DCRM_UPDATE); + fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); + log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 1: FAGC locked at %ds, CTRL3=0x%02x\n", + sec_cnt, dpd_ctl3_reg); + dpd_log_string_save("phase 1. FAGC locked, DAGC only"); + } + + // Keep the same raw FPGA signal trace used by phases 3-10 so + // the FAGC-to-DAGC handover can be analysed end-to-end. + dpd_log_read_and_save(psys->dpd_phase); + + // out + if(sec_cnt >= 20 || g_query_skip == E_QUERY_SKIP){ // 计时超过20秒离开phase1 + g_pow_state_check = 1; + + if(g_query_skip == E_QUERY_SKIP)g_query_skip=E_QUERY; + psys->dpd_phase=2; // 离开前进行的操作 + sec_cnt = 0; + phase_in_flag = 1; + } + break; + + case 2: + ////////////// 2.TX RX SYNC + // in + psys->dpd_phase=2; + if(phase_in_flag) //进入phase时执行一次的初始化操作 + { + phase_in_flag = 0; + dpd_ctl2_reg = 0; + dpd_ctl3_reg = (DPD_CTRL3_SYNC_UPDATE | DPD_CTRL3_DCRM_UPDATE); + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); + } + + // Phase 2 can be short when TX/RX sync is already locked, so + // sample on every state-machine pass instead of entry only. + dpd_log_read_and_save(psys->dpd_phase); + + //out + if(rd_reg & MASK_DPD_TRX_SYNC_OK || g_query_skip == E_QUERY_SKIP) // 读取到dpd_trx_sync_ok状态为1时进入下一阶段 + { + if(g_query_skip == E_QUERY_SKIP)g_query_skip=E_QUERY; + + // set fix delay + psys->dpd_phase=3; + sec_cnt = 0; + phase_in_flag = 1; + } + else if(sec_cnt >= 80)// 超过80秒为读到sync ok， 同步失败，退出校正 + { + log_printf(LOG_DEBUG, I_USER_CFG, "\b TX RX sync failed\r\n"); + psys->adpc_err = DPD_SYNC_TIMEOUT; + goto DPD_END; + } + break; + + + case 3: + ////////////// 3.ROT + // in + psys->dpd_phase=3; + if(phase_in_flag) + { + phase_in_flag = 0; + dpd_ctl2_reg = 0; + //dpd_ctl3_reg = DPD_CTRL3_ROT_UPDATE; + dpd_ctl3_reg = DPD_CTRL3_DAGC_UPDATE|DPD_CTRL3_DAGC_SLOWDN|DPD_CTRL3_ROT_UPDATE; + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); + } + dpd_log_read_and_save( psys->dpd_phase); + // out + if(sec_cnt >= 30 || g_query_skip == E_QUERY_SKIP) // 计时到15秒进入下一阶段 + { + if(g_query_skip == E_QUERY_SKIP) { + g_query_skip = E_QUERY; + sec_cnt=0xffff; + } + dpd_log_read_and_save( psys->dpd_phase); + if(atsc_para.dpd_para.dpd_mode==E_DPD_MODE_MANUAL) {//MANUAL + if(g_query_operate==0) + g_query_operate = E_QUERY; + if(g_query_operate == E_QUERY_UP_STOP) { + g_query_operate = 0; + sec_cnt = 0; + psys->adpc_step = 3; + atsc_para.system_para.adpc = ADPC_OFF; + c256_bytewrite(EEPROM_DPD_ADDR,ADPC_OFF); + dpd_log_string_save( "phase 3. MANUAL E_QUERY_SKIP. Will DPD_SUCCESS"); + goto DPD_SUCCESS; + } + else if(g_query_operate==E_QUERY_OK_CONTINUE) { + g_query_operate=0; + psys->dpd_phase=4; + sec_cnt = 0; + phase_in_flag = 1; + dpd_log_string_save("phase 3. MANUAL E_QUERY_OK_CONTINUE. Will enter phase 4"); + } + else if(g_query_operate==E_QUERY_ESC_EXIT) { + g_query_operate=0; + sec_cnt = 0; + phase_in_flag = 1; + psys->adpc_err=DPD_PROC_EXIT; + dpd_log_string_save("phase 3. MANUAL E_QUERY_ESC_EXIT. Will DPD_END"); + goto DPD_END; + } + + } + else{//AUTO + dpd_log_read_and_save( psys->dpd_phase); + g_query_operate=0; + psys->dpd_phase=4; + sec_cnt = 0; + phase_in_flag = 1; + dpd_log_string_save("phase 3. AUTO. Will enter phase 4"); + } + } + break; + + case 4: + ////////////// 4.Linear update + // in + psys->dpd_phase = 4; + if(phase_in_flag) + { + stc_insert_step = 0; + phase_in_flag = 0; + dpd_ctl2_reg = (DPD_CTRL2_LIN_UPDATE | DPD_CTRL2_AMP_CHK ); + + fpga_byte_write(5,0x25, 0xff); + fpga_byte_write(5,0x26, 0x08); + + u_dpdctl_r23.dpd_bt.iqb_upd = 0; + fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); + log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 4: 0x%x\n", u_dpdctl_r23.u8val); + + log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 4 0x26-0x08\n"); + dpd_log_string_save("phase 4 0x26-0x08"); + + dpd_ctl3_reg = (DPD_CTRL3_DAGC_UPDATE|DPD_CTRL3_DAGC_SLOWDN); + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); + } + dpd_log_read_and_save(psys->dpd_phase); + // out + if(sec_cnt >= 90 || g_query_skip == E_QUERY_SKIP) { + if(g_query_skip == E_QUERY_SKIP){g_query_skip=E_QUERY;sec_cnt=0xffff;} + + if(atsc_para.dpd_para.dpd_mode == E_DPD_MODE_MANUAL) + {//MANUAL + if(g_query_operate == 0) + g_query_operate = E_QUERY; + + if(g_query_operate == E_QUERY_UP_STOP) { + g_query_operate = 0; + sec_cnt = 0; + psys->adpc_step = 3; + atsc_para.system_para.adpc = ADPC_OFF; + c256_bytewrite(EEPROM_DPD_ADDR,ADPC_OFF); + dpd_log_string_save( "phase 4.(MANUAL) E_QUERY_SKIP. Will DPD_SUCCESS"); + goto DPD_SUCCESS; + } + else if(g_query_operate==E_QUERY_OK_CONTINUE) + { + g_query_operate=0; + psys->dpd_phase=5; + sec_cnt = 0; + phase_in_flag = 1; + dpd_log_string_save( "phase 4.(MANUAL) E_QUERY_OK_CONTINUE. Will enter phase 5"); + } + else if(g_query_operate==E_QUERY_ESC_EXIT) + { + g_query_operate=0; + sec_cnt = 0; + phase_in_flag = 1; + psys->adpc_err=DPD_PROC_EXIT; + dpd_log_string_save( "phase 4.(MANUAL) E_QUERY_ESC_EXIT. Will DPD_END"); + goto DPD_END; + } + + } + else{//AUTO + if(stc_insert_step==0){ + stc_insert_step = 1; + + //1. 在4结束后，lin_update_set = 0, 同时把0x21的bit7 设置为1。其它都不动； + dpd_ctl2_reg = (DPD_CTRL2_AMP_CHK | DPD_CTRL2_POLYESTI_UPDATE); + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg);//0x21 + printf("phase4 end-5s set Reg0x21=0x%x\n", dpd_ctl2_reg); + } + + if(sec_cnt >= 90+5){ + + //2. 过个5秒左右，0x21 的bit7 设置为0，然后进入状态5； + dpd_ctl2_reg = (DPD_CTRL2_AMP_CHK ); + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg);//0x21 + printf("phase4 end set Reg0x21=0x%x\n", dpd_ctl2_reg); + + g_query_operate=0; + psys->dpd_phase=5; + sec_cnt = 0; + phase_in_flag = 1; + dpd_log_string_save( "phase 4.(AUTO) Will enter phase 5"); + } + } + } + + break; + case 5: + ////////////////// 5.POLY update + // in + psys->dpd_phase=5; + if(phase_in_flag) { + phase_in_flag = 0; + + dpd_ctl2_reg = (DPD_CTRL2_NONLIN_UPDATE | DPD_CTRL2_SET_NONLIN_UDP_MOD(1) | DPD_CTRL2_AMP_CHK); // + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); + + dpd_ctl3_reg = ((DPD_CTRL3_DAGC_UPDATE|DPD_CTRL3_DAGC_SLOWDN) | (DPD_CTRL3_DCRM_UPDATE)); + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); + log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 5: in\n"); + } + + dpd_log_read_and_save( psys->dpd_phase); + + // out + if(sec_cnt >= 90 || g_query_skip == E_QUERY_SKIP) { + + if(g_query_skip == E_QUERY_SKIP) { + g_query_skip = E_QUERY; + sec_cnt = 0xffff; + } + + if(atsc_para.dpd_para.dpd_mode == E_DPD_MODE_MANUAL) {//MANUAL + if(g_query_operate==0) + g_query_operate = E_QUERY; + if(g_query_operate == E_QUERY_UP_STOP) { + g_query_operate = 0; + sec_cnt = 0; + psys->adpc_step = 3; + atsc_para.system_para.adpc = ADPC_OFF; + c256_bytewrite(EEPROM_DPD_ADDR,ADPC_OFF); + dpd_log_string_save( "phase 5.MANUAL E_QUERY_SKIP. Will DPD_SUCCESS"); + goto DPD_SUCCESS; + } + else if(g_query_operate==E_QUERY_OK_CONTINUE) + { + g_query_operate=0; + psys->dpd_phase=6; + sec_cnt = 0; + phase_in_flag = 1; + dpd_log_string_save( "phase 5. MANUAL E_QUERY_OK_CONTINUE. Will enter phase 6"); + } + else if(g_query_operate==E_QUERY_ESC_EXIT) + { + g_query_operate=0; + sec_cnt = 0; + phase_in_flag = 1; + psys->adpc_err=DPD_PROC_EXIT; + dpd_log_string_save( "phase 5. MANUAL E_QUERY_ESC_EXIT. Will DPD_END"); + goto DPD_END; + } + + } + else{//AUTO + + g_query_operate=0; + psys->dpd_phase=6; + sec_cnt = 0; + phase_in_flag = 1; + dpd_log_string_save( "phase 5. auto, Will enter phase 6"); + + } + } + break; + case 6: + //check wpp then skip to next + if(g_prompt_skip_wpp==1) { + s_ms200_cnt++; + if(s_ms200_cnt >= 5) { + s_ms200_cnt = 0; + if(g_skip_next_dly) + g_skip_next_dly--; + } + + if(g_skip_next_dly) { + break; + } + else{ + if(atsc_para.wj_para.ctl_dpd==E_DPD_NSAVE_NFLITER)//no save + { + g_prompt_skip_wpp=0; + g_query_save_flg = PHASE6_SET_SAVE; + g_query_save = E_QUERY_CANCEL; + log_printf(LOG_DEBUG, I_USER_CFG, "sta-6.wpp no save, no fliter\n"); + dpd_log_string_save( "phase 6.Checked WPP ,exit and no save"); + goto DPD_SAVE_PROC; + } + else if(atsc_para.wj_para.ctl_dpd==E_DPD_SAVE_NFLITER) + { + g_prompt_skip_wpp=0; + g_query_save_flg = PHASE6_SET_SAVE; + g_query_save = E_QUERY_CONFIRM; + log_printf(LOG_DEBUG, I_USER_CFG, "sta-6.wpp save, no fliter\n"); + dpd_log_string_save( "phase 6.Checked WPP ,exit and save"); + goto DPD_SAVE_PROC; + } + else if(atsc_para.wj_para.ctl_dpd==E_DPD_NSAVE_FLITER ||atsc_para.wj_para.ctl_dpd==E_DPD_SAVE_FLITER){ + g_prompt_skip_wpp=0; + // 4.skip to phase 7 + g_skip_next_dly=0; + g_query_operate=0; + psys->dpd_phase=7; + sec_cnt = 0; + phase_in_flag = 1; + log_printf(LOG_DEBUG, I_USER_CFG, "sta-6.wpp save, fliter\n"); + dpd_log_string_save( "phase 6.Checked WPP AUTO E_QUERY_RF_FLITER. Will enter phase 7"); + goto DPD_SAVE_PROC; + } + + log_printf(LOG_DEBUG, I_USER_CFG, "sta-6. out ctrl\n"); + g_prompt_skip_wpp=0; + } + } + + ////////////////// 6.CRST update + // in + psys->dpd_phase = 6; + if(phase_in_flag) { + phase_in_flag = 0; + dpd_ctl2_reg = (DPD_CTRL2_NONLIN_UPDATE | DPD_CTRL2_SET_NONLIN_UDP_MOD(3) | DPD_CTRL2_AMP_CHK ); + fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); + + dpd_ctl3_reg = DPD_CTRL3_DAGC_UPDATE | DPD_CTRL3_DAGC_SLOWDN | DPD_CTRL3_DCRM_UPDATE; + fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); + + fpga_byte_write(0x05, FPGA_ADDR_DPD_CFG_STEP, 0); + fpga_byte_write(0x05, 0x25, 0xff); + + fpga_byte_write(0x05, 0x26, 0); + log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 6: in, will do %d mins dpd_mode=%d,ctl_dpd=0x%02X\n", + atsc_para.dpd_para.phase6_minute, + atsc_para.dpd_para.dpd_mode, + atsc_para.wj_para.ctl_dpd); + } + + if(sec_cnt == 31) { + fpga_byte_write(0x05, FPGA_ADDR_DPD_CFG_STEP, 1); + fpga_byte_write(0x05, 0x25, 0xff); + fpga_byte_write(0x05, 0x26, 0); + } + dpd_log_read_and_save( psys->dpd_phase); + + + // out + if((sec_cnt >= atsc_para.dpd_para.phase6_minute*60) || (g_query_skip == E_QUERY_SKIP)) { + #if USE_PHASE_78910 + if(g_query_skip == E_QUERY_SKIP) { + g_query_skip = E_QUERY; + sec_cnt = 0xffff; + log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 6: out, g_query_skip = E_QUERY_SKIP\n"); + } + + if(atsc_para.dpd_para.dpd_mode==E_DPD_MODE_MANUAL) {//MANUAL + log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 6: out, dpd_mode = E_DPD_MODE_MANUAL,g_query_operate=%d\n",g_query_operate); + + if(g_query_operate==0) + g_query_operate=E_QUERY; + + if(g_query_operate == E_QUERY_UP_STOP) { + g_query_operate = 0; + sec_cnt = 0; + psys->adpc_step = 3; + atsc_para.system_para.adpc = ADPC_OFF; + c256_bytewrite(EEPROM_DPD_ADDR,ADPC_OFF); + dpd_log_string_save( "phase 6.MANUAL E_QUERY_SKIP. Will DPD_SUCCESS"); + log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase6: MANUAL E_QUERY_SKIP. Will DPD_SUCCESS\n"); + goto DPD_SUCCESS; + } + else if(g_query_operate==E_QUERY_OK_CONTINUE) + { + g_query_operate=0; + psys->dpd_phase=7; + sec_cnt = 0; + phase_in_flag = 1; + dpd_log_string_save( "phase 6.MANUAL E_QUERY_OK_CONTINUE. Will enter phase 7"); + } + else if(g_query_operate==E_QUERY_ESC_EXIT) + { + g_query_operate=0; + sec_cnt = 0; + phase_in_flag = 1; + psys->adpc_err=DPD_PROC_EXIT; + dpd_log_string_save( "phase 6.MANUAL E_QUERY_ESC_EXIT. Will DPD_END"); + goto DPD_END; + } + + } + else{//AUTO + + #if USE_REMOTE_DPD + //for udp + if(adpc_source_udp){ + adpc_source_udp = 0; + g_query_save_flg= 0; + g_query_save = 0; + psys->adpc_step = 3; + atsc_para.system_para.adpc = ADPC_HOLD;//断电失效 + c256_bytewrite(EEPROM_DPD_ADDR,ADPC_OFF); + dpd_log_string_save( " adpc_source_udp = 1. set STEP = 3., Will DPD_END"); + log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 6: adpc_source_udp = 1. set STEP = 3., Will DPD_END\n"); + goto DPD_END; + } + //for web and uart + if(adpc_source_web){ + g_query_operate = E_QUERY_RF_FLITER; + log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 6:---- E_QUERY_RF_FLITER\n"); + } + #endif + + //normal-exe + if(atsc_para.wj_para.ctl_dpd==E_DPD_NSAVE_NFLITER) + { + g_query_save_flg = PHASE6_SET_SAVE; + g_query_save = E_QUERY_CANCEL; + log_printf(LOG_DEBUG, I_USER_CFG, "sta-6.normal no save, no fliter\n"); + } + else if(atsc_para.wj_para.ctl_dpd==E_DPD_SAVE_NFLITER) + { + g_query_save_flg = PHASE6_SET_SAVE; + g_query_save = E_QUERY_CONFIRM; + log_printf(LOG_DEBUG, I_USER_CFG, "sta-6.normal save, no fliter\n"); + } + else if(atsc_para.wj_para.ctl_dpd==E_DPD_NSAVE_FLITER||atsc_para.wj_para.ctl_dpd==E_DPD_SAVE_FLITER) + { + if(psys->adpc==ADPC_UPDATE3) { + g_query_operate=0; + //psys->dpd_phase=0; + sec_cnt = 0xFFFF; + phase_in_flag = 0; + g_query_save = E_QUERY_CONFIRM; + g_query_save_flg = PHASE6_SET_SAVE; + log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase6: done, will save data..........\n"); + dpd_log_string_save( "phase 6.AUTO E_QUERY_RF_FLITER. Will enter save data"); + goto DPD_SAVE_PROC; + + } else { + + g_query_operate=0; + psys->dpd_phase=7; + sec_cnt = 0; + phase_in_flag = 1; + log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 7:------Will enter phase 7 \n"); + + if(atsc_para.wj_para.ctl_dpd==E_DPD_SAVE_FLITER) + log_printf(LOG_DEBUG, I_USER_CFG, "sta-6.normal save, fliter\n"); + else if(atsc_para.wj_para.ctl_dpd==E_DPD_NSAVE_FLITER) + log_printf(LOG_DEBUG, I_USER_CFG, "sta-6.normal no save, fliter\n"); + dpd_log_string_save( "phase 6.AUTO E_QUERY_RF_FLITER. Will enter phase 7"); + } + } + else{ + + if(g_query_operate == 0){//query fliter + g_query_operate = E_QUERY2; + log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase6: E_QUERY2\n"); + } + else if(g_query_operate == E_QUERY_ESC_SAVE) {//query save + g_query_save_flg = PHASE6_SET_SAVE;// p6 + log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase6: E_QUERY_ESC_SAVE PHASE6_SET_SAVE\n"); + dpd_log_string_save( "phase 6.AUTO E_QUERY_ESC_SAVE ,PHASE6_SET_SAVE "); + } + else if(g_query_operate==E_QUERY_RF_FLITER) { + if(psys->adpc==ADPC_UPDATE3) { + g_query_operate=0; + psys->dpd_phase=0; + sec_cnt = 0; + phase_in_flag = 0; + g_query_save =E_QUERY_CONFIRM; + g_query_save_flg = PHASE6_SET_SAVE; + log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase6: done, will save data.\n"); + dpd_log_string_save( "phase 6.AUTO E_QUERY_RF_FLITER. Will enter save data"); + goto DPD_SAVE_PROC; + + }else{ + g_query_operate=0; + psys->dpd_phase=7; + sec_cnt = 0; + phase_in_flag = 1; + log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase6: AUTO E_QUERY_RF_FLITER. Will enter phase 7\n"); + dpd_log_string_save( "phase 6.AUTO E_QUERY_RF_FLITER. Will enter phase 7"); + } + + } + } + + } + #endif + } + + break; + + + case 7: + ////////////// 7-2-AGC + // in + psys->dpd_phase=7; + if(phase_in_flag) //进入phase时执行一次的初始化操作 + { + dpd_log_string_save( "phase 7. in :"); + dpd_log_read_and_save( psys->dpd_phase); + phase_in_flag = 0; + dpd_log_string_save( "dpd rf sel: after"); + + dpd_ctl2_reg = 0; + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); + + dpd_ctl3_reg = (DPD_CTRL3_SYNC_RESTART | DPD_CTRL3_FAGC_UPDATE | DPD_CTRL3_DAGC_UPDATE | DPD_CTRL3_DCRM_UPDATE ); + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); + + u_dpdctl_r23.dpd_bt.iqb_upd =0; + u_dpdctl_r23.dpd_bt.sync_mode=1; + u_dpdctl_r23.dpd_bt.rf_sel = DPD_RF_SEL_VALUE(E_SELECT_A); + fpga_byte_write(5,FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); + log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 7: 0x%x\n", u_dpdctl_r23.u8val); + + s_fagc_locked = 0; + } + + // 前半段跑完, 锁死射频AGC, 后半段只留数字AGC收敛(见 FAGC_LOCK_SEC 注释) + if(!s_fagc_locked && sec_cnt >= FAGC_LOCK_SEC) + { + s_fagc_locked = 1; + // 只清 FAGC_UPDATE(bit0), SYNC_RESTART 必须继续保持到相8才放开 + dpd_ctl3_reg = (DPD_CTRL3_SYNC_RESTART | DPD_CTRL3_DAGC_UPDATE | DPD_CTRL3_DCRM_UPDATE); + fpga_byte_write(5, FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); + log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 7: FAGC locked at %ds, CTRL3=0x%02x\n", + sec_cnt, dpd_ctl3_reg); + dpd_log_string_save("phase 7. FAGC locked, DAGC only"); + } + + dpd_log_read_and_save( psys->dpd_phase); + + // out + if(sec_cnt >= 20 || g_query_skip == E_QUERY_SKIP){ // 计时超过20秒离开phase7 + if(g_query_skip == E_QUERY_SKIP) + g_query_skip=E_QUERY; + + g_pow_state_check = 1; + psys->dpd_phase=8; // 离开前进行的操作 + sec_cnt = 0; + phase_in_flag = 1; + dpd_log_string_save("phase 7. E_QUERY_SKIP will enter phase 8"); + } + break; + + case 8: + ////////////// 8-3-TX RX SYNC + // in + + psys->dpd_phase=8; + if(phase_in_flag) //进入phase时执行一次的初始化操作 + { + dpd_log_string_save( "phase 8. in :"); + dpd_log_read_and_save( psys->dpd_phase); + phase_in_flag = 0; + dpd_ctl2_reg = 0; + dpd_ctl3_reg = (DPD_CTRL3_SYNC_UPDATE | DPD_CTRL3_DCRM_UPDATE); + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); + } + dpd_log_read_and_save( psys->dpd_phase); + //out + if(rd_reg & MASK_DPD_TRX_SYNC_OK || g_query_skip == E_QUERY_SKIP) // 读取到dpd_trx_sync_ok状态为1时进入下一阶段 + { + if(g_query_skip == E_QUERY_SKIP) + g_query_skip = E_QUERY; + + // set fix delay + psys->dpd_phase=9; + sec_cnt = 0; + phase_in_flag = 1; + dpd_log_string_save( "Phase 8. out , Will enter phase 9"); + } + else if(sec_cnt >= 80)// 超过80秒未读到sync ok， 同步失败，退出校正 + { + log_printf(LOG_DEBUG, I_USER_CFG, "[update] TX RX sync failed\r\n"); + dpd_log_string_save( "Phase 8. TX RX sync failed, Will DPD_END"); + psys->adpc_err = DPD_SYNC_TIMEOUT; + goto DPD_END; + } + break; + + case 9: + ////////////// 9-4-ROT + // in + psys->dpd_phase=9; + if(phase_in_flag) { + dpd_log_string_save( "phase 9. in :"); + dpd_log_read_and_save( psys->dpd_phase); + phase_in_flag = 0; + dpd_ctl2_reg = 0; + + + dpd_ctl3_reg = ((DPD_CTRL3_DAGC_UPDATE|DPD_CTRL3_DAGC_SLOWDN) | (DPD_CTRL3_ROT_UPDATE)); + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); + + u_dpdctl_r23.dpd_bt.iqb_upd =1; + log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 9 --- 0x%x\n", u_dpdctl_r23.u8val); + fpga_byte_write(5,FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); + } + + dpd_log_read_and_save( psys->dpd_phase); + + // out + if(sec_cnt >= 30 || g_query_skip == E_QUERY_SKIP) // 计时到15秒进入下一阶段 + { + if(g_query_skip == E_QUERY_SKIP){g_query_skip=E_QUERY;sec_cnt=15;} + if(atsc_para.dpd_para.dpd_mode==E_DPD_MODE_MANUAL) + {//MANUAL + if(g_query_operate==0)g_query_operate=E_QUERY; + if(g_query_operate == E_QUERY_UP_STOP) + { + g_query_operate = 0; + sec_cnt = 0; + psys->adpc_step = 3; + atsc_para.system_para.adpc = ADPC_OFF; + c256_bytewrite(EEPROM_DPD_ADDR,ADPC_OFF); + dpd_log_string_save( "Phase 9. MANUAL E_QUERY_SKIP, Will DPD_SUCCESS"); + goto DPD_SUCCESS; + } + else if(g_query_operate==E_QUERY_OK_CONTINUE) + { + g_query_operate=0; + psys->dpd_phase=10; + sec_cnt = 0; + phase_in_flag = 1; + dpd_log_string_save( "Phase 9.MANUAL E_QUERY_OK_CONTINUE, Will enter phase 10"); + } + else if(g_query_operate==E_QUERY_ESC_EXIT) + { + g_query_operate=0; + sec_cnt = 0; + phase_in_flag = 1; + psys->adpc_err=DPD_PROC_EXIT; + dpd_log_string_save( "Phase 9.MANUAL E_QUERY_ESC_EXIT, Will DPD_END"); + goto DPD_END; + } + + } + else{//AUTO + g_query_operate=0; + psys->dpd_phase=10; + sec_cnt = 0; + phase_in_flag = 1; + dpd_log_string_save( "Phase 9.auto Will enter phase 10"); + } + } + break; + case 10: + ////////////// 10-4-Linear update + // in + psys->dpd_phase = 10; + if(phase_in_flag) { + log_printf(LOG_DEBUG, I_USER_CFG, "ph10_time = %d min\n",atsc_para.wj_para.ph10_time); + dpd_log_string_save( "Phase 10 in"); + dpd_log_read_and_save( psys->dpd_phase); + + fpga_byte_write(5,FPGA_ADDR_DPD_CFG_STEP, 0); + fpga_byte_write(5,0x25, 0xff); + fpga_byte_write(5,0x26, 0x04); + + phase_in_flag = 0; + dpd_ctl2_reg = (DPD_CTRL2_PRL_UPDATE|DPD_CTRL2_AMP_CHK); + dpd_ctl3_reg = 0; // oneshu remove dags + + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, dpd_ctl2_reg); + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, dpd_ctl3_reg); + + u_dpdctl_r23.dpd_bt.iqb_upd = 0; + fpga_byte_write(5,FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); + log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 10 --- 0x%x\n", u_dpdctl_r23.u8val); + } + dpd_log_read_and_save( psys->dpd_phase); + // out + if(sec_cnt >= atsc_para.wj_para.ph10_time*60 || g_query_skip == E_QUERY_SKIP) // 300 + { + //note web set first + if(atsc_para.wj_para.ctl_dpd==E_DPD_SAVE_FLITER){ + g_query_save =E_QUERY_CONFIRM; + log_printf(LOG_DEBUG, I_USER_CFG, "sta-10.save, fliter\n"); + } + else if(atsc_para.wj_para.ctl_dpd==E_DPD_NSAVE_FLITER){ + g_query_save =E_QUERY_CANCEL; + log_printf(LOG_DEBUG, I_USER_CFG, "sta-10.no save, no fliter\n"); + } + else{ + g_query_save =E_QUERY_CANCEL; + } + + #if USE_REMOTE_DPD + //for web and uart + if(adpc_source_web){ + adpc_source_web = 0; + g_query_save =E_QUERY_CONFIRM; + } + #endif + + if(g_query_skip == E_QUERY_SKIP) { + g_query_skip=E_QUERY; + sec_cnt=0xffff; + } + //printf("\r\n step finished, finish the dpd process? >> "); + + g_query_save_flg = PHASE10_SET_SAVE;// p10 + dpd_log_string_save( "Phase 10 out, PHASE10_SET_SAVE"); + + + } + break; + default: + break; + } + + +#if 1 +DPD_SAVE_PROC: + if(g_query_save_flg != 0) { + /*if(g_query_save == 0) + g_query_save = E_QUERY;*/ + + if(g_query_save==E_QUERY_CONFIRM) { + if(g_query_save_flg == PHASE6_SET_SAVE) + g_query_operate = 0; + + g_query_save_flg = 0; + g_query_save = 0; + //初始化配置，所有的 “控制”寄存器全部置0, 在ctrl123均配置0时,顺序应为2 1 3. + fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL2, 0); + fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL1, 0); + fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, 0); + + u_dpdctl_r23.u8val = 0; + u_dpdctl_r23.dpd_bt.rf_sel = DPD_RF_SEL_VALUE(E_SELECT_A); + fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); + log_printf(LOG_DEBUG, I_USER_CFG, "[update] save data --- 0x%x\n", u_dpdctl_r23.u8val); + + + fpga_byte_write(0x05, FPGA_ADDR_WPP_EN_CLR, 0); + fpga_byte_write(0x05, FPGA_ADDR_WPP_EN_CLR, MASK_WPP_CLR); + fpga_byte_write(0x05, FPGA_ADDR_WPP_EN_CLR, 0); + + dpd_curve_proc(E_LOAD_TO_MCU); + if(dpd_ck_status==CK_OK){ + psys->adpc_step = 3; + atsc_para.system_para.adpc = ADPC_HOLD;//断电保持 + c256_bytewrite(EEPROM_DPD_ADDR, ADPC_HOLD); + c256_bytewrite(EEPROM_DPD_FLASH_VALID, 1); + log_printf(LOG_DEBUG, I_USER_CFG, "dpd load to mcu ok\n"); + dpd_log_string_save("g_query_save E_QUERY_CONFIRM CK_OK, will DPD_SUCCESS"); + goto DPD_SUCCESS; + } + else{ + atsc_para.system_para.adpc = ADPC_OFF; + c256_bytewrite(EEPROM_DPD_ADDR, ADPC_OFF); + psys->adpc_err = DPD_READ_CKECK_ERR; + log_printf(LOG_DEBUG, I_USER_CFG, "dpd load to mcu err\n"); + dpd_log_string_save("g_query_save E_QUERY_CONFIRM !CK_OK, will DPD_END"); + goto DPD_END; + } + } + else if(g_query_save==E_QUERY_CANCEL) + { + if(g_query_save_flg==PHASE6_SET_SAVE) + g_query_operate=0; + + g_query_save_flg=0; + g_query_save=0; + psys->adpc_step = 3; + atsc_para.system_para.adpc = ADPC_HOLD;//断电失效 + c256_bytewrite(EEPROM_DPD_ADDR,ADPC_OFF); + dpd_log_string_save("g_query_save E_QUERY_CANCEL , will DPD_SUCCESS"); + goto DPD_SUCCESS; + } + } +#endif + + gettimeofday(&now_tv, NULL); now_sec = (uint32)now_tv.tv_sec; if(last_sec_tick == 0) { @@ -2917,290 +2919,291 @@ DPD_SAVE_PROC: } break; } - - //-------------------------------------------------------------------- - - DPD_SUCCESS: - // DPD成功后停止校正过程，注意这里不含曲线的存储，即“Save to mcu”过程, 需弹出询问和添加save过程 - if(psys->adpc_step==3){ - // 顺序应为 2 - 1 - 3 - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, 0); - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL1, 0); - fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, 0); - u_dpdctl_r23.u8val = 0; - fpga_byte_write(5,FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); - log_printf(LOG_DEBUG, I_USER_CFG, "[update] success --- u_dpdctl_r23=0x%x\n", u_dpdctl_r23.u8val); - - fpga_byte_write(5,FPGA_ADDR_WPP_EN_CLR, 0); - fpga_byte_write(5,FPGA_ADDR_WPP_EN_CLR, MASK_WPP_CLR); - fpga_byte_write(5,FPGA_ADDR_WPP_EN_CLR, 0); - -// if(g_trigger_up_tsnr_flg == 0) { -// g_trigger_up_tsnr_flg = 1; -// g_trigger_up_start_flg = 1; -// printf("Do phase 78910 in background progress ~~\n"); -// } - S_SYS_TIME bak_time = {0xff,};//本地时间 - S_SYS_TIME now_time = {0,}; - int ret = 0; - uint8 reset_up = 1; - uint8 uuu_phase = 0; - uint8 old_phase = 0; - char show_perc[5] = {0}; - psys->final_stage = 3; - - lcd_write_string(LINE_1,0," WAIT A MOMENT .... "); - lcd_write_string(LINE_2,0," FINAL STAGE "); - lcd_write_cache(); - while(1) - { - get_sys_time(&now_time); - - if(bak_time.sec != now_time.sec) { - pthread_mutex_lock(&mtx_phase78910_again); - ret = update_tsnr_uimd_limd(reset_up,&uuu_phase); - if(reset_up) - reset_up = 0; - if(uuu_phase!=old_phase){ - psys->final_stage = 10-uuu_phase; - old_phase = uuu_phase; - memset(show_perc, 0, sizeof(show_perc)); - sprintf(show_perc, "%d ", 10-uuu_phase); - lcd_write_string(LINE_2, 15, show_perc); - lcd_write_cache(); - } - - if(ret == 1) { - pthread_mutex_unlock(&mtx_phase78910_again); - break; - } - pthread_mutex_unlock(&mtx_phase78910_again); - - get_sys_time(&bak_time); - } - usleep(20000);// 20ms - } - - reset_dpd_to_normal_state(); - psys->final_stage = 0xff; - - //finished - atsc_para.system_para.adpc_step = 0x21; - atsc_para.system_para.dpd_phase = 0; - atsc_para.system_para.adpc_err = 0; - - //for auto check dpd - update_flag = 0; - if(( TRUE == auto_update ) &&(s_check_signal.adpc_flag) ){ - update_adpc_para_flag.flag=TRUE; - update_adpc_para_flag.sec = 60; - s_check_signal.adpc_flag = FALSE; - } - - ret_father_menu(); - dpd_log_file_close( "DPD Success, and Step=3"); - } - - DPD_END: - // 异常状态下的退出处理 - if(psys->adpc_err&&(psys->adpc_err!=DPD_STATUS_UPDATING)&&psys->adpc_step!=0){ - - dpd_log_read_and_save_end("DPD process abort"); - - light_on_forever(); - - if(psys->adpc_err==DPD_CHECK_WPP_ERR_EXIT_HOLD){ - psys->adpc = ADPC_HOLD; - dpd_log_read_and_save_end("check wpp DPD process esc and hold"); - reset_dpd_to_normal_state(); - } - else - { - psys->adpc = ADPC_OFF; - c256_bytewrite(EEPROM_DPD_ADDR, ADPC_OFF); - - dpd_set_clr(); - dpd_exit(); - - log_printf(LOG_DEBUG,I_NOUSED,"\b DPD process abort\r\n"); - dpd_log_file_close( "DPD process abort due to ADPC_OFF. DPD_END"); - - //dpd_boot_run_init(); - reset_dpd_to_normal_state(); - } - - //ret_father_menu(); - if(psys->adpc_err != DPD_PROC_EXIT) - psys->adpc_step = 0; - - } - - if(psys->adpc_err && (psys->adpc_err != DPD_STATUS_UPDATING)) { - dpd_disp_step = psys->adpc_err; - if(g_query_save != 0) - g_query_save = 0; - - if(g_query_operate != 0) - g_query_operate = 0; - } - else if(g_query_operate==E_QUERY) - dpd_disp_step = 0x88; - else if(g_query_operate==E_QUERY2) - dpd_disp_step = 0x77; - else if(g_query_save==E_QUERY) - dpd_disp_step = 0x66; - else if(g_query_wpp_to_save==E_QUERY) - dpd_disp_step = 0x55; - else if(g_prompt_skip_wpp==1) - dpd_disp_step = 0x44; - else - dpd_disp_step = psys->adpc_step; - - - switch(dpd_disp_step) { - case 0: - switch(disp_sec%3) - { - case 0: - sprintf(out_str, "WAIT A MOMENT. PREPARE UPDATING"); - break; - case 1: - sprintf(out_str, "WAIT A MOMENT.. PREPARE UPDATING"); - break; - case 2: - sprintf(out_str, "WAIT A MOMENT... PREPARE UPDATING"); - break; - } - lcd_write_string(0,0," "); - lcd_write_string(0,0,out_str); - lcd_write_string(1,0," *CANCEL (ADPC OFF) "); - //dpd_log_file_close(p_dpd_log_fp, out_str); - break; - case 2: //校正中 - switch(disp_sec%3) - { - case 0://dpd_sat_flg - sprintf(out_str, "WAITING(%02d). SNR MAXP ",psys->dpd_phase);//"WAIT A MOMENT(%02d). TSNR TXP WPP " - break; - case 1: - sprintf(out_str, "WAITING(%02d).. SNR MAXP ",psys->dpd_phase);//"WAIT A MOMENT(%02d).. TSNR TXP WPP " - break; - case 2: - sprintf(out_str, "WAITING(%02d)... SNR MAXP ",psys->dpd_phase);//"WAIT A MOMENT(%02d)... TSNR TXP WPP " - break; - } - lcd_write_string(0,0,out_str); - lcd_write_string(1,0, "[Esc]Exit [->]Next ");//"[Esc]Exit [->]Next " - - psys->tsnr = u16_tsnr; - psys->maxp = wpp_max; - sprintf(out_str,"%02d.%01d",u16_tsnr/100,(u16_tsnr%100)/10); - lcd_write_string(1,19,out_str); - - sprintf(out_str,"%d",wpp_max); - lcd_write_string(1,26,out_str);// 25 - - if(dpd_sat_flg==1){ - lcd_write_string(LINE_2,39,"s"); - } - else{ - lcd_write_string(LINE_2,39," "); - } - break; - - case DPD_STATE_ERR: - //lcd_write_string(0,0, " POWER RISE TOO MUCH ERROR! "); - lcd_write_string(0,0, " ADPC stoped - PA protection! [1]"); - lcd_write_string(1,0, " Press Any key to ESC "); - break; - case DPD_STATE_POWER_HIGH: - //lcd_write_string(0,0, " FEEDBACK POWER IS HIGH! "); - lcd_write_string(0,0, " ADPC failed - Feedback high! [2]"); - lcd_write_string(1,0, " Press Any key to ESC "); - break; - case DPD_STATE_POWER_LOW: - //lcd_write_string(0,0, " FEEDBACK POWER IS SMALL! "); - lcd_write_string(0,0, " ADPC failed - Feedback low! [3]"); - lcd_write_string(1,0, " Press Any key to ESC "); - break; - case DPD_STATE_POWER_TOO_HIGH: - //lcd_write_string(0,0, " DAGC INPUT HIGH! "); - lcd_write_string(0,0, " ADPC failed - Feedback high! [4]"); - lcd_write_string(1,0, " Press Any key to ESC "); - break; - case DPD_STATE_POWER_TOO_LOW: - //lcd_write_string(0,0, " DAGC INPUT SMALL! "); - lcd_write_string(0,0, " ADPC failed - Feedback low! [5]"); - lcd_write_string(1,0, " Press Any key to ESC "); - break; - case DPD_STATE_ERR_OVER_RANGE: - //lcd_write_string(0,0, " ERROR IS TOO LARGE! "); - if(psys->dpd_phase>=1 && psys->dpd_phase<=6){ - lcd_write_string(0,0, " ADPC stoped - Over distortion! [6]"); - lcd_write_string(1,0, " Press Any key to ESC "); - } - else if(psys->dpd_phase){ - lcd_write_string(0,0, " ADPC stoped - Check RF filter! [6]"); - lcd_write_string(1,0, " Press Any key to ESC "); - } - break; - - case DPD_READ_CKECK_ERR: - //lcd_write_string(0,0, " DPD READ FPGA CHECK ERROR! "); - lcd_write_string(0,0, " ADPC data save error! [8]"); - lcd_write_string(1,0, " Press Any key to ESC "); - break; - case DPD_SYNC_TIMEOUT: - lcd_write_string(0,0, " ADPC failed - Sync time out! [10]"); - lcd_write_string(1,0, " Press Any key to ESC "); - break; - - case 0x99: - ret_father_menu(); - sec_cnt = 0; - psys->adpc_step = 0; - psys->adpc_err = 0; - psys->dpd_phase = 0; - break; - //g_prompt_skip_wpp - case 0x44: - if(atsc_para.wj_para.ctl_dpd==E_DPD_SAVE_FLITER||atsc_para.wj_para.ctl_dpd==E_DPD_NSAVE_FLITER){ - sprintf(out_str," Enter Next Phase [%02d] WPPMAX ",g_skip_next_dly); - } - else{ - sprintf(out_str," Check WPP, Esc Now[%02d] WPPMAX ",g_skip_next_dly); - } - - lcd_write_string(0,0, out_str); - lcd_write_string(1,0, " "); - memset(out_str,0,sizeof(out_str)); - sprintf(out_str,"%d",g_wpp_max);//g_wpp_max - lcd_write_string(1,33,out_str); - break; - case 0x55:case DPD_CHECK_WPP_ERR_EXIT_HOLD: - //lcd_write_string(0,0, " Checked Pulse Power Over,Process Abort "); - //lcd_write_string(1,0, " [OK] Yes "); - lcd_write_string(0,0, " ADPC stoped - PA protection! [7]"); - lcd_write_string(1,0, " [OK] Yes "); - break; - case 0x66: - lcd_write_string(0,0, " Save ADPC ? "); - lcd_write_string(1,0, " [OK] Yes [ESC] Exit "); - break; - case 0x77: - lcd_write_string(0,0, " START LINEAR ADPC ? "); - lcd_write_string(1,0, " [OK] Yes [ESC] Skip&Save "); - break; - case 0x88: - sprintf(out_str, " Continue to step %d ",psys->dpd_phase+1); - lcd_write_string(0,0, out_str); - //lcd_write_string(1,0, "[OK]Continue [->]Skip [^]Stop [ESC]Exit");//" [OK] Continue [->] Skip [ESC] Exit " - lcd_write_string(1,0, " [OK]Continue [^]Stop [ESC]Exit "); - break; - default:break; - } - - + + //-------------------------------------------------------------------- + + DPD_SUCCESS: + // DPD成功后停止校正过程，注意这里不含曲线的存储，即“Save to mcu”过程, 需弹出询问和添加save过程 + if(psys->adpc_step==3){ + // 顺序应为 2 - 1 - 3 + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL2, 0); + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL1, 0); + fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, 0); + u_dpdctl_r23.u8val = 0; + u_dpdctl_r23.dpd_bt.rf_sel = DPD_RF_SEL_VALUE(E_SELECT_A); + fpga_byte_write(5,FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); + log_printf(LOG_DEBUG, I_USER_CFG, "[update] success --- u_dpdctl_r23=0x%x\n", u_dpdctl_r23.u8val); + + fpga_byte_write(5,FPGA_ADDR_WPP_EN_CLR, 0); + fpga_byte_write(5,FPGA_ADDR_WPP_EN_CLR, MASK_WPP_CLR); + fpga_byte_write(5,FPGA_ADDR_WPP_EN_CLR, 0); + +// if(g_trigger_up_tsnr_flg == 0) { +// g_trigger_up_tsnr_flg = 1; +// g_trigger_up_start_flg = 1; +// printf("Do phase 78910 in background progress ~~\n"); +// } + S_SYS_TIME bak_time = {0xff,};//本地时间 + S_SYS_TIME now_time = {0,}; + int ret = 0; + uint8 reset_up = 1; + uint8 uuu_phase = 0; + uint8 old_phase = 0; + char show_perc[5] = {0}; + psys->final_stage = 3; + + lcd_write_string(LINE_1,0," WAIT A MOMENT .... "); + lcd_write_string(LINE_2,0," FINAL STAGE "); + lcd_write_cache(); + while(1) + { + get_sys_time(&now_time); + + if(bak_time.sec != now_time.sec) { + pthread_mutex_lock(&mtx_phase78910_again); + ret = update_tsnr_uimd_limd(reset_up,&uuu_phase); + if(reset_up) + reset_up = 0; + if(uuu_phase!=old_phase){ + psys->final_stage = 10-uuu_phase; + old_phase = uuu_phase; + memset(show_perc, 0, sizeof(show_perc)); + sprintf(show_perc, "%d ", 10-uuu_phase); + lcd_write_string(LINE_2, 15, show_perc); + lcd_write_cache(); + } + + if(ret == 1) { + pthread_mutex_unlock(&mtx_phase78910_again); + break; + } + pthread_mutex_unlock(&mtx_phase78910_again); + + get_sys_time(&bak_time); + } + usleep(20000);// 20ms + } + + reset_dpd_to_normal_state(); + psys->final_stage = 0xff; + + //finished + atsc_para.system_para.adpc_step = 0x21; + atsc_para.system_para.dpd_phase = 0; + atsc_para.system_para.adpc_err = 0; + + //for auto check dpd + update_flag = 0; + if(( TRUE == auto_update ) &&(s_check_signal.adpc_flag) ){ + update_adpc_para_flag.flag=TRUE; + update_adpc_para_flag.sec = 60; + s_check_signal.adpc_flag = FALSE; + } + + ret_father_menu(); + dpd_log_file_close( "DPD Success, and Step=3"); + } + + DPD_END: + // 异常状态下的退出处理 + if(psys->adpc_err&&(psys->adpc_err!=DPD_STATUS_UPDATING)&&psys->adpc_step!=0){ + + dpd_log_read_and_save_end("DPD process abort"); + + light_on_forever(); + + if(psys->adpc_err==DPD_CHECK_WPP_ERR_EXIT_HOLD){ + psys->adpc = ADPC_HOLD; + dpd_log_read_and_save_end("check wpp DPD process esc and hold"); + reset_dpd_to_normal_state(); + } + else + { + psys->adpc = ADPC_OFF; + c256_bytewrite(EEPROM_DPD_ADDR, ADPC_OFF); + + dpd_set_clr(); + dpd_exit(); + + log_printf(LOG_DEBUG,I_NOUSED,"\b DPD process abort\r\n"); + dpd_log_file_close( "DPD process abort due to ADPC_OFF. DPD_END"); + + //dpd_boot_run_init(); + reset_dpd_to_normal_state(); + } + + //ret_father_menu(); + if(psys->adpc_err != DPD_PROC_EXIT) + psys->adpc_step = 0; + + } + + if(psys->adpc_err && (psys->adpc_err != DPD_STATUS_UPDATING)) { + dpd_disp_step = psys->adpc_err; + if(g_query_save != 0) + g_query_save = 0; + + if(g_query_operate != 0) + g_query_operate = 0; + } + else if(g_query_operate==E_QUERY) + dpd_disp_step = 0x88; + else if(g_query_operate==E_QUERY2) + dpd_disp_step = 0x77; + else if(g_query_save==E_QUERY) + dpd_disp_step = 0x66; + else if(g_query_wpp_to_save==E_QUERY) + dpd_disp_step = 0x55; + else if(g_prompt_skip_wpp==1) + dpd_disp_step = 0x44; + else + dpd_disp_step = psys->adpc_step; + + + switch(dpd_disp_step) { + case 0: + switch(disp_sec%3) + { + case 0: + sprintf(out_str, "WAIT A MOMENT. PREPARE UPDATING"); + break; + case 1: + sprintf(out_str, "WAIT A MOMENT.. PREPARE UPDATING"); + break; + case 2: + sprintf(out_str, "WAIT A MOMENT... PREPARE UPDATING"); + break; + } + lcd_write_string(0,0," "); + lcd_write_string(0,0,out_str); + lcd_write_string(1,0," *CANCEL (ADPC OFF) "); + //dpd_log_file_close(p_dpd_log_fp, out_str); + break; + case 2: //校正中 + switch(disp_sec%3) + { + case 0://dpd_sat_flg + sprintf(out_str, "WAITING(%02d). SNR MAXP ",psys->dpd_phase);//"WAIT A MOMENT(%02d). TSNR TXP WPP " + break; + case 1: + sprintf(out_str, "WAITING(%02d).. SNR MAXP ",psys->dpd_phase);//"WAIT A MOMENT(%02d).. TSNR TXP WPP " + break; + case 2: + sprintf(out_str, "WAITING(%02d)... SNR MAXP ",psys->dpd_phase);//"WAIT A MOMENT(%02d)... TSNR TXP WPP " + break; + } + lcd_write_string(0,0,out_str); + lcd_write_string(1,0, "[Esc]Exit [->]Next ");//"[Esc]Exit [->]Next " + + psys->tsnr = u16_tsnr; + psys->maxp = wpp_max; + sprintf(out_str,"%02d.%01d",u16_tsnr/100,(u16_tsnr%100)/10); + lcd_write_string(1,19,out_str); + + sprintf(out_str,"%d",wpp_max); + lcd_write_string(1,26,out_str);// 25 + + if(dpd_sat_flg==1){ + lcd_write_string(LINE_2,39,"s"); + } + else{ + lcd_write_string(LINE_2,39," "); + } + break; + + case DPD_STATE_ERR: + //lcd_write_string(0,0, " POWER RISE TOO MUCH ERROR! "); + lcd_write_string(0,0, " ADPC stoped - PA protection! [1]"); + lcd_write_string(1,0, " Press Any key to ESC "); + break; + case DPD_STATE_POWER_HIGH: + //lcd_write_string(0,0, " FEEDBACK POWER IS HIGH! "); + lcd_write_string(0,0, " ADPC failed - Feedback high! [2]"); + lcd_write_string(1,0, " Press Any key to ESC "); + break; + case DPD_STATE_POWER_LOW: + //lcd_write_string(0,0, " FEEDBACK POWER IS SMALL! "); + lcd_write_string(0,0, " ADPC failed - Feedback low! [3]"); + lcd_write_string(1,0, " Press Any key to ESC "); + break; + case DPD_STATE_POWER_TOO_HIGH: + //lcd_write_string(0,0, " DAGC INPUT HIGH! "); + lcd_write_string(0,0, " ADPC failed - Feedback high! [4]"); + lcd_write_string(1,0, " Press Any key to ESC "); + break; + case DPD_STATE_POWER_TOO_LOW: + //lcd_write_string(0,0, " DAGC INPUT SMALL! "); + lcd_write_string(0,0, " ADPC failed - Feedback low! [5]"); + lcd_write_string(1,0, " Press Any key to ESC "); + break; + case DPD_STATE_ERR_OVER_RANGE: + //lcd_write_string(0,0, " ERROR IS TOO LARGE! "); + if(psys->dpd_phase>=1 && psys->dpd_phase<=6){ + lcd_write_string(0,0, " ADPC stoped - Over distortion! [6]"); + lcd_write_string(1,0, " Press Any key to ESC "); + } + else if(psys->dpd_phase){ + lcd_write_string(0,0, " ADPC stoped - Check RF filter! [6]"); + lcd_write_string(1,0, " Press Any key to ESC "); + } + break; + + case DPD_READ_CKECK_ERR: + //lcd_write_string(0,0, " DPD READ FPGA CHECK ERROR! "); + lcd_write_string(0,0, " ADPC data save error! [8]"); + lcd_write_string(1,0, " Press Any key to ESC "); + break; + case DPD_SYNC_TIMEOUT: + lcd_write_string(0,0, " ADPC failed - Sync time out! [10]"); + lcd_write_string(1,0, " Press Any key to ESC "); + break; + + case 0x99: + ret_father_menu(); + sec_cnt = 0; + psys->adpc_step = 0; + psys->adpc_err = 0; + psys->dpd_phase = 0; + break; + //g_prompt_skip_wpp + case 0x44: + if(atsc_para.wj_para.ctl_dpd==E_DPD_SAVE_FLITER||atsc_para.wj_para.ctl_dpd==E_DPD_NSAVE_FLITER){ + sprintf(out_str," Enter Next Phase [%02d] WPPMAX ",g_skip_next_dly); + } + else{ + sprintf(out_str," Check WPP, Esc Now[%02d] WPPMAX ",g_skip_next_dly); + } + + lcd_write_string(0,0, out_str); + lcd_write_string(1,0, " "); + memset(out_str,0,sizeof(out_str)); + sprintf(out_str,"%d",g_wpp_max);//g_wpp_max + lcd_write_string(1,33,out_str); + break; + case 0x55:case DPD_CHECK_WPP_ERR_EXIT_HOLD: + //lcd_write_string(0,0, " Checked Pulse Power Over,Process Abort "); + //lcd_write_string(1,0, " [OK] Yes "); + lcd_write_string(0,0, " ADPC stoped - PA protection! [7]"); + lcd_write_string(1,0, " [OK] Yes "); + break; + case 0x66: + lcd_write_string(0,0, " Save ADPC ? "); + lcd_write_string(1,0, " [OK] Yes [ESC] Exit "); + break; + case 0x77: + lcd_write_string(0,0, " START LINEAR ADPC ? "); + lcd_write_string(1,0, " [OK] Yes [ESC] Skip&Save "); + break; + case 0x88: + sprintf(out_str, " Continue to step %d ",psys->dpd_phase+1); + lcd_write_string(0,0, out_str); + //lcd_write_string(1,0, "[OK]Continue [->]Skip [^]Stop [ESC]Exit");//" [OK] Continue [->] Skip [ESC] Exit " + lcd_write_string(1,0, " [OK]Continue [^]Stop [ESC]Exit "); + break; + default:break; + } + + DPD_FORCE_STOP: if(atsc_adpc_force_stop_flag==TRUE) { @@ -3209,12 +3212,12 @@ DPD_FORCE_STOP: atsc_adpc_force_stop_flag = FALSE; atsc_para.system_para.adpc_step = 0; - atsc_para.system_para.adpc_err = 0; - atsc_para.system_para.dpd_phase = 0; - - if(1){//强制退出处理 - dpd_set_clr(); - dpd_exit(); + atsc_para.system_para.adpc_err = 0; + atsc_para.system_para.dpd_phase = 0; + + if(1){//强制退出处理 + dpd_set_clr(); + dpd_exit(); log_printf(LOG_DEBUG, I_USER_CFG, "\b DPD process abort\r\n"); dpd_log_file_close( "DPD force stop"); } @@ -3236,8 +3239,8 @@ DPD_FORCE_STOP: //dpd_boot_run_init(); reset_dpd_to_normal_state(); ret_father_menu(); - } - - - } - + } + + + } + diff --git a/src/atsc_app/inc/dpd_proc.h b/src/atsc_app/inc/dpd_proc.h index 0f02cb3..6e24f64 100755 --- a/src/atsc_app/inc/dpd_proc.h +++ b/src/atsc_app/inc/dpd_proc.h @@ -1,242 +1,250 @@ -#ifndef _DPD_PROC_H_ -#define _DPD_PROC_H_ - -#include "type.h" - -#define DPD_LOG_ENABLE 1 -#define DPD_LOG_FILE "/aw/anywave/dpd_log/log" - -#define FPGA_ADDR_DPD_LOG_TRIG 0x15 -//----Write Only-------------- -//ok -#define FPGA_ADDR_DPD_CTRL1 0x20 -#define FPGA_ADDR_DPD_CTRL2 0x21 -#define FPGA_ADDR_DPD_CTRL3 0x22 -//ok -#define FPGA_ADDR_DPD_IQB_UPD 0x23 -#define FPGA_ADDR_DPD_CFG_STEP 0x24 - - -//wpp -#define FPGA_ADDR_WPP_EN_CLR 0x0d -#define FPGA_ADDR_WPP_TH_L 0x0e -#define FPGA_ADDR_WPP_TH_H 0x0f - -#define MASK_WPP_ENABLE (1) -#define MASK_WPP_CLR (1<<1) - - -//#define FPGA_ADDR_DPD_SYNCOFFSET ?? - -#define FPGA_ADDR_DPD_TEST_L 0x02 -#define FPGA_ADDR_DPD_TEST_H 0x03 - -//----Read Only-------------- -#define FPGA_ADDR_DPD_STATUS1 0x01 - -//--------------------------- -#define MASK_RFAGC_DOWN_LIMIT (1<<1) -#define MASK_RFAGC_UP_LIMIT (1<<2) - -#define SPI_BLK_LEN 35//Byte - -enum{ - E_RFAGC_NORMAL=0, - E_RFAGC_DOWN_LIMIT, - E_RFAGC_UP_LIMIT, -}E_AGC_ERR_CODE; - /* - E_RFAGC_POWER_LOW, - E_RFAGC_POWER_HIGH, - */ - -//ok -#define MASK_DPD_ERR (0x0001) -#define MASK_DPD_PWRHIGH (0x0001<<1) -#define MASK_DPD_PWRLOW (0x0001<<2) -#define MASK_DPD_DAGC_TOOHIGH (0x0001<<3) -#define MASK_DPD_DAGC_TOOLOW (0x0001<<4) -#define MASK_DPD_ERR_ABORT (0x0001<<5) -#define MASK_DPD_TRX_SYNC_OK (0x0001<<6) -#define MASK_DPD_SAT_FLG (0x0001<<7) - -//ok -#define DPD_CTRL1_DPD_START (0x0001) -#define DPD_CTRL1_DPD_ALLCLR (0x0001<<1) -#define DPD_CTRL1_ALL_BYPS (0x0001<<2) - -#define DPD_CTRL2_LIN_UPDATE (0x0001) -#define DPD_CTRL2_NONLIN_UPDATE (0x0001<<1) -#define DPD_CTRL2_SET_NONLIN_UDP_MOD(x) (((x)&0x03)<<2) /*01 : POLY; 10: CRST*/ -#define DPD_CTRL2_AMP_CHK (0x0001<<4) -#define DPD_CTRL2_PRL_UPDATE (0x0001<<5) -#define DPD_CTRL2_RXEQ_UPDATE (0x0001<<6) - -#define DPD_CTRL2_POLYESTI_UPDATE (0x0001<<7) - -//ok -#define INTER_DISTORTION_SW_MAX (7) - - -//ok -#define DPD_CTRL3_FAGC_UPDATE (0x0001) -#define DPD_CTRL3_FAGC_SLOWDN (0x0001<<1) -#define DPD_CTRL3_DAGC_UPDATE (0x0001<<2) -#define DPD_CTRL3_DAGC_SLOWDN (0x0001<<3) -#define DPD_CTRL3_DCRM_UPDATE (0x0001<<4) -#define DPD_CTRL3_ROT_UPDATE (0x0001<<5) -#define DPD_CTRL3_SYNC_UPDATE (0x0001<<6) -#define DPD_CTRL3_SYNC_RESTART (0x0001<<7) -//ok -#define DPD_IQB_UPDATE (0x0001) -#define DPD_IQB_BP_MASK (0x0001<<1) -//#define DPD_IQB_SYNC_MASK (0x0001<<2) -#define DPD_SYNC_MODE_MASK (0x0001<<2) - -#define DPD_RF_SEL_BEFORE (0x0001<<3) - -#define DPD_SET_100M (0x00) -#define DPD_SET_25M (0x01) - -#define SET_DPDFAGC_REFPWR(x) ((x)) -#define DPD_SET_CRST_ADDR_STRUCT_2 ((0x01)<<17) -#define DPD_SET_ERR_TH(x) (((x)&0xffff)) -#define DPD_SET_ERR_CNT_TH(x) (((x)&0xff)<<16) -#define DPD_SET_DGAIN(x) (((x)&0xffff)<<2) -#define DPD_SET_FIX_DLY(x) (0x8000 & ((x)&0x7ff)) -#define DPD_SET_CRST_REFAD(x) ((x)[0] | ((x)[1]<<4) | ((x)[2]<<8) | ((x)[3]<<12) | ((x)[4]<<16) | ((x)[5]<<20)) - -#define DPD_MAX_TX_AMP_SAT 65535 -//#define TX_FREQ_IN_HZ 2550000000 - - -#define DPD_SEG 5 - -#define MASK_DPD_DATA_AREA0_MODE ((1)&0xff) -#define MASK_DPD_DATA_AREA1_MODE ((1<<1)&0xff) -#define MASK_DPD_DATA_AREA2_MODE ((1<<2)&0xff) -#define MASK_DPD_DATA_AREA3_MODE ((1<<3)&0xff) - -//#define MASK_TO_FPGA_WRITE_ENABLE ((1)) -#define MASK_TO_SPI_WR_RD_ENABLE (1) -#define MASK_TO_FPGA_REFRESH_DATA (1<<1) -#define MASK_TO_FPGA_CHECK_CLEAR (1<<2) - -enum{E_CHECK_FOR_RAED=0, E_CHECK_FOR_WIRTE=1}; - -typedef struct{ - u32 area_fpga_w_check; - u32 area_fpga_r_check; - u32 area_imx_w_check; - u32 area_imx_r_check; -}S_CHECK_SUM; - -//-------------------------------------------- - -/*Add Bit Ctrl*/ -typedef struct{ - uint8 iqb_upd:1; - uint8 iqb_bp:1; - uint8 sync_mode:1; /* !! sync_mode 与 re_sel 相反 */ - uint8 rf_sel:1; /* !! sync_mode 与 re_sel 相反 */ -}S_DPD_REG23; - -typedef union -{ - S_DPD_REG23 dpd_bt; - uint8 u8val; -}U_DPDCTL_REG23; -#define TSNR_FIX 3.5*100 - -enum{E_READ=0,E_WRITE=1}; - -typedef enum -{ - DPD_STATE_OK=0, - DPD_STATE_ERR=0x10, - DPD_STATE_POWER_HIGH, - DPD_STATE_POWER_LOW, - DPD_STATE_POWER_TOO_HIGH, - DPD_STATE_POWER_TOO_LOW, - DPD_STATE_ERR_OVER_RANGE, - DPD_STATE_SYNC_OK, - - DPD_READ_CKECK_ERR, - DPD_WRITE_CHECK_ERR, - - DPD_SYNC_TIMEOUT, - DPD_CHECK_WPP_ERR_EXIT_HOLD, - - //... - - DPD_IDLE_ERR=0x30, - - - DPD_PROC_EXIT = 0x99, - DPD_UPDATING, - DPD_SAVE_DATA = 0xAA, - DPD_LOAD_DATA = 0xBB, - DPD_STATUS_UPDATING = 0xff -}E_DPD_STATE; - -typedef enum{ -E_DPD_NSAVE_NFLITER=0x00,//0x00 -E_DPD_NSAVE_FLITER =0x01,//0x01 -E_DPD_SAVE_NFLITER =0x10,//0x10 -E_DPD_SAVE_FLITER =0x11,//0x11 -}E_CTL_DPD;//cttb_para.wh_para.ctl_dpd - - -// -typedef enum -{ - E_LOAD_TO_MCU, - E_LOAD_TO_FPGA, -}E_DPD_CURVE_PROC; - -typedef enum -{ - E_DPD_AREA0=0, - E_DPD_AREA1, - E_DPD_AREA2, - E_DPD_AREA3, - E_DPD_AREA_FIRST_4K, -}E_DPD_CURVE_AREA; - - -typedef struct -{ - uint32 tx_data_iq_i; - uint32 rx_data_iq_i; - uint16 ob_wpp_max_i; - uint16 txaveamp_i; - uint16 txpow_cur_i; - uint16 rx_dgain_i; - uint16 rx_fgain_cw_i; - uint16 dpd_dynamic_gain_i; // 发端算出、传给收端归一化的增益字 (14bit, seg5 0x32/0x33) - uint16 ob_b_pwr_i; // 预失真前功率 (14bit, seg5 0x34/0x35) - uint16 ob_a_pwr_i; // 预失真后功率 (14bit, seg5 0x36/0x37) -}S_DPD_LOG_TYPE; - -void refresh_update_dpd(void *parg,void *parv); -int dpd_curve_proc(uint8 proc_mode); - -void dpd_exit(void); -void dpd_set_clr(void); -uint8 get_fpga_dpd_check(void); -void dpd_boot_run_init(void); -extern void set_dpd_unit_area_auto_inc(uint8 inc_flg); -extern void set_tsnr_update_flg(uint8 up_flg); -extern int update_tsnr_uimd_limd(uint8 rst_flg,uint8* p_phase); -extern uint8 get_tsnr_update_flg(void); -extern void remote_set_dpd_clr(void); -extern uint8 conv_adpc_err_output(uint8 raw_dpd_err); - -extern void clear_dpd_data_file(void); -extern void set_ab_switch(E_AB_SEL ab_val); -extern u32 read_fpga_area_u32_check_sum(u8 check_type); -extern void clear_check_sum(S_CHECK_SUM *parea_check); -extern void calc_area_u32_check_sum(u32 *pcheck, u8 *pbuf, u32 len); -extern void calc_area_check_sum(u8 *pcheck, u8 *pbuf, u32 len); -#endif - +#ifndef _DPD_PROC_H_ +#define _DPD_PROC_H_ + +#include "type.h" + +#define DPD_LOG_ENABLE 1 +#define DPD_LOG_FILE "/aw/anywave/dpd_log/log" + +#define FPGA_ADDR_DPD_LOG_TRIG 0x15 +//----Write Only-------------- +//ok +#define FPGA_ADDR_DPD_CTRL1 0x20 +#define FPGA_ADDR_DPD_CTRL2 0x21 +#define FPGA_ADDR_DPD_CTRL3 0x22 +//ok +#define FPGA_ADDR_DPD_IQB_UPD 0x23 +#define FPGA_ADDR_DPD_CFG_STEP 0x24 + + +//wpp +#define FPGA_ADDR_WPP_EN_CLR 0x0d +#define FPGA_ADDR_WPP_TH_L 0x0e +#define FPGA_ADDR_WPP_TH_H 0x0f + +#define MASK_WPP_ENABLE (1) +#define MASK_WPP_CLR (1<<1) + + +//#define FPGA_ADDR_DPD_SYNCOFFSET ?? + +#define FPGA_ADDR_DPD_TEST_L 0x02 +#define FPGA_ADDR_DPD_TEST_H 0x03 + +//----Read Only-------------- +#define FPGA_ADDR_DPD_STATUS1 0x01 + +//--------------------------- +#define MASK_RFAGC_DOWN_LIMIT (1<<1) +#define MASK_RFAGC_UP_LIMIT (1<<2) + +#define SPI_BLK_LEN 35//Byte + +enum{ + E_RFAGC_NORMAL=0, + E_RFAGC_DOWN_LIMIT, + E_RFAGC_UP_LIMIT, +}E_AGC_ERR_CODE; + /* + E_RFAGC_POWER_LOW, + E_RFAGC_POWER_HIGH, + */ + +//ok +#define MASK_DPD_ERR (0x0001) +#define MASK_DPD_PWRHIGH (0x0001<<1) +#define MASK_DPD_PWRLOW (0x0001<<2) +#define MASK_DPD_DAGC_TOOHIGH (0x0001<<3) +#define MASK_DPD_DAGC_TOOLOW (0x0001<<4) +#define MASK_DPD_ERR_ABORT (0x0001<<5) +#define MASK_DPD_TRX_SYNC_OK (0x0001<<6) +#define MASK_DPD_SAT_FLG (0x0001<<7) + +//ok +#define DPD_CTRL1_DPD_START (0x0001) +#define DPD_CTRL1_DPD_ALLCLR (0x0001<<1) +#define DPD_CTRL1_ALL_BYPS (0x0001<<2) + +#define DPD_CTRL2_LIN_UPDATE (0x0001) +#define DPD_CTRL2_NONLIN_UPDATE (0x0001<<1) +#define DPD_CTRL2_SET_NONLIN_UDP_MOD(x) (((x)&0x03)<<2) /*01 : POLY; 10: CRST*/ +#define DPD_CTRL2_AMP_CHK (0x0001<<4) +#define DPD_CTRL2_PRL_UPDATE (0x0001<<5) +#define DPD_CTRL2_RXEQ_UPDATE (0x0001<<6) + +#define DPD_CTRL2_POLYESTI_UPDATE (0x0001<<7) + +//ok +#define INTER_DISTORTION_SW_MAX (7) + + +//ok +#define DPD_CTRL3_FAGC_UPDATE (0x0001) +#define DPD_CTRL3_FAGC_SLOWDN (0x0001<<1) +#define DPD_CTRL3_DAGC_UPDATE (0x0001<<2) +#define DPD_CTRL3_DAGC_SLOWDN (0x0001<<3) +#define DPD_CTRL3_DCRM_UPDATE (0x0001<<4) +#define DPD_CTRL3_ROT_UPDATE (0x0001<<5) +#define DPD_CTRL3_SYNC_UPDATE (0x0001<<6) +#define DPD_CTRL3_SYNC_RESTART (0x0001<<7) +//ok +#define DPD_IQB_UPDATE (0x0001) +#define DPD_IQB_BP_MASK (0x0001<<1) +//#define DPD_IQB_SYNC_MASK (0x0001<<2) +#define DPD_SYNC_MODE_MASK (0x0001<<2) + +/* + * Hardware order is exchanged again: logical/silkscreen A -> rf_sel 0, + * logical/silkscreen B -> rf_sel 1. Keep every RF input selection routed + * through this mapping so DPD/FWD/FSSI use the same A/B interpretation. + */ +#define DPD_RF_SEL_HW_A 0U +#define DPD_RF_SEL_HW_B 1U +#define DPD_RF_SEL_VALUE(sel) (((sel) == E_SELECT_B) ? DPD_RF_SEL_HW_B : DPD_RF_SEL_HW_A) +#define DPD_RF_SEL_AFTER (0x0001<<3) + +#define DPD_SET_100M (0x00) +#define DPD_SET_25M (0x01) + +#define SET_DPDFAGC_REFPWR(x) ((x)) +#define DPD_SET_CRST_ADDR_STRUCT_2 ((0x01)<<17) +#define DPD_SET_ERR_TH(x) (((x)&0xffff)) +#define DPD_SET_ERR_CNT_TH(x) (((x)&0xff)<<16) +#define DPD_SET_DGAIN(x) (((x)&0xffff)<<2) +#define DPD_SET_FIX_DLY(x) (0x8000 & ((x)&0x7ff)) +#define DPD_SET_CRST_REFAD(x) ((x)[0] | ((x)[1]<<4) | ((x)[2]<<8) | ((x)[3]<<12) | ((x)[4]<<16) | ((x)[5]<<20)) + +#define DPD_MAX_TX_AMP_SAT 65535 +//#define TX_FREQ_IN_HZ 2550000000 + + +#define DPD_SEG 5 + +#define MASK_DPD_DATA_AREA0_MODE ((1)&0xff) +#define MASK_DPD_DATA_AREA1_MODE ((1<<1)&0xff) +#define MASK_DPD_DATA_AREA2_MODE ((1<<2)&0xff) +#define MASK_DPD_DATA_AREA3_MODE ((1<<3)&0xff) + +//#define MASK_TO_FPGA_WRITE_ENABLE ((1)) +#define MASK_TO_SPI_WR_RD_ENABLE (1) +#define MASK_TO_FPGA_REFRESH_DATA (1<<1) +#define MASK_TO_FPGA_CHECK_CLEAR (1<<2) + +enum{E_CHECK_FOR_RAED=0, E_CHECK_FOR_WIRTE=1}; + +typedef struct{ + u32 area_fpga_w_check; + u32 area_fpga_r_check; + u32 area_imx_w_check; + u32 area_imx_r_check; +}S_CHECK_SUM; + +//-------------------------------------------- + +/*Add Bit Ctrl*/ +typedef struct{ + uint8 iqb_upd:1; + uint8 iqb_bp:1; + uint8 sync_mode:1; /* !! sync_mode 与 re_sel 相反 */ + uint8 rf_sel:1; /* !! sync_mode 与 re_sel 相反 */ +}S_DPD_REG23; + +typedef union +{ + S_DPD_REG23 dpd_bt; + uint8 u8val; +}U_DPDCTL_REG23; +#define TSNR_FIX 3.5*100 + +enum{E_READ=0,E_WRITE=1}; + +typedef enum +{ + DPD_STATE_OK=0, + DPD_STATE_ERR=0x10, + DPD_STATE_POWER_HIGH, + DPD_STATE_POWER_LOW, + DPD_STATE_POWER_TOO_HIGH, + DPD_STATE_POWER_TOO_LOW, + DPD_STATE_ERR_OVER_RANGE, + DPD_STATE_SYNC_OK, + + DPD_READ_CKECK_ERR, + DPD_WRITE_CHECK_ERR, + + DPD_SYNC_TIMEOUT, + DPD_CHECK_WPP_ERR_EXIT_HOLD, + + //... + + DPD_IDLE_ERR=0x30, + + + DPD_PROC_EXIT = 0x99, + DPD_UPDATING, + DPD_SAVE_DATA = 0xAA, + DPD_LOAD_DATA = 0xBB, + DPD_STATUS_UPDATING = 0xff +}E_DPD_STATE; + +typedef enum{ +E_DPD_NSAVE_NFLITER=0x00,//0x00 +E_DPD_NSAVE_FLITER =0x01,//0x01 +E_DPD_SAVE_NFLITER =0x10,//0x10 +E_DPD_SAVE_FLITER =0x11,//0x11 +}E_CTL_DPD;//cttb_para.wh_para.ctl_dpd + + +// +typedef enum +{ + E_LOAD_TO_MCU, + E_LOAD_TO_FPGA, +}E_DPD_CURVE_PROC; + +typedef enum +{ + E_DPD_AREA0=0, + E_DPD_AREA1, + E_DPD_AREA2, + E_DPD_AREA3, + E_DPD_AREA_FIRST_4K, +}E_DPD_CURVE_AREA; + + +typedef struct +{ + uint32 tx_data_iq_i; + uint32 rx_data_iq_i; + uint16 ob_wpp_max_i; + uint16 txaveamp_i; + uint16 txpow_cur_i; + uint16 rx_dgain_i; + uint16 rx_fgain_cw_i; + uint16 dpd_dynamic_gain_i; // 发端算出、传给收端归一化的增益字 (14bit, seg5 0x32/0x33) + uint16 ob_b_pwr_i; // 预失真前功率 (14bit, seg5 0x34/0x35) + uint16 ob_a_pwr_i; // 预失真后功率 (14bit, seg5 0x36/0x37) +}S_DPD_LOG_TYPE; + +void refresh_update_dpd(void *parg,void *parv); +int dpd_curve_proc(uint8 proc_mode); + +void dpd_exit(void); +void dpd_set_clr(void); +uint8 get_fpga_dpd_check(void); +void dpd_boot_run_init(void); +extern void set_dpd_unit_area_auto_inc(uint8 inc_flg); +extern void set_tsnr_update_flg(uint8 up_flg); +extern int update_tsnr_uimd_limd(uint8 rst_flg,uint8* p_phase); +extern uint8 get_tsnr_update_flg(void); +extern void remote_set_dpd_clr(void); +extern uint8 conv_adpc_err_output(uint8 raw_dpd_err); + +extern void clear_dpd_data_file(void); +extern void set_ab_switch(E_AB_SEL ab_val); +extern u32 read_fpga_area_u32_check_sum(u8 check_type); +extern void clear_check_sum(S_CHECK_SUM *parea_check); +extern void calc_area_u32_check_sum(u32 *pcheck, u8 *pbuf, u32 len); +extern void calc_area_check_sum(u8 *pcheck, u8 *pbuf, u32 len); +#endif +