1823 lines
53 KiB
C
Executable File
1823 lines
53 KiB
C
Executable File
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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/*
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#include "FreeRTOS.h"
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#include "task.h"
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#include "i2c_drv.h"
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#include "delay.h"
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#include "type.h"
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#include "lcd_task.h"
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#include "config.h"
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#include "fpga.h"
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#include "eeprom.h"
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#include "i2c_drv.h"
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#include "flash.h"
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#include "os_task.h"
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*/
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#include "../inc/i2c_drv.h"
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#include "../inc/ipara_cfg.h"
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#include "../inc/delay.h"
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#include "../inc/type.h"
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#include "../inc/lcd_task.h"
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#include "../inc/config.h"
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#include "../inc/fpga.h"
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#include "../inc/eeprom.h"
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#include "../inc/os_task.h"
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#include "../inc/dpd_proc.h"
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#include "../inc/tsoip.h"
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#include "../inc/iweb_task.h"
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#include "../inc/msg.h"
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#include "../inc/dac38j82.h"
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#include "../inc/isys_com.h"
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#include "../adrv9009/adrv9009_config.h"
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#include "../inc/adrv9009_ext.h"
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extern uint16 cal_crc_zb(const uint8 *ptr, uint32 len);
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extern void task_is_ok(void);
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uint8 dataBuffer[LEN_ADPC_DATE_BUF+8];
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extern S_ATSC_PARA atsc_para;
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extern uint32 update_flag;
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extern uint8 agc_value[];
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extern int g_restart_app_flg;
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extern int g_rf_boot_done; /* PR10: set after boot RF init done (main.c) */
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extern int g_skip_talise_cfg; /* PR10: 1 = skip 9009 TALISE re-init (adrv9009_config.c) */
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extern void little_balance(S_SYSTEM_PARA * psys);
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extern void reset_dpd_to_normal_state(void);
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extern pthread_mutex_t mtx_phase78910_again;
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#if USE_TUNER
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extern BOOL tuner_flag(void);
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uint32 bak_tuner_freq = (uint32)-1;
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#endif
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extern S_IP2TS_PARA ip2ts[2];
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void adpc_load_data(uint32 cmd,uint32 adpc);
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#if SHOW_DEBUG_INFO
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void uart_debug(uint8 *pbuf,uint32 len)
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{
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uint8 temp[8];
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while(len--)
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{
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temp[0] = temp[1] = 0;
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sprintf((char*)temp,"%02x\n",*pbuf++);
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uart_send_string(temp,strlen((const char*)temp));
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delay_ms(10);
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}
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}
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#endif
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#define RF_FORCE_OFF_DELAY_MS 400
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#define USE_RF_FORCE_OFF 0 //切换CW和TXFREQ时,先关RF
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#if USE_NEW_POWER_CFG
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#define RAW_MAX_OUTPUT_MDB 10000
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#define REF_POWER_UNITS (RF_POWER_ZERO + WE_POWER_ZERO)
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#define PWR_UNIT_TO_MDB 50
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#define HMC472_STEP_MDB 500
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#define HMC472_STEPS_MAX 63
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#define ADRV9009_ATT_BASE 8000
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#define ADRV9009_ATT_MAX 40000
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/*
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* The post-reset measurements were made in V1.0 software mode and established
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* that LCD -11 dB produces 0 dBm at the 563 MHz reference point. Therefore
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* V1.1 needs 11 dB additional attenuation for LCD 0 dB to map to the same
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* physical 0 dBm output.
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*/
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#define V1_1_OUTPUT_GAIN_MDB 11000
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static int32 g_last_total_mdb = -1;
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static uint16 g_last_adrv9009_att = 0xFFFF;
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static volatile uint8 g_adrv9009_ready = 0;
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static int32 hardware_output_gain_mdb(void)
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{
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return atsc_para.system_para.hardware_version == HARDWARE_VERSION_V1_1
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? V1_1_OUTPUT_GAIN_MDB : 0;
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}
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/*
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* Validate a stored power command only after the current channel's WE power
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* has been loaded. A raw attenuation of zero is a valid physical maximum;
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* only a negative raw attenuation proves that the stored db value is beyond
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* the range represented by the new HMC472 + ADRV9009 power model.
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*/
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static uint8 normalize_new_power_rf_db(S_WE_PARA *pwe, S_RF_PARA *prf)
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{
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int32 raw_total_mdb;
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raw_total_mdb = (int32)RAW_MAX_OUTPUT_MDB
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- ((int32)prf->db + (int32)pwe->power - (int32)REF_POWER_UNITS)
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* (int32)PWR_UNIT_TO_MDB;
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raw_total_mdb += hardware_output_gain_mdb();
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if(raw_total_mdb >= 0)
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return 0;
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printf("new power cfg reset invalid rf db: we=%d power=%d db=%d raw_total_mdb=%d\n",
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pwe->power, prf->power, prf->db, raw_total_mdb);
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prf->db = DEFAULT_RF_POWER_DB;
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prf->power = RF_POWER_ZERO;
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return 1;
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}
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#endif
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#if USE_NEW_POWER_CFG
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#define RF_OFF_AGC_ATT HMC472_STEPS_MAX
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#else
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#define RF_OFF_AGC_ATT 0x3f
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#endif
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#define RF_ATT_RESTORE_DELAY_MS 20
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#if USE_DELAYED_RF_ENABLE
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static volatile uint8 g_boot_rf_hold = 0;
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#endif
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static uint32 flash_adpc_write_err = 0;
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uint32 flash_get_err_time(void)
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{
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return flash_adpc_write_err;
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}
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static void fpga_restore_rf_att(S_RF_PARA *prf)
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{
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#if USE_NEW_POWER_CFG
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fpga_save_power(&atsc_para.we_para, prf);
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#else
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cfg_fpga_agc_att(atsc_para.system_para.agc_att);
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#endif
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}
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static void fpga_set_rf_output_with_para(uint8 rf, S_RF_PARA *prf)
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{
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uint8 current_rf;
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rf = rf ? 1 : 0;
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#if USE_DELAYED_RF_ENABLE
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/* Preserve the requested RF state, but never expose init transients. */
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if(g_boot_rf_hold && rf)
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{
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rf = 0;
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}
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#endif
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current_rf = fpga_byte_read(0x01, 0x26) & 0x01;
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if(rf && current_rf)
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{
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/*
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* RF is already exposed at the connector. Re-running the complete
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* enable sequence would first force HMC472 to 31.5 dB and create a
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* visible output-power dip before restoring the requested setting.
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* Keep the path enabled and only refresh its attenuation instead.
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*/
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fpga_restore_rf_att(prf);
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return;
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}
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cfg_fpga_agc_att(RF_OFF_AGC_ATT);
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if(rf)
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{
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#if USE_NEW_POWER_CFG
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/*
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* Keep the ADRV9009 TX path synchronized with the requested RF state.
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* ADRV9009 control failure is reported, but must not override the
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* independently requested state of the physical RF switch.
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*/
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if(g_adrv9009_ready && (adrv9009_set_tx_path_enable(1) != OK))
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{
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log_printf(LOG_ERR, I_SYS_STATUS,
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"ADRV9009 TX enable failed, continue setting RF output ON\n");
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}
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if(g_adrv9009_ready)
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{
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delay_ms(RF_ATT_RESTORE_DELAY_MS);
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}
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#endif
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fpga_byte_write(0x01, 0x26, 1);
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delay_ms(RF_ATT_RESTORE_DELAY_MS);
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fpga_restore_rf_att(prf);
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}
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else
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{
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/* Isolate the RF connector before powering down the internal TX path. */
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fpga_byte_write(0x01, 0x26, 0);
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#if USE_NEW_POWER_CFG
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if(g_adrv9009_ready && (adrv9009_set_tx_path_enable(0) != OK))
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{
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log_printf(LOG_ERR, I_SYS_STATUS,
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"ADRV9009 TX disable failed, physical RF switch is OFF\n");
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}
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#endif
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}
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}
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void fpga_set_rf_output(uint8 rf)
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{
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fpga_set_rf_output_with_para(rf, &atsc_para.rf_para);
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}
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void fpga_boot_rf_hold_begin(void)
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{
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#if USE_DELAYED_RF_ENABLE
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g_boot_rf_hold = 1;
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log_printf(LOG_DEBUG, I_NOUSED, "boot RF hold enabled\n");
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#endif
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}
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void fpga_boot_rf_hold_release(void)
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{
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#if USE_DELAYED_RF_ENABLE
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uint8 requested_rf;
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if(!g_boot_rf_hold)
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{
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return;
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}
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requested_rf = atsc_para.rf_para.rf ? 1 : 0;
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if(requested_rf && RF_BOOT_STABLE_DELAY_MS)
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{
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delay_ms(RF_BOOT_STABLE_DELAY_MS);
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}
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/* Read it again in case web/UART changed the request during the delay. */
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requested_rf = atsc_para.rf_para.rf ? 1 : 0;
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g_boot_rf_hold = 0;
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fpga_set_rf_output_with_para(requested_rf, &atsc_para.rf_para);
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log_printf(LOG_DEBUG, I_NOUSED,
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"boot RF hold released, requested_rf=%d\n", requested_rf);
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#endif
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}
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#if 1//@ALD_UPDATE
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void fpga_save_dest_mac(void)
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{
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#if NO_USE
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struct ip_addr dest_ip;
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struct eth_addr *pmac;
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struct ip_addr *pdstip;
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struct netif *netif;
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int8 arp_ret = 0;
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IP4_ADDR(&dest_ip,
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ip2ts.tsoip_config_para.dest_ip[0],
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ip2ts.tsoip_config_para.dest_ip[1],
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ip2ts.tsoip_config_para.dest_ip[2],
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ip2ts.tsoip_config_para.dest_ip[3]);
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if(ip_addr_ismulticast(&dest_ip))
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{
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tsoip_byte_write(TSOIP_1,FPGA_MAC_DEST1,0XFF);
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tsoip_byte_write(TSOIP_1,FPGA_MAC_DEST2,0XFF);
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tsoip_byte_write(TSOIP_1,FPGA_MAC_DEST3,0XFF);
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tsoip_byte_write(TSOIP_1,FPGA_MAC_DEST4,0XFF);
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tsoip_byte_write(TSOIP_1,FPGA_MAC_DEST5,0XFF);
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tsoip_byte_write(TSOIP_1,FPGA_MAC_DEST6,0XFF);
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return;
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}
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netif = ip_route(&dest_ip);
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if(netif==NULL)
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{
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return;
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}
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arp_ret = etharp_find_addr(netif, &dest_ip, &pmac, &pdstip);
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if(arp_ret==-1)
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{
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return;
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}
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tsoip_byte_write(TSOIP_1,FPGA_MAC_DEST1, pmac->addr[0]);
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tsoip_byte_write(TSOIP_1,FPGA_MAC_DEST2, pmac->addr[1]);
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tsoip_byte_write(TSOIP_1,FPGA_MAC_DEST3, pmac->addr[2]);
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tsoip_byte_write(TSOIP_1,FPGA_MAC_DEST4, pmac->addr[3]);
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tsoip_byte_write(TSOIP_1,FPGA_MAC_DEST5, pmac->addr[4]);
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tsoip_byte_write(TSOIP_1,FPGA_MAC_DEST6, pmac->addr[5]);
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#endif
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}
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void fpga_save_config_tsoip(int tsoip_index,S_TSOIP_CONFIG_PARA *ppara)
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{
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log_printf(LOG_DEBUG,I_NOUSED,"save tsoip %d config to fpga \n", tsoip_index);
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tsoip_index = tsoip_index & 0x01;
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tsoip_byte_write(tsoip_index,FPGA_BROAD_TYPE, ppara->receive_type);
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if(ppara->receive_type == IP2TS_REC_TYPE_MULTI) // 组播
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{
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tsoip_byte_write(tsoip_index,FPGA_IP_ADDR1, ppara->multi_address[0]); //新增,接收TS流用
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tsoip_byte_write(tsoip_index,FPGA_IP_ADDR2, ppara->multi_address[1]);
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tsoip_byte_write(tsoip_index,FPGA_IP_ADDR3, ppara->multi_address[2]);
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tsoip_byte_write(tsoip_index,FPGA_IP_ADDR4, ppara->multi_address[3]);
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}
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else // 单播
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{
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tsoip_byte_write(tsoip_index,FPGA_IP_ADDR1,ppara->ip[0]);
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tsoip_byte_write(tsoip_index,FPGA_IP_ADDR2,ppara->ip[1]);
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tsoip_byte_write(tsoip_index,FPGA_IP_ADDR3,ppara->ip[2]);
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tsoip_byte_write(tsoip_index,FPGA_IP_ADDR4,ppara->ip[3]);
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}
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tsoip_byte_write(tsoip_index,FPGA_REC_PORT_HIGH,ppara->port>>8);
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tsoip_byte_write(tsoip_index,FPGA_REC_PORT_LOW, ppara->port);
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tsoip_byte_write(tsoip_index,FPGA_TS_PACKET_LEN,ppara->packet_len);
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tsoip_byte_write(tsoip_index,FPGA_TS_PACKET_TYPE,ppara->udp_rtp);
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tsoip_byte_write(tsoip_index,FPGA_TS_FEC,ppara->fec);
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tsoip_byte_write(tsoip_index,FPGA_TS_ROW,ppara->row);
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tsoip_byte_write(tsoip_index,FPGA_TS_COL,ppara->col);
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tsoip_byte_write(tsoip_index,FPGA_DELAY_H,ppara->delay>>8);
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tsoip_byte_write(tsoip_index,FPGA_DELAY_L,ppara->delay);
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tsoip_byte_write(tsoip_index,FPGA_IP_DEST1,ppara->dest_ip[0]);
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tsoip_byte_write(tsoip_index,FPGA_IP_DEST2,ppara->dest_ip[1]);
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tsoip_byte_write(tsoip_index,FPGA_IP_DEST3,ppara->dest_ip[2]);
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tsoip_byte_write(tsoip_index,FPGA_IP_DEST4,ppara->dest_ip[3]);
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tsoip_byte_write(tsoip_index,FPGA_MAC_SOURCE1,LOCAL_MAC_FIRST_OCTET);
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tsoip_byte_write(tsoip_index,FPGA_MAC_SOURCE2,LOCAL_MAC_SECOND_OCTET);
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tsoip_byte_write(tsoip_index,FPGA_MAC_SOURCE3,LOCAL_MAC_THIRD_OCTET);
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tsoip_byte_write(tsoip_index,FPGA_MAC_SOURCE4,ppara->mac[0]);
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tsoip_byte_write(tsoip_index,FPGA_MAC_SOURCE5,ppara->mac[1]);
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tsoip_byte_write(tsoip_index,FPGA_MAC_SOURCE6,ppara->mac[2]);
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tsoip_byte_write(tsoip_index,FPGA_PHY_TYPE,ppara->phy_type);
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tsoip_byte_write(tsoip_index,FPGA_DEST_PORT_HIGH,ppara->dest_port>>8);
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tsoip_byte_write(tsoip_index,FPGA_DEST_PORT_LOW, ppara->dest_port);
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tsoip_byte_write(tsoip_index,FPGA_SFN_MFN_SELECT, ppara->sfn_mfn_sel);
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tsoip_byte_write(tsoip_index,FPGA_DEST_LCL_ADDR1,ppara->ip[0]);
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tsoip_byte_write(tsoip_index,FPGA_DEST_LCL_ADDR2,ppara->ip[1]);
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tsoip_byte_write(tsoip_index,FPGA_DEST_LCL_ADDR3,ppara->ip[2]);
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tsoip_byte_write(tsoip_index,FPGA_DEST_LCL_ADDR4,ppara->ip[3]);
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fpga_save_dest_mac();
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if(tsoip_index==TSOIP_1) {
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tsoip_byte_write(tsoip_index, FPGA_IP12_SELECT,ppara->ip12_sel);//h20190221
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log_printf(LOG_DEBUG,I_NOUSED,"TSOIP_%d ip2sel=%d \n", tsoip_index+1, ppara->ip12_sel);
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}
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}
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#endif//
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uint32 rw_e2rom_adpc(uint32 adpc,uint8 kind,uint32 block,uint8 *ptr)
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{
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#if 0//_USE_RVL_
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uint8 *pData = ptr;
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uint32 i = 0;
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uint32 rw_len = 0;
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uint32 e2_address;
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uint32 e2_address2;
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uint32 address = 0;
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uint16 crc = 0;
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uint16 crc_read = 0;
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uint8 *preadbak = NULL;
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uint32 retry_time = 0;
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uint8 cor=0;
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e2_address = EEPROM_ADPC_BEGIN1_ADDR;
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e2_address2= E2_ADPC_BEGIN1_ADDR;
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cor=atsc_para.ad3_para.cor;
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if(kind==RW_ADPC_SAVE)//保存曲线
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{
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if(block==0)
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{
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#if USE_UPDATA5
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if((adpc==ADPC_UPDATE1)||(adpc==ADPC_UPDATE3)||(adpc==ADPC_UPDATE4))
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#else
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if((adpc==ADPC_UPDATE1)||(adpc==ADPC_UPDATE3))
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#endif
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{
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if(cor==0)
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atmel_write_e1(pData,e2_address,64);
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else
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atmel_write_e2(pData,e2_address2,64);
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rw_len = 64;
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}
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#if USE_UPDATA5
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else if((adpc==ADPC_UPDATE2) || (adpc==ADPC_UPDATE5))
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#else
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else if((adpc==ADPC_UPDATE2) || (adpc==ADPC_UPDATE4))
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#endif
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{
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for(i=0;i<16;i++)
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{
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if(cor==0)
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atmel_write_e1(pData+64*i,e2_address+64+64*i,64);
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else
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atmel_write_e2(pData+64*i,e2_address2+64+64*i,64);
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delay_us(200);
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}
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rw_len=64*16;
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}
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}
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else
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{
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i = ((block-1)/FPGA_ADPC_CURRENT_NONLINER_SIZE)*FPGA_ADPC_CURRENT_NONLINER_SIZE*1024; //线性区0占用
|
|
address = i+((block-4)%FPGA_ADPC_CURRENT_NONLINER_SIZE)*1024; //存储时,block第一个为4,第二个为8
|
|
preadbak = (uint8*)alloc_mem(LEN_ADPC_DATE_BUF);
|
|
L_RETRY:
|
|
if(preadbak)
|
|
{
|
|
crc = cal_crc_zb(pData,LEN_ADPC_DATE_BUF);
|
|
}
|
|
flash_write_buf(pData,LEN_ADPC_DATE_BUF,address);
|
|
if(preadbak)
|
|
{
|
|
flash_read_buf(preadbak,LEN_ADPC_DATE_BUF,address);
|
|
crc_read = cal_crc_zb(preadbak,LEN_ADPC_DATE_BUF);
|
|
if(crc_read!=crc)
|
|
{
|
|
flash_adpc_write_err++;
|
|
if(retry_time++<3)
|
|
{
|
|
flash_erase_sector(address,LEN_ADPC_DATE_BUF);
|
|
goto L_RETRY;
|
|
}
|
|
}
|
|
free_mem(preadbak);
|
|
|
|
rw_len = LEN_ADPC_DATE_BUF;
|
|
}
|
|
}
|
|
}
|
|
else if(kind==RW_ADPC_LOAD)//读取曲线
|
|
{
|
|
if(block==0)
|
|
{
|
|
for ( i = 0 ; i <17 ; i++ )
|
|
{
|
|
if(cor==0)
|
|
atmel_read_e1(pData+64*i,e2_address+64*i,64);
|
|
else
|
|
atmel_read_e2(pData+64*i,e2_address2+64*i,64);
|
|
delay_us(200);
|
|
|
|
}
|
|
rw_len = 64*17;
|
|
}
|
|
else
|
|
{
|
|
i = ((block-1)/FPGA_ADPC_CURRENT_NONLINER_SIZE)*FPGA_ADPC_CURRENT_NONLINER_SIZE*1024; //线性区占用0
|
|
address = i+((block-1)%FPGA_ADPC_CURRENT_NONLINER_SIZE)*1024;//存储时,block第一个为1,第二个为5
|
|
|
|
|
|
flash_read_buf(pData,LEN_ADPC_DATE_BUF,address);
|
|
rw_len = LEN_ADPC_DATE_BUF;
|
|
}
|
|
}
|
|
|
|
return rw_len;
|
|
#endif
|
|
}
|
|
|
|
void erase_adpc_data(void)
|
|
{
|
|
#if 1//NEED_TO_EN//@TMP_NOT_USED
|
|
clear_dpd_data_file();
|
|
#endif
|
|
|
|
#if 0//_USE_RVL_
|
|
uint8 *pdata = &dataBuffer[0];
|
|
uint32 e2_address;
|
|
uint8 cor;
|
|
uint32 i;
|
|
|
|
memset(pdata,0,128);
|
|
|
|
cor=atsc_para.ad3_para.cor;
|
|
if(0==cor)
|
|
{
|
|
e2_address = EEPROM_ADPC_BEGIN1_ADDR;
|
|
for(i=0; i<17; i++)
|
|
{
|
|
atmel_write_e1(pdata,e2_address+64*i,64);
|
|
}
|
|
flash_erase_sector(FPGA_ADPC_NONLINER_DATA_ADDRESS, FPGA_ADPC_DATA_NUM*FPGA_ADPC_CURRENT_NONLINER_SIZE*1024);
|
|
}
|
|
else
|
|
{
|
|
e2_address = E2_ADPC_BEGIN1_ADDR;
|
|
for(i=0; i<17; i++)
|
|
{
|
|
|
|
atmel_write_e2(pdata,e2_address+64*i,64);
|
|
}
|
|
flash_erase_sector(E2_FPGA_ADPC_NONLINER_DATA_ADDRESS, FPGA_ADPC_DATA_NUM*FPGA_ADPC_CURRENT_NONLINER_SIZE*1024);
|
|
}
|
|
#endif
|
|
}
|
|
uint32 RdFPGADataCnt = 0;
|
|
static uint8 ReadDataCheckSum(uint8 seg,uint8 addr,uint8 *pOut)
|
|
{
|
|
uint8 Data[4]={0},checksum,Step = 10;
|
|
|
|
while(Step--)
|
|
{
|
|
Data[0] = fpga_byte_read(seg,addr);
|
|
Data[1] = fpga_byte_read(seg,addr+1);
|
|
Data[2] = fpga_byte_read(seg,addr+2);
|
|
Data[3] = fpga_byte_read(seg,addr+3);
|
|
checksum = Data[0]+Data[1]+Data[2];
|
|
if(checksum==Data[3])
|
|
{
|
|
memcpy(pOut,Data,4);
|
|
return 1;
|
|
}
|
|
}
|
|
memset(pOut,0xff,4);
|
|
//RdFPGADataCnt++;
|
|
return 0;
|
|
}
|
|
uint32 rw_fpga_adpc(uint32 adpc,uint8 kind,uint32 block,uint8 *ptr)
|
|
{
|
|
uint8 *pData = ptr;
|
|
uint32 CntByte = 0,CntBlock = 0;
|
|
uint32 len=0;
|
|
|
|
if(kind==RW_ADPC_SAVE)//保存曲线 读 FPGA
|
|
{
|
|
if(block==0)
|
|
{
|
|
#if USE_UPDATA5
|
|
if((adpc==ADPC_UPDATE1)||(adpc==ADPC_UPDATE3)||(adpc==ADPC_UPDATE4))
|
|
#else
|
|
if((adpc==ADPC_UPDATE1)||(adpc==ADPC_UPDATE3))
|
|
#endif
|
|
{
|
|
len = 64;
|
|
for(CntByte=0;CntByte<(64/4);CntByte++)
|
|
{
|
|
if(ReadDataCheckSum(0x7e,0X04+CntByte*4,pData)==0)
|
|
RdFPGADataCnt++;
|
|
pData+=4;
|
|
}
|
|
}
|
|
#if USE_UPDATA5
|
|
else if((adpc==ADPC_UPDATE2) || (adpc==ADPC_UPDATE5))
|
|
#else
|
|
else if((adpc==ADPC_UPDATE2) || (adpc==ADPC_UPDATE4))
|
|
#endif
|
|
{
|
|
len = 62*4*4;
|
|
for(CntByte=0;CntByte<62;CntByte++)
|
|
{
|
|
if(ReadDataCheckSum(0x7b,0X04+CntByte*4,pData)==0)
|
|
RdFPGADataCnt++;
|
|
pData+=4;
|
|
}
|
|
|
|
for(CntByte=0;CntByte<62;CntByte++)
|
|
{
|
|
if(ReadDataCheckSum(0x7c,0X04+CntByte*4,pData)==0)
|
|
RdFPGADataCnt++;
|
|
pData+=4;
|
|
}
|
|
|
|
for(CntByte=0;CntByte< 62;CntByte++)
|
|
{
|
|
if(ReadDataCheckSum(0x7d,0X04+CntByte*4,pData)==0)
|
|
RdFPGADataCnt++;
|
|
pData+=4;
|
|
}
|
|
|
|
for(CntByte=0;CntByte<(62);CntByte++)
|
|
{
|
|
if(ReadDataCheckSum(0x7f,0X04+CntByte*4,pData)==0)
|
|
RdFPGADataCnt++;
|
|
pData+=4;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
len = 8*0x80;
|
|
|
|
for(CntBlock=0;CntBlock<8;CntBlock++)
|
|
{
|
|
for(CntByte=0;CntByte<(0X80/4);CntByte++)
|
|
{
|
|
if(ReadDataCheckSum(0X80+(block-1)*8+CntBlock,0X80+CntByte*4,pData)==0)
|
|
RdFPGADataCnt++;
|
|
pData+=4;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
else if(kind==RW_ADPC_LOAD)//加载曲线 写FPGA
|
|
{
|
|
if(block==0)
|
|
{
|
|
for(CntByte=0;CntByte<64;CntByte++)
|
|
{
|
|
fpga_byte_write(0x7e,0X04+CntByte,*pData++);
|
|
}
|
|
len+=64;
|
|
|
|
for(CntByte=0;CntByte<62*4;CntByte++)
|
|
{
|
|
fpga_byte_write(0x7b,0X04+CntByte,*pData++);
|
|
}
|
|
|
|
for(CntByte=0;CntByte<62*4;CntByte++)
|
|
{
|
|
fpga_byte_write(0x7c,0X04+CntByte,*pData++);
|
|
}
|
|
len += 64*2*4;
|
|
|
|
for(CntByte=0;CntByte< 62*4;CntByte++)
|
|
{
|
|
fpga_byte_write(0x7d,0X04+CntByte,*pData++);
|
|
}
|
|
len += 64*4;
|
|
for(CntByte=0;CntByte<62*4;CntByte++)
|
|
{
|
|
fpga_byte_write(0x7f,0X04+CntByte,*pData++);
|
|
}
|
|
len += 64*4;
|
|
}
|
|
else
|
|
{
|
|
for(CntBlock=0;CntBlock<8;CntBlock++)
|
|
{
|
|
for(CntByte=0X80;CntByte<=0Xff;CntByte++)
|
|
{
|
|
fpga_byte_write(0X80+(block-1)*8+CntBlock,CntByte,*pData++);
|
|
}
|
|
}
|
|
len = 8*0x80;
|
|
}
|
|
}
|
|
return len;
|
|
}
|
|
|
|
static uint8 conv_input_to_fpga(uint8 input)
|
|
{
|
|
uint8 set_input=0;
|
|
|
|
switch(input)
|
|
{
|
|
case ASI_INPUT_TUNER:
|
|
set_input = (1&0x7)<<2;//001
|
|
printf("set tun 0x%x\n",set_input);
|
|
break;
|
|
case ASI_INPUT_TS:
|
|
set_input = (2&0x7)<<2;//010
|
|
printf("set asi 0x%x\n",set_input);
|
|
break;
|
|
case ASI_INPUT_EAS:
|
|
set_input = (3&0x7)<<2;//011
|
|
printf("set eas 0x%x\n",set_input);
|
|
break;
|
|
case TSOIP_INPUT_IP:
|
|
set_input = (0&0x7)<<2;//000
|
|
printf("set tsoip 0x%x\n",set_input);
|
|
break;
|
|
case SMPTE_INPUT:
|
|
set_input = (6&0x7)<<2;//110
|
|
printf("set smpte 0x%x\n",set_input);
|
|
break;//0x18 11000
|
|
default:
|
|
printf("set none 0x%x\n",set_input);
|
|
break;
|
|
}
|
|
|
|
return set_input;
|
|
}
|
|
|
|
void fpga_save_sys(S_SYSTEM_PARA *ppara)
|
|
{
|
|
uint16 hz;
|
|
uint8 data = 0;
|
|
|
|
//data = ((ppara->input+1)&3)<<2;
|
|
data = conv_input_to_fpga(ppara->input);
|
|
fpga_byte_write(0x01,0x50,data);
|
|
|
|
hz = math_abs(ppara->ocxo);
|
|
hz *=OCXO_UNIT;
|
|
if(ppara->ocxo>0) //存储下限为0
|
|
hz = atsc_para.wb_para.hz+hz;
|
|
else
|
|
{
|
|
if(atsc_para.wb_para.hz>hz)
|
|
hz = atsc_para.wb_para.hz-hz;
|
|
else
|
|
hz = 0;
|
|
}
|
|
fpga_byte_write(0x01,0x1e,hz>>8);
|
|
fpga_byte_write(0x01,0x1f,hz);
|
|
|
|
fpga_byte_write(0x01,0x08,ppara->gps);//modiy 0x05->0x08 240221
|
|
//fpga_byte_write(0x01,0x02,ppara->net);
|
|
fpga_byte_write(0x03,0x01,ppara->mode);
|
|
|
|
if(ppara->ctrl==CTRL_REMOTE)
|
|
fpga_byte_write(0x01,0x27,1);
|
|
else
|
|
fpga_byte_write(0x01,0x27,0);
|
|
|
|
#if !USE_NEW_POWER_CFG
|
|
cfg_fpga_agc_att(ppara->agc_att);
|
|
#endif
|
|
}
|
|
void fpga_save_chn(S_RF_PARA *ppara)
|
|
{
|
|
#if USE_RF_FORCE_OFF
|
|
static uint32 freq_bak = (uint32)-1;
|
|
uint32 rf_force_open = 0;
|
|
uint8 sys_rdy;
|
|
uint32 tick_num = 0;
|
|
#endif
|
|
S_WE_PARA *pwe = &atsc_para.we_para;
|
|
|
|
pwe->ch = ppara->txfreq;
|
|
#if USE_RF_FORCE_OFF
|
|
if(atsc_para.rf_para.rf)
|
|
{
|
|
if(freq_bak!=ppara->txfreq)
|
|
{
|
|
if(freq_bak!=(uint32)-1)
|
|
{
|
|
rf_force_open = 1;
|
|
fpga_set_rf_output(0); //先关RF
|
|
tick_num = 1;
|
|
do
|
|
{
|
|
delay_ms(10);
|
|
sys_rdy = fpga_byte_read(0x01,0x26);
|
|
}while((sys_rdy&0x40)&&(tick_num++<300)); //sys_rdy bit6为1代表功率还没降到0, 总延时最大3秒
|
|
delay_ms(RF_FORCE_OFF_DELAY_MS);
|
|
}
|
|
freq_bak = ppara->txfreq;
|
|
}
|
|
}
|
|
#endif
|
|
e2rom_read_leak(ppara->txfreq,pwe);
|
|
fpga_save_we(pwe);
|
|
|
|
#if USE_RF_FORCE_OFF
|
|
if(rf_force_open)
|
|
{
|
|
delay_ms(RF_FORCE_OFF_DELAY_MS);
|
|
fpga_set_rf_output(1);
|
|
}
|
|
#endif
|
|
}
|
|
void fpga_save_agc_vol(void)
|
|
{
|
|
#if 0
|
|
uint8 pwrvref_i_h,pwrvref_i_l,pwrvref_v;
|
|
|
|
atsc_para.wb_para.b2=c256_byteread(EEPROM_WB_ADDR+OFFSET_OF_STRUCT(S_WB_PARA,b2));//0.1dB
|
|
|
|
if(atsc_para.ad3_para.cor==0)
|
|
{
|
|
pwrvref_i_h=c256_byteread(EEPROM_PWRVREF_O_HADDR);
|
|
pwrvref_i_l=c256_byteread(EEPROM_PWRVREF_O_LADDR);
|
|
pwrvref_v=c256_byteread(EEPROM_PWRVREF_VLDO_ADDR);
|
|
}
|
|
else
|
|
{
|
|
pwrvref_i_h=c256_byteread2(E2_PWRVREF_O_HADDR);
|
|
pwrvref_i_l=c256_byteread2(E2_PWRVREF_O_LADDR);
|
|
pwrvref_v=c256_byteread2(E2_PWRVREF_VLDO_ADDR);
|
|
}
|
|
fpga_byte_write(0x01,0x4B,atsc_para.wb_para.b2); //发端功率0.1dB控制字
|
|
fpga_byte_write(0x01,0x48,pwrvref_v&1);
|
|
fpga_byte_write(0x01,0x46,pwrvref_i_h);
|
|
fpga_byte_write(0x01,0x47,pwrvref_i_l);
|
|
#endif
|
|
}
|
|
void fpga_save_rf(S_RF_PARA *ppara)
|
|
{
|
|
fpga_save_chn(ppara); //保存频道和功率信息
|
|
|
|
fpga_byte_write(0x01,0x4c,ppara->hz>>16); //+ -
|
|
fpga_byte_write(0x01,0x4d,ppara->hz>>8);
|
|
fpga_byte_write(0x01,0x4e,ppara->hz);
|
|
|
|
#if USE_DRY_LOOP
|
|
if(atsc_para.fpga_load_wait_flag ==1)
|
|
{ //上电发off
|
|
fpga_set_rf_output(0);
|
|
}
|
|
else
|
|
{
|
|
fpga_set_rf_output_with_para(ppara->rf, ppara);
|
|
}
|
|
atsc_para.fpga_load_wait_flag = 0;
|
|
#else
|
|
fpga_set_rf_output_with_para(ppara->rf, ppara);
|
|
#endif
|
|
|
|
/*if(ppara->agc) //由OFF->ON时发送 判断有效标志
|
|
{
|
|
fpga_save_agc_vol();
|
|
}
|
|
fpga_byte_write(0x01,0x4A,agc_value[ppara->agc]);//agc
|
|
*/
|
|
}
|
|
void fpga_save_network(S_NETWORK_PARA *ppara) //41
|
|
{
|
|
fpga_byte_write(0x01,0x3f,ppara->delay>>16);
|
|
fpga_byte_write(0x01,0x40,ppara->delay>>8);
|
|
fpga_byte_write(0x01,0x41,ppara->delay);
|
|
}
|
|
void fpga_save_mode(S_MODE_PARA *ppara)
|
|
{
|
|
fpga_byte_write(0x3,0x5,ppara->sync);
|
|
|
|
if(atsc_para.system_para.net==0)
|
|
{
|
|
fpga_byte_write(0x3,0x4,ppara->zp1f);
|
|
fpga_byte_write(0x3,0xb,ppara->tcp_c);
|
|
}
|
|
}
|
|
|
|
void fpga_save_latch(S_LATCH_PARA *ppara, S_SYSTEM_PARA *psys)
|
|
{
|
|
#if USE_CTRL_MODE
|
|
if(psys->ctrl==CTRL_REMOTE)
|
|
fpga_byte_write(0x01,0x27,1);
|
|
else
|
|
fpga_byte_write(0x01,0x27,0);
|
|
#endif
|
|
}
|
|
|
|
void fpga_save_ad(S_ADVANCE_PARA *ppara)
|
|
{
|
|
uint8 data = 0;
|
|
|
|
fpga_byte_write(0x1, 0x51, ppara->pcr);
|
|
data = ppara->slow_down ? 1 << 0 : 0;
|
|
data |= ppara->slow_up ? 1 << 1 : 0;
|
|
log_printf(LOG_DEBUG,I_NOUSED,"slow_up slow_down, data=0x%X\n", data);
|
|
fpga_byte_write(0x1, 0x25, data);
|
|
#if ADDR_CONFLICT_DISABLED
|
|
fpga_byte_write(0x6, 0x5, ppara->swrt);
|
|
fpga_byte_write(0x6, 0x6, atsc_para.wh_para.ball);
|
|
log_printf(LOG_DEBUG,I_NOUSED,"swrt=====0x%x\n", ppara->swrt);
|
|
#else
|
|
fpga_byte_write(0x5, 0x5, ppara->swrt);
|
|
fpga_byte_write(0x5, 0x6, atsc_para.wh_para.ball);
|
|
#endif
|
|
|
|
data = (atsc_para.system_para.gps);
|
|
fpga_byte_write(0x01,0x08 ,data);//0x05->0x08
|
|
|
|
//fpga_byte_write(0x05, 0x00, 0x01); //??LQ say: fpga has remove this addr ,case no used
|
|
|
|
fpga_byte_write(0x05, 0x83, ppara->pac&1);
|
|
fpga_byte_write(0x01, 0x65, ppara->pac&1);
|
|
|
|
fpga_byte_write(0x06, 0xAF, ppara->asiout); // FPGA changed : seg5 --> seg6
|
|
}
|
|
|
|
void fpga_save_ad2(S_ADVANCE2_PARA *ppara)
|
|
{
|
|
uint8 data = 0;
|
|
uint32 dly=0;
|
|
|
|
data = ppara->m_ts ?1<<0:0;
|
|
data |=ppara->m_10m ?1<<1:0;
|
|
data |=ppara->m_1pps?1<<2:0;
|
|
|
|
fpga_byte_write(0x1,0x29,data);
|
|
dly = (ppara->m_dly_hh*3600+ppara->m_dly_mm*60+ppara->m_dly_ss-4);
|
|
fpga_byte_write(0x1,0x2a,(dly>>16)&0x7);
|
|
fpga_byte_write(0x1,0x2b,(dly>>8)&0xff);
|
|
fpga_byte_write(0x1,0x2c,(dly)&0xff);
|
|
}
|
|
|
|
void fpga_save_ad3(S_ADVANCE3_PARA *ppara)
|
|
{
|
|
#if USE_RF_FORCE_OFF
|
|
static uint32 cw_bak = (uint32)-1;
|
|
uint32 rf_force_open = 0;
|
|
uint8 sys_rdy;
|
|
uint32 tick_num = 0;
|
|
|
|
if(atsc_para.rf_para.rf) {
|
|
if(cw_bak != ppara->cw) {
|
|
if(cw_bak != (uint32)-1) {
|
|
rf_force_open = 1;
|
|
fpga_set_rf_output(0); //先关RF
|
|
tick_num = 1;
|
|
do {
|
|
delay_ms(10);
|
|
sys_rdy = fpga_byte_read(0x01,0x26);
|
|
}while((sys_rdy&0x40)&&(tick_num++<300)); //sys_rdy bit6为1代表功率还没降到0, 总延时最大3秒
|
|
delay_ms(RF_FORCE_OFF_DELAY_MS);
|
|
}
|
|
cw_bak = ppara->cw;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
fpga_byte_write(0x0,0xfe,ppara->cw<<7); //cW:ON/OFF oc
|
|
|
|
#if USE_RF_FORCE_OFF
|
|
if(rf_force_open) {
|
|
delay_ms(RF_FORCE_OFF_DELAY_MS);
|
|
fpga_set_rf_output(1);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
#if USE_PSTS
|
|
void fpga_save_psts(S_PSTS_PARA *ppara)
|
|
{
|
|
uint8 address;
|
|
uint32 i;
|
|
uint32 j = 0;
|
|
|
|
fpga_byte_write(0x02,0xfb,ppara->ts_ctrl);
|
|
if(ppara->ts_ctrl==PSTS_CTRL_DISABLE)
|
|
{
|
|
//return;
|
|
}
|
|
|
|
fpga_byte_write(0x02,0xf8,ppara->tsid>>8);
|
|
fpga_byte_write(0x02,0xf9,ppara->tsid);
|
|
|
|
if(0)//ppara->index<PSIP_MAX_CHANNLE_NUM)
|
|
{
|
|
address = ppara->index*19;
|
|
for(i=0; i<PSIP_SHT_NAME_LEN-1; i++)
|
|
{
|
|
fpga_byte_write(0x02,address+1+2*i,0);
|
|
fpga_byte_write(0x02,address+2+2*i,ppara->sip_para[ppara->index].sht_name[i]);
|
|
}
|
|
|
|
fpga_byte_write(0x02,address+0x0f,( 0xf0 | ((ppara->sip_para[ppara->index].maj_num>>6)&0x0f)));
|
|
fpga_byte_write(0x02,address+0x10,((ppara->sip_para[ppara->index].maj_num&0x3f)<<2) | (ppara->sip_para[ppara->index].min_num>>8 ));
|
|
fpga_byte_write(0x02,address+0x11,ppara->sip_para[ppara->index].min_num);
|
|
}//每次固定全部channel信息都配置
|
|
else// if(ppara->index==0xff)
|
|
{
|
|
ppara->channel_max = ppara->channel_max>PSIP_MAX_CHANNLE_NUM?PSIP_MAX_CHANNLE_NUM:ppara->channel_max;
|
|
for(j=0;j<ppara->channel_max;j++)
|
|
{
|
|
address = j*19;
|
|
for(i=0; i<PSIP_SHT_NAME_LEN-1; i++)
|
|
{
|
|
fpga_byte_write(0x02,address+1+2*i,0);
|
|
fpga_byte_write(0x02,address+2+2*i,ppara->sip_para[j].sht_name[i]);
|
|
}
|
|
|
|
fpga_byte_write(0x02,address+0x0f,( 0xf0 | ((ppara->sip_para[j].maj_num>>6)&0x0f)));
|
|
fpga_byte_write(0x02,address+0x10,((ppara->sip_para[j].maj_num&0x3f)<<2) | (ppara->sip_para[j].min_num>>8 ));
|
|
fpga_byte_write(0x02,address+0x11,ppara->sip_para[j].min_num);
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
|
|
|
|
void fpga_save_ad4(S_ADVANCE4_PARA *ppara)
|
|
{
|
|
fpga_byte_write(0x5,0x32,ppara->pdt); // need confirm with LQ
|
|
//fpga_byte_write(0x0,0x48,ppara->cfr); // need confirm with LQ
|
|
}
|
|
void fpga_save_wb(S_WB_PARA *ppara)
|
|
{
|
|
uint16 hz;
|
|
|
|
fpga_byte_write(0x01,0x4B,ppara->b2);
|
|
//fpga_byte_write(0x01,0x08,ppara->b8);//delete 0x08
|
|
if(atsc_para.system_para.ocxo>0)
|
|
hz = ppara->hz+math_abs(atsc_para.system_para.ocxo);
|
|
else
|
|
hz = ppara->hz-math_abs(atsc_para.system_para.ocxo);
|
|
fpga_byte_write(0x01,0x1e,hz>>8); //high 8 bit
|
|
fpga_byte_write(0x01,0x1f,hz); //low 8 bit
|
|
fpga_byte_write(0x01,0x63,ppara->gpsc>>8);
|
|
fpga_byte_write(0x01,0x64,ppara->gpsc);
|
|
//fpga_byte_write(0x0,0x48,ppara->cfr);
|
|
}
|
|
void fpga_save_wc(S_WC_PARA *ppara)
|
|
{
|
|
#if ADDR_CONFLICT_DISABLED
|
|
#else
|
|
fpga_byte_write(0x05,0x10,ppara->crg);
|
|
fpga_byte_write(0x05,0x11,ppara->pr);
|
|
fpga_byte_write(0x05,0x12,ppara->ch);
|
|
fpga_byte_write(0x05,0x13,ppara->cl);
|
|
fpga_byte_write(0x05,0x14,ppara->dh);
|
|
fpga_byte_write(0x05,0x15,ppara->dl);
|
|
fpga_byte_write(0x05,0x16,ppara->til);
|
|
fpga_byte_write(0x05,0x17,ppara->tfl);
|
|
fpga_byte_write(0x05,0x18,ppara->tls);
|
|
fpga_byte_write(0x05,0x19,ppara->pg);
|
|
#endif
|
|
}
|
|
void fpga_save_wd(S_WD_PARA *ppara)
|
|
{
|
|
uint16 clip_sqr=0;
|
|
uint16 u16tmp;
|
|
|
|
fpga_byte_write(0x05,0x10,ppara->cfr_work&0x1);
|
|
|
|
fpga_byte_write(0x05,0x11, ppara->cfr_clip&0xff);
|
|
fpga_byte_write(0x05,0x12,(ppara->cfr_clip>>8)&0xff);
|
|
|
|
clip_sqr = (ppara->cfr_clip*ppara->cfr_clip)/65536;
|
|
fpga_byte_write(0x05,0x13, clip_sqr&0xff);
|
|
fpga_byte_write(0x05,0x14,(clip_sqr>>8)&0xff);
|
|
|
|
/*fpga_byte_write(0x05,0x20,ppara->twk);
|
|
fpga_byte_write(0x05,0x21,ppara->pfg);
|
|
fpga_byte_write(0x05,0x22,ppara->pdg);
|
|
fpga_byte_write(0x05,0x23,ppara->feg);
|
|
fpga_byte_write(0x05,0x24,ppara->deg);
|
|
fpga_byte_write(0x05,0x25,ppara->lct);
|
|
fpga_byte_write(0x05,0x26,ppara->sa);
|
|
fpga_byte_write(0x05,0x27,ppara->sb);
|
|
fpga_byte_write(0x05,0x28,ppara->sc);
|
|
fpga_byte_write(0x05,0x29,ppara->sd);*/
|
|
|
|
}
|
|
|
|
uint16 fpga_limit_power_target(S_WE_PARA *pwe, S_RF_PARA *prf, uint16 target_power)
|
|
{
|
|
#if USE_NEW_POWER_CFG
|
|
int32 total_mdb;
|
|
uint32 power_up_steps;
|
|
|
|
if(target_power <= prf->power)
|
|
return target_power;
|
|
|
|
total_mdb = (int32)RAW_MAX_OUTPUT_MDB
|
|
- ((int32)prf->db + (int32)pwe->power - (int32)REF_POWER_UNITS)
|
|
* (int32)PWR_UNIT_TO_MDB;
|
|
total_mdb += hardware_output_gain_mdb();
|
|
|
|
if(total_mdb <= 0)
|
|
return prf->power;
|
|
|
|
power_up_steps = (uint32)total_mdb / PWR_UNIT_TO_MDB;
|
|
if((uint32)(target_power - prf->power) > power_up_steps)
|
|
target_power = (uint16)(prf->power + power_up_steps);
|
|
#else
|
|
(void)pwe;
|
|
(void)prf;
|
|
#endif
|
|
|
|
return target_power;
|
|
}
|
|
|
|
void fpga_save_power(S_WE_PARA *pwe,S_RF_PARA *prf)
|
|
{
|
|
#if USE_NEW_POWER_CFG
|
|
int32 total_mdb = 0;
|
|
uint32 hmc_extra = 0;
|
|
uint8 agc_att_val = 0;
|
|
uint8 adrv9009_first = 0;
|
|
uint16 adrv9009_att_val = 0;
|
|
|
|
if(normalize_new_power_rf_db(pwe, prf))
|
|
e2rom_save_power(prf);
|
|
|
|
total_mdb = (int32)RAW_MAX_OUTPUT_MDB
|
|
- ((int32)prf->db + (int32)pwe->power - (int32)REF_POWER_UNITS)
|
|
* (int32)PWR_UNIT_TO_MDB;
|
|
total_mdb += hardware_output_gain_mdb();
|
|
|
|
if(total_mdb < 0)
|
|
total_mdb = 0;
|
|
|
|
if(total_mdb > (int32)(ADRV9009_ATT_MAX + HMC472_STEPS_MAX * HMC472_STEP_MDB))
|
|
total_mdb = ADRV9009_ATT_MAX + HMC472_STEPS_MAX * HMC472_STEP_MDB;
|
|
|
|
if(total_mdb >= (int32)ADRV9009_ATT_BASE)
|
|
{
|
|
hmc_extra = (uint32)total_mdb - ADRV9009_ATT_BASE;
|
|
agc_att_val = (uint8)(hmc_extra / HMC472_STEP_MDB);
|
|
if(agc_att_val > HMC472_STEPS_MAX)
|
|
agc_att_val = HMC472_STEPS_MAX;
|
|
|
|
/*
|
|
* Keep ADRV9009 near its 8000 mdB optimum while HMC472 has range.
|
|
* Once HMC472 reaches 63, use the remaining ADRV9009 range up to
|
|
* 40000 mdB instead of clipping the combined attenuation at 39500.
|
|
*/
|
|
adrv9009_att_val = (uint16)(total_mdb - agc_att_val * HMC472_STEP_MDB);
|
|
}
|
|
else
|
|
{
|
|
agc_att_val = 0;
|
|
adrv9009_att_val = (uint16)total_mdb;
|
|
}
|
|
|
|
if(prf->rf == 0)
|
|
{
|
|
agc_att_val = RF_OFF_AGC_ATT;
|
|
}
|
|
|
|
/*
|
|
* Use one safe ordering rule for every adjustment, including large
|
|
* changes and HMC472 crossover steps:
|
|
* output power rising (total attenuation falling): ADRV9009 first;
|
|
* output power falling (total attenuation rising): HMC472 first.
|
|
* This keeps every intermediate state at or below the requested/previous
|
|
* output level. Unknown direction (initialization) uses HMC472 first.
|
|
*/
|
|
if(g_adrv9009_ready &&
|
|
(g_last_total_mdb >= 0) &&
|
|
(g_last_adrv9009_att != 0xFFFF) &&
|
|
(total_mdb < g_last_total_mdb) &&
|
|
(adrv9009_att_val != g_last_adrv9009_att))
|
|
{
|
|
cfg_adrv_att(adrv9009_att_val);
|
|
g_last_adrv9009_att = adrv9009_att_val;
|
|
adrv9009_first = 1;
|
|
}
|
|
|
|
cfg_fpga_agc_att(agc_att_val);
|
|
|
|
if(!adrv9009_first && g_adrv9009_ready && (adrv9009_att_val != g_last_adrv9009_att))
|
|
{
|
|
cfg_adrv_att(adrv9009_att_val);
|
|
g_last_adrv9009_att = adrv9009_att_val;
|
|
}
|
|
|
|
g_last_total_mdb = total_mdb;
|
|
printf("[power] hardware=V1.%d offset_mdb=%d\n",
|
|
atsc_para.system_para.hardware_version, hardware_output_gain_mdb());
|
|
|
|
printf("[power] we=%3d db=%3d total_mdb=%5d | agc_att=%d adrv_att=%d\n",
|
|
pwe->power, prf->db, total_mdb, agc_att_val, adrv9009_att_val);
|
|
|
|
fpga_byte_write(0x1,0x20,0xff);
|
|
fpga_byte_write(0x1,0x21,0xff);
|
|
#else
|
|
S_WE_PARA *ppara = pwe;
|
|
static uint32 power_on = 0;
|
|
uint32 UI_temp;
|
|
uint32 UI_power;
|
|
|
|
#if SHOW_DEBUG_INFO
|
|
uint8 powerbuf[20];
|
|
#endif
|
|
|
|
if(ppara->power>=WE_POWER_ZERO)
|
|
{
|
|
if(RF_POWER_DB_MAX>=(ppara->power-WE_POWER_ZERO+prf->db))//65536/46=1424 -200~+100 1424-100=1324
|
|
{
|
|
UI_temp = (ppara->power-WE_POWER_ZERO+prf->db)*46;
|
|
if(power_on==0)
|
|
{
|
|
if(prf->agc!=0)
|
|
{
|
|
UI_power = prf->power;
|
|
if(UI_temp > UI_power)
|
|
UI_temp = UI_power;
|
|
}
|
|
power_on = 1;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
UI_temp = 0xffff;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if(prf->db >= (WE_POWER_ZERO-ppara->power))
|
|
{
|
|
UI_temp = (prf->db - (WE_POWER_ZERO-ppara->power))*46;
|
|
if(power_on==0)
|
|
{
|
|
if(prf->agc!=0)
|
|
{
|
|
UI_power = prf->power;
|
|
if(UI_temp > UI_power)
|
|
UI_temp = UI_power;
|
|
}
|
|
power_on = 1;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
UI_temp = 0;
|
|
}
|
|
}
|
|
|
|
if(0)//(atsc_para.rf_para.agc) //判 AGC
|
|
{
|
|
fpga_byte_write(0x1,0x4A,0); //关AGC
|
|
|
|
fpga_byte_write(0x1,0x20,UI_temp>>8); //high 8 bit
|
|
fpga_byte_write(0x1,0x21,UI_temp); //low 8 bit
|
|
|
|
fpga_byte_write(0x1,0x4A,1); //开AGC
|
|
}
|
|
else
|
|
{
|
|
//printf("set pwr=%d,fpga_pwr=%d\n",ppara->power,UI_temp);
|
|
fpga_byte_write(0x1,0x20,UI_temp>>8); //high 8 bit
|
|
fpga_byte_write(0x1,0x21,UI_temp); //low 8 bit
|
|
}
|
|
#if SHOW_DEBUG_INFO
|
|
lcd_write_string(LINE_2,25," ");
|
|
sprintf((char *)powerbuf, "power:%X ",UI_temp);
|
|
lcd_write_string(LINE_2,25,powerbuf);
|
|
#endif
|
|
//printf("set fpga_pwr=%d db=%d power=%d \n",UI_temp, prf->db, ppara->power);
|
|
#endif
|
|
}
|
|
void fpga_save_we(S_WE_PARA *ppara)
|
|
{
|
|
uint8 temp;
|
|
|
|
const uint8 dis_sp[] = {0,1,3,4,0x0c};
|
|
|
|
fpga_byte_write(0x01,0x01,ppara->ch);
|
|
|
|
fpga_byte_write(0x01,0x0A,ppara->ltn&0xf);
|
|
|
|
temp=(ppara->dsc<<4) | ppara->snc;
|
|
fpga_byte_write(0x01,0x19,temp);
|
|
fpga_byte_write(0x01,0x1C,ppara->dpgh);
|
|
fpga_byte_write(0x01,0x1D,ppara->dpgm);
|
|
fpga_byte_write(0x01,0x09,ppara->dpgl);
|
|
//fpga_byte_write(0x01,0x03,ppara->fsc);
|
|
|
|
if(ppara->sp>4)
|
|
ppara->sp = 0;
|
|
fpga_byte_write(0x01,0x98,dis_sp[ppara->sp]);
|
|
|
|
fpga_save_power(ppara,&atsc_para.rf_para);
|
|
}
|
|
void fpga_save_wf(S_WF_PARA *ppara)
|
|
{
|
|
#if ADDR_CONFLICT_DISABLED
|
|
#else
|
|
|
|
fpga_byte_write(0x05,0x32,ppara->pdt); // 时间
|
|
fpga_byte_write(0x05,0x33,ppara->ah); // AH
|
|
fpga_byte_write(0x05,0x34,ppara->al); // AL
|
|
fpga_byte_write(0x05,0x35,ppara->m); //
|
|
|
|
fpga_byte_write(0x05,0x3b,ppara->th);
|
|
|
|
fpga_byte_write(0x00,0xf5,ppara->sp<<6);
|
|
fpga_byte_write(0x00,0x29,ppara->equc>>8);
|
|
fpga_byte_write(0x00,0x2a,ppara->equc);
|
|
#endif
|
|
}
|
|
void fpga_save_wh(S_WH_PARA *ppara)
|
|
{
|
|
#if ADDR_CONFLICT_DISABLED
|
|
|
|
fpga_byte_write(0x01, 0xf8, ppara->chip&1);
|
|
fpga_byte_write(0x06, 0x05, ppara->balh);
|
|
fpga_byte_write(0x06, 0x06, ppara->ball);
|
|
|
|
|
|
#else
|
|
|
|
fpga_byte_write(0x06,0x02, ppara->bw); // 20220720 seg5 -> seg6 case FPGA changed
|
|
|
|
fpga_byte_write(0x06,0x03, ppara->ralh);
|
|
fpga_byte_write(0x06,0x04, ppara->rall);
|
|
|
|
fpga_byte_write(0x06,0x05, ppara->balh);
|
|
fpga_byte_write(0x06,0x06, ppara->ball);
|
|
|
|
//fpga_byte_write(0x05,0x2a,ppara->pwrt);
|
|
|
|
//fpga_byte_write(0x05,0x83,ppara->pac&1);
|
|
//fpga_byte_write(0x01,0x65,ppara->pac&1);
|
|
#endif
|
|
}
|
|
void fpga_save_wj(S_WJ_PARA *ppara)
|
|
{
|
|
fpga_byte_write(0x01,0x84, ppara->picture);
|
|
}
|
|
void fpga_save_wl(S_WL_PARA *ppara)
|
|
{
|
|
fpga_byte_write(0x01,0x66,ppara->roll_off_sel&0x01);
|
|
fpga_byte_write(0x01,0x4f,ppara->spec_shift&0x01);
|
|
}
|
|
uint16 amp_sat_th2sqr_th(uint16 sat)
|
|
{
|
|
float fdata;
|
|
uint16 retval;
|
|
|
|
fdata = sat/4096.0;
|
|
retval = (uint16)(fdata*fdata*256);
|
|
return retval;
|
|
}
|
|
|
|
void fpga_save_dpd_para(S_DPD_PARA *ppara)
|
|
{
|
|
fpga_byte_write(0x05,0x01,ppara->distortion_sw);
|
|
|
|
fpga_byte_write(0x05,0x02,(ppara->dpd_test&0xff));
|
|
fpga_byte_write(0x05,0x03,(ppara->dpd_test>>8)&0xff);
|
|
|
|
fpga_byte_write(0x05,0x04,(ppara->agc_pwr&0xff));
|
|
fpga_byte_write(0x05,0x05,(ppara->agc_pwr>>8)&0xff);
|
|
|
|
fpga_byte_write(0x05,0x06,(ppara->err_th&0xff));
|
|
fpga_byte_write(0x05,0x07,(ppara->err_th>>8)&0xff);
|
|
|
|
fpga_byte_write(0x05,0x08,(ppara->err_cnt_th));
|
|
|
|
if(ppara->amp_sat>FPGA_AMP_SAT_MAX){
|
|
ppara->amp_sat = FPGA_AMP_SAT_DEF;
|
|
}
|
|
fpga_byte_write(0x05,0x09,(ppara->amp_sat&0xff));
|
|
fpga_byte_write(0x05,0x0a,(ppara->amp_sat>>8)&0xff);
|
|
|
|
ppara->amp_sat_sqr = amp_sat_th2sqr_th(ppara->amp_sat);
|
|
|
|
fpga_byte_write(0x05,0x0b,(ppara->amp_sat_sqr&0xff));
|
|
fpga_byte_write(0x05,0x0c,(ppara->amp_sat_sqr>>8)&0xff);
|
|
|
|
fpga_byte_write(0x05,0x0e,(ppara->wpp_th&0xff));
|
|
fpga_byte_write(0x05,0x0f,(ppara->wpp_th>>8)&0xff);
|
|
|
|
|
|
fpga_byte_write(0x05, 0x2C, (ppara->gl&0xff));
|
|
fpga_byte_write(0x05, 0x2D, (ppara->gl>>8)&0xff);
|
|
|
|
fpga_byte_write(0x05, 0x98, (ppara->dpd_ctl&0xff));
|
|
}
|
|
|
|
volatile uint8 _g_adrv9009_spi_src = E_CTRL_SRC_MCU;
|
|
void cfg_adrv9009_spi_ctrl_source(uint8 ctrl_src)
|
|
{
|
|
fpga_byte_write(0x05,0x58,ctrl_src);
|
|
if(ctrl_src==E_CTRL_SRC_MCU){
|
|
printf("adrv9009_spi ctrl src [mcu]\n");
|
|
delay_ms(100);
|
|
}
|
|
else if(ctrl_src==E_CTRL_SRC_FPGA){
|
|
printf("adrv9009_spi ctrl src [fpga]\n");
|
|
}
|
|
_g_adrv9009_spi_src = ctrl_src;
|
|
}
|
|
void boot_cfg_fagc_update()
|
|
{
|
|
if(_g_adrv9009_spi_src==E_CTRL_SRC_FPGA){
|
|
fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, DPD_CTRL3_FAGC_UPDATE);
|
|
printf("OK, boot_cfg_fagc_update\n");
|
|
}
|
|
else{
|
|
printf("Err, boot_cfg_fagc_update \n");
|
|
}
|
|
}
|
|
|
|
|
|
void fpga_save_all_para(BOOL flag)
|
|
{
|
|
uint8 flash_valid = 0;
|
|
int ret = 0;
|
|
|
|
log_printf(LOG_DEBUG,I_NOUSED,"[fpga_save_all_para]\n");
|
|
if(g_restart_app_flg==0) {
|
|
fpga_byte_write(0x01,0xfe,0x01);
|
|
fpga_byte_write(0x01,0xfe,0x00);
|
|
log_printf(LOG_DEBUG,I_NOUSED,"\n\nsys reset fpga now!\n\n");
|
|
}
|
|
|
|
|
|
fpga_byte_write(0x01,0xff,0x00 ); //配置开始标志
|
|
|
|
fpga_save_sys(&atsc_para.system_para);
|
|
fpga_save_network(&atsc_para.network_para);
|
|
fpga_save_rf(&atsc_para.rf_para);
|
|
|
|
fpga_save_mode(&atsc_para.mode_para);
|
|
fpga_save_ad(&atsc_para.ad_para);
|
|
fpga_save_ad2(&atsc_para.ad2_para);
|
|
fpga_save_ad3(&atsc_para.ad3_para);
|
|
fpga_save_ad4(&atsc_para.ad4_para);
|
|
|
|
#if USE_PSTS
|
|
fpga_save_psts(&atsc_para.psts_para);
|
|
#endif
|
|
|
|
fpga_save_dpd_para(&atsc_para.dpd_para);
|
|
|
|
fpga_save_wb(&atsc_para.wb_para);
|
|
fpga_save_wc(&atsc_para.wc_para);
|
|
fpga_save_wd(&atsc_para.wd_para);
|
|
fpga_save_we(&atsc_para.we_para);
|
|
fpga_save_wf(&atsc_para.wf_para);
|
|
fpga_save_wh(&atsc_para.wh_para);
|
|
fpga_save_wj(&atsc_para.wj_para);
|
|
fpga_save_wl(&atsc_para.wl_para);
|
|
fpga_byte_write(0x1,0xfe,0x5a);
|
|
|
|
fpga_byte_write(0x1,0xff,0x5a); //配置结束标志
|
|
|
|
delay_ms(10);//sleep(4);//delay_ms(10);
|
|
#if USE_TUNER
|
|
printf("\n\ntuner init start >>> \n");
|
|
if(bak_tuner_freq!=atsc_para.rf_para.rxfreq)
|
|
{
|
|
tuner_init(atsc_para.rf_para.rxfreq);
|
|
bak_tuner_freq=atsc_para.rf_para.rxfreq;
|
|
}
|
|
printf("\ntuner init end <<< \n\n");
|
|
#endif
|
|
|
|
if(flag)
|
|
{
|
|
#if 1//NEED_TO_EN
|
|
flash_valid = c256_byteread(EEPROM_DPD_FLASH_VALID);
|
|
|
|
if(atsc_para.system_para.adpc == ADPC_HOLD){
|
|
if(flash_valid){
|
|
ret = dpd_curve_proc(E_LOAD_TO_FPGA);
|
|
if(ret!=0){
|
|
atsc_para.system_para.adpc = ADPC_OFF;
|
|
c256_bytewrite(EEPROM_DPD_ADDR, atsc_para.system_para.adpc);
|
|
}
|
|
}
|
|
}
|
|
else if(atsc_para.system_para.adpc == ADPC_OFF){//OFF
|
|
fpga_byte_write(0x05,FPGA_ADDR_DPD_CTRL1,DPD_CTRL1_ALL_BYPS);
|
|
|
|
fpga_byte_write(0x05,0x04,(atsc_para.dpd_para.agc_pwr&0xff));
|
|
fpga_byte_write(0x05,0x05,(atsc_para.dpd_para.agc_pwr>>8)&0xff);
|
|
|
|
log_printf(LOG_DEBUG,I_NOUSED,"set dpd bypass\n");
|
|
}
|
|
#endif
|
|
}
|
|
|
|
enter_menu(1);
|
|
|
|
/*
|
|
当系统守护进程启动的时候 g_restart_app_flg 为1, 不会重新配置38j82. 然后恢复g_restart_app_flg=0.
|
|
若 LCD/网页/串口/udp/tcp 协议,再进此函数 会保证能执行38j82 */
|
|
log_printf(LOG_DEBUG,I_NOUSED,"g_restart_app_flg=%d\n", g_restart_app_flg);
|
|
|
|
if(g_restart_app_flg==0) {
|
|
//cfg_dac38j82(atsc_para.rf_para.txfreq, atsc_para.ad3_para.cw);
|
|
|
|
cfg_adrv9009_spi_ctrl_source(E_CTRL_SRC_MCU);
|
|
printf("get txfreq ch=%d\n", atsc_para.rf_para.txfreq);
|
|
adrv9009_init();
|
|
|
|
uint8 data =fpga_byte_read(0x01,0xBB);
|
|
printf("1.rd reg0xBB data=0x%x\n", data);
|
|
|
|
data =fpga_byte_read(0x01,0xB4);
|
|
printf("2.rd reg0xB4 data=0x%x\n", data);
|
|
|
|
cfg_adrv_orx_manu_gain(atsc_para.system_para.orx_manu_gain);
|
|
#if USE_NEW_POWER_CFG
|
|
g_adrv9009_ready = 1;
|
|
g_last_total_mdb = -1;
|
|
g_last_adrv9009_att = 0xFFFF;
|
|
fpga_save_power(&atsc_para.we_para, &atsc_para.rf_para);
|
|
#else
|
|
cfg_adrv_att(atsc_para.system_para.adrv9009_att);
|
|
#endif
|
|
cfg_adrv9009_spi_ctrl_source(E_CTRL_SRC_FPGA);
|
|
|
|
data =fpga_byte_read(0x01,0xBB);
|
|
printf("2.rd reg0xBB data=0x%x\n", data);
|
|
|
|
data =fpga_byte_read(0x01,0xB4);
|
|
printf("2.rd reg0xB4 data=0x%x\n", data);
|
|
|
|
sleep(1);
|
|
}
|
|
g_restart_app_flg = 0;
|
|
|
|
/* PR10: mark the FPGA "config valid" flag (seg5 0x60 = 1). It is cleared to 0 ONLY when the
|
|
* FPGA bitstream (re)loads (GSR at config/IPROG/power-on), so a later read of 0 tells imx6
|
|
* the FPGA was reloaded and needs a re-config + JESD relink (see imx_up_thr poll). */
|
|
fpga_byte_write(0x05, 0x60, 0x01);
|
|
g_rf_boot_done = 1;
|
|
}
|
|
|
|
/* PR10: read the FPGA config-valid flag (seg5 0x60). Returns 1 if the FPGA is still
|
|
* configured by us, 0 if the FPGA bitstream has (re)loaded since we last set it. */
|
|
int fpga_read_cfg_valid(void)
|
|
{
|
|
return (fpga_byte_read(0x05, 0x60) & 0x01);
|
|
}
|
|
|
|
void fpga_write_adpc(uint32 adpc)
|
|
{
|
|
#if NEED_TO_EN//@TMP_UNUSED_FOR_MAKE func no need
|
|
S_WF_PARA *ppara = &atsc_para.wf_para;
|
|
|
|
switch(adpc) // 0:on&hold 1:on&update1 2:off 3: on&update2
|
|
{
|
|
case ADPC_HOLD:
|
|
fpga_byte_write(0x5,0x31,0x00);
|
|
adpc_load_data(1,ADPC_HOLD);
|
|
break;
|
|
case ADPC_UPDATE1: //on&update1
|
|
#if USE_UPDATA5
|
|
fpga_byte_write(0x5,0x3c,0x1);//最低bit用于确定updata开始
|
|
fpga_byte_write(0x5,0x3c,0);
|
|
case ADPC_UPDATE4:
|
|
#endif
|
|
fpga_byte_write(0x5,0x31,0);
|
|
fpga_byte_write(0x5,0x32,ppara->pdt); // 时间
|
|
fpga_byte_write(0x5,0x33,ppara->ah); // AH
|
|
fpga_byte_write(0x5,0x34,ppara->al); // AL
|
|
fpga_byte_write(0x5,0x35,ppara->m); //
|
|
|
|
if(atsc_para.ad5_para.use_dpd==1) //NEW
|
|
fpga_byte_write(0x5,0x30,0x03);
|
|
else
|
|
fpga_byte_write(0x5,0x30,0x03|(0x03<<5));
|
|
break;
|
|
case ADPC_UPDATE2: //on&update2
|
|
#if USE_UPDATA5
|
|
case ADPC_UPDATE5:
|
|
#else
|
|
case ADPC_UPDATE4:
|
|
#endif
|
|
fpga_byte_write(0x5,0x31,0);
|
|
|
|
fpga_byte_write(0x5,0x32,ppara->pdt); // 时间
|
|
fpga_byte_write(0x5,0x33,ppara->ah); // AH
|
|
fpga_byte_write(0x5,0x34,ppara->al); // AL
|
|
fpga_byte_write(0x5,0x35,ppara->m); //
|
|
|
|
if(atsc_para.ad5_para.use_dpd==1) //NEW
|
|
fpga_byte_write(0x5,0x30,0x81);
|
|
else
|
|
fpga_byte_write(0x5,0x30,0x81|(0x03<<5));
|
|
break;
|
|
case ADPC_UPDATE3:
|
|
fpga_byte_write(0x5,0x31,0);
|
|
|
|
fpga_byte_write(0x5,0x32,ppara->pdt); // 时间
|
|
fpga_byte_write(0x5,0x33,ppara->ah); // AH
|
|
fpga_byte_write(0x5,0x34,ppara->al); // AL
|
|
fpga_byte_write(0x5,0x35,ppara->m); //
|
|
|
|
if(atsc_para.ad5_para.use_dpd==1) //NEW
|
|
fpga_byte_write(0x5,0x30,0x07);
|
|
else
|
|
fpga_byte_write(0x5,0x30,0x07|(0x03<<5));
|
|
break;
|
|
case ADPC_OFF : //off
|
|
fpga_byte_write(0x5,0x30,0x00);//
|
|
fpga_byte_write(0x5,0x31,0x07);// 启动预校正
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
#endif//@TMP_UNUSED_FOR_MAKE
|
|
}
|
|
void adpc_load_data(uint32 cmd,uint32 adpc)
|
|
{
|
|
#if 0//_USE_RVL_
|
|
|
|
uint32 j=0;
|
|
uint32 Num = 0;
|
|
uint8 temp_buf[20];
|
|
uint32 len = 0;
|
|
#if USE_SPI_FLASH
|
|
uint32 i = 0;
|
|
uint32 block_offset = 0;
|
|
#endif
|
|
uint8 bak_adpc_err=0;
|
|
uint8 cor=0;
|
|
|
|
(void)len;
|
|
RdFPGADataCnt = 0;
|
|
update_flag = 1;
|
|
|
|
task_stop_sec_msg();
|
|
|
|
cor=atsc_para.ad3_para.cor;
|
|
|
|
if(cmd==RW_ADPC_SAVE)//FPGA TO MCU
|
|
{
|
|
lcd_write_string(0,0," WAIT A MOMENT .... ");
|
|
lcd_write_string(1,0," SAVING DATA ");
|
|
lcd_write_cache();
|
|
|
|
bak_adpc_err = atsc_para.system_para.adpc_err;
|
|
atsc_para.system_para.adpc_err = STATUS_SAVE_DATE;
|
|
fpga_byte_write(0x05,0x30,0x08);
|
|
#if USE_UPDATA5
|
|
if((adpc==ADPC_UPDATE1) || (adpc==ADPC_UPDATE4))
|
|
#else
|
|
if((adpc==ADPC_UPDATE1))
|
|
#endif
|
|
{
|
|
rw_fpga_adpc(adpc,RW_ADPC_SAVE,0,dataBuffer);
|
|
rw_e2rom_adpc(adpc,RW_ADPC_SAVE,0,dataBuffer);
|
|
}
|
|
#if USE_UPDATA5
|
|
else if((adpc==ADPC_UPDATE2) || (adpc==ADPC_UPDATE5))
|
|
#else
|
|
else if((adpc==ADPC_UPDATE2) || (adpc==ADPC_UPDATE4))
|
|
#endif
|
|
{
|
|
len = rw_fpga_adpc(adpc,RW_ADPC_SAVE,0,dataBuffer);
|
|
rw_e2rom_adpc(adpc,RW_ADPC_SAVE,0,dataBuffer);
|
|
}
|
|
else if(adpc==ADPC_UPDATE3)
|
|
{
|
|
rw_fpga_adpc(adpc,RW_ADPC_SAVE,0,dataBuffer);
|
|
rw_e2rom_adpc(adpc,RW_ADPC_SAVE,0,dataBuffer); //线性区
|
|
|
|
if(cor==0)
|
|
flash_erase_sector(FPGA_ADPC_NONLINER_DATA_ADDRESS, FPGA_ADPC_DATA_NUM*FPGA_ADPC_CURRENT_NONLINER_SIZE*1024); //保存前先全部擦除
|
|
else
|
|
flash_erase_sector(E2_FPGA_ADPC_NONLINER_DATA_ADDRESS, FPGA_ADPC_DATA_NUM*FPGA_ADPC_CURRENT_NONLINER_SIZE*1024); //保存前先全部擦除
|
|
|
|
for(i=0;i<FPGA_ADPC_DATA_NUM;i++)
|
|
{
|
|
fpga_byte_write(0x05,0x0C,i); //由此决定FPGA当前使用的曲线
|
|
|
|
//UPDATE3非线性区,一条曲线16k
|
|
block_offset = FPGA_ADPC_CURRENT_NONLINER_SIZE*i;
|
|
for(j=0;j<FPGA_ADPC_CURRENT_NONLINER_SIZE;j++)
|
|
{
|
|
//task_is_ok();
|
|
Num=100*(block_offset+j)/(FPGA_ADPC_CURRENT_NONLINER_SIZE*FPGA_ADPC_DATA_NUM);
|
|
sprintf((char *)temp_buf,"%02d%% ",Num);
|
|
lcd_write_string(1,15,(uint8*)temp_buf);
|
|
lcd_write_cache();
|
|
rw_fpga_adpc(adpc,RW_ADPC_SAVE,1+j,&dataBuffer[1024*(j%4)]);
|
|
|
|
|
|
if((j%4)==3) //4k写一次
|
|
{
|
|
if(cor==0)
|
|
rw_e2rom_adpc(adpc,RW_ADPC_SAVE,1+j+block_offset,dataBuffer);
|
|
else
|
|
rw_e2rom_adpc(adpc,RW_ADPC_SAVE,1+j+block_offset+FPGA_ADPC_CURRENT_NONLINER_SIZE*FPGA_ADPC_DATA_NUM,dataBuffer);
|
|
}
|
|
delay_ticks(1); //不能是task_delay/delay_ms
|
|
}
|
|
}
|
|
}
|
|
}
|
|
else if(cmd==RW_ADPC_LOAD) //MCU TO FPGA
|
|
{
|
|
lcd_write_string(0,0," WAIT A MOMENT .... ");
|
|
lcd_write_string(1,0," LOADING DATA ");
|
|
lcd_write_cache();
|
|
|
|
atsc_para.system_para.adpc= ADPC_HOLD;
|
|
bak_adpc_err = atsc_para.system_para.adpc_err;
|
|
atsc_para.system_para.adpc_err = STATUS_LOAD_DATE;
|
|
fpga_byte_write(0x05,0x30,0x10);
|
|
|
|
rw_e2rom_adpc(adpc,RW_ADPC_LOAD,0,dataBuffer);
|
|
rw_fpga_adpc(adpc,RW_ADPC_LOAD,0,dataBuffer); //线性区
|
|
|
|
//非线性区
|
|
for(i=0;i<FPGA_ADPC_DATA_NUM;i++)
|
|
{
|
|
fpga_byte_write(0x05,0x0c,i);
|
|
|
|
block_offset = FPGA_ADPC_CURRENT_NONLINER_SIZE*i;
|
|
for(j=0;j<FPGA_ADPC_CURRENT_NONLINER_SIZE;j++)
|
|
{
|
|
//task_is_ok();
|
|
Num=100*(block_offset+j)/(FPGA_ADPC_CURRENT_NONLINER_SIZE*FPGA_ADPC_DATA_NUM);
|
|
sprintf((char*)temp_buf,"%02d%% ",Num);
|
|
lcd_write_string(1,15,(uint8*)temp_buf);
|
|
lcd_write_cache();
|
|
|
|
if((j%4)==0)
|
|
{
|
|
if(cor==0)
|
|
rw_e2rom_adpc(adpc,RW_ADPC_LOAD,1+j+block_offset,dataBuffer);
|
|
else
|
|
rw_e2rom_adpc(adpc,RW_ADPC_LOAD,1+j+block_offset+FPGA_ADPC_CURRENT_NONLINER_SIZE*FPGA_ADPC_DATA_NUM,dataBuffer);
|
|
}
|
|
rw_fpga_adpc(adpc,RW_ADPC_LOAD,1+j,&dataBuffer[1024*(j%4)]);
|
|
delay_ticks(1); //不能是task_delay/delay_ms 因为外部已经调用过task_stop_sec_msg/task_resume_sec_msg
|
|
}
|
|
}
|
|
}
|
|
|
|
fpga_byte_write(0x05,0x30,0x00);
|
|
atsc_para.system_para.adpc_err = bak_adpc_err;
|
|
|
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update_flag = 0;
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task_resume_sec_msg();
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#endif
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}
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|
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void config_fpga_para(void)
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{
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config_fpga_soft(STANDARD_ATSC);
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|
|
|
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//check_fpga_i2c();
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|
|
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fpga_save_all_para(TRUE);
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|
|
|
/* TSOIP settings have already been restored by e2rom_read_all_para().
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* Do not load defaults here: that routine also writes the defaults back to
|
|
* EEPROM and would erase the values set from the web page on every reboot. */
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|
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tsoip_byte_write(TSOIP_1, I2C_REG_ADDRES, 0x11);
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delay_ms(200);//delay_ms(6000);
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|
fpga_save_config_tsoip(TSOIP_1, &ip2ts[TSOIP_1].tsoip_config_para);
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tsoip_byte_write(TSOIP_1, 0xff, 0x5a); //配置完成后发5a,fpga开始重启运行
|
|
|
|
// TSOIP_2 (U2/ETH2) — also configure for TSoIP unicast so whichever port carries the stream locks (PR03)
|
|
tsoip_byte_write(TSOIP_2, I2C_REG_ADDRES, 0x11);
|
|
delay_ms(200);
|
|
fpga_save_config_tsoip(TSOIP_2, &ip2ts[TSOIP_2].tsoip_config_para);
|
|
tsoip_byte_write(TSOIP_2, 0xff, 0x5a);
|
|
}
|
|
|
|
void boot_reset_for_test(void)
|
|
{
|
|
S_DPD_PARA *ppara = &atsc_para.dpd_para;
|
|
|
|
atsc_para.dpd_para.wpp_th =65535;
|
|
atsc_para.dpd_para.err_th =65535;
|
|
atsc_para.dpd_para.amp_sat =65535;
|
|
|
|
fpga_byte_write(0x05,0x06,(ppara->err_th&0xff));
|
|
fpga_byte_write(0x05,0x07,(ppara->err_th>>8)&0xff);
|
|
|
|
|
|
/*if(ppara->amp_sat>FPGA_AMP_SAT_MAX){
|
|
ppara->amp_sat = FPGA_AMP_SAT_DEF;
|
|
}*/
|
|
fpga_byte_write(0x05,0x09,(ppara->amp_sat&0xff));
|
|
fpga_byte_write(0x05,0x0a,(ppara->amp_sat>>8)&0xff);
|
|
|
|
ppara->amp_sat_sqr = amp_sat_th2sqr_th(ppara->amp_sat);
|
|
|
|
fpga_byte_write(0x05,0x0b,(ppara->amp_sat_sqr&0xff));
|
|
fpga_byte_write(0x05,0x0c,(ppara->amp_sat_sqr>>8)&0xff);
|
|
|
|
fpga_byte_write(0x05,0x0e,(ppara->wpp_th&0xff));
|
|
fpga_byte_write(0x05,0x0f,(ppara->wpp_th>>8)&0xff);
|
|
}
|
|
|
|
void fpga_read_system(S_SYSTEM_PARA *ppara)
|
|
{
|
|
uint8 u8data = 0;
|
|
if(ppara == NULL)
|
|
return;
|
|
|
|
u8data = fpga_byte_read(0x01, 0xF3); // bit0 :testmode bit1:localremote
|
|
u8data = (u8data==0xff)? 0x00:u8data;
|
|
|
|
ppara->test = u8data & 0x01;
|
|
|
|
return;
|
|
}
|
|
|
|
|
|
#define CONFIG_FPGA_SOFT_DELAY 5000 //配置运行代码后,延时时间 单位MS
|
|
|
|
void config_fpga_soft(uint32 app)
|
|
{
|
|
fpga_reset_save_segment();
|
|
if(app==STANDARD_ATSC)
|
|
{
|
|
fpga_byte_write(0x01,FPGA_UPGRADE_I2C_REG_ADDRES,0x11); //切换到APP1
|
|
}
|
|
else
|
|
{
|
|
fpga_byte_write(0x01,FPGA_UPGRADE_I2C_REG_ADDRES,0x12); //切换到APP2
|
|
}
|
|
|
|
delay_ms(200);//delay_ms(CONFIG_FPGA_SOFT_DELAY);
|
|
fpga_reset_save_segment();
|
|
}
|
|
|
|
/*******************************************END*******************************************/
|