提交SMOD ATSC IMX APP版本 V122
This commit is contained in:
Executable
+3468
File diff suppressed because it is too large
Load Diff
Executable
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#ifndef _AD9009_FUN_H_
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#define _AD9009_FUN_H_
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#define PROJECT_VER "HJX_ADRV9009_X2"
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#define AD9009_VERSION_X "1"
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#define AD9009_VERSION_Y "0"
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#define AD9009_VERSION_Z "0"
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typedef const struct
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{
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const char *cmd; /* command name user types , ie. */
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int32_t min_args; /* min num of args command accepts */
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int32_t max_args; /* max num of args command accepts */
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int32_t (*func)(int32_t, char **); /* actual function to call */
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const char *description; /* brief description of command */
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const char *syntax; /* syntax of command */
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}AD9009_CMD_STRUCT;
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//int ad9009_main(void);
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int ad9009_main(int argc,char *argv[]);
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int ad9009_ver_print(int argc,char *argv[]);
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int ad9009_help(int32_t argc, char *argv[]);
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int ad9009_api_ver_print(int argc,char *argv[]);
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int ad9009_rd(int argc, char *argv[]);
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int ad9009_wr(int argc, char *argv[]);
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int ad9009_TALISE_init(int argc, char *argv[]);
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//int TALISE_initClocks(int argc, char *argv[]);
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int ad9009_TALISE_setRfPllFreq(int argc, char *argv[]);
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int ad9009_TALISE_getRfPllFreq(int argc, char *argv[]);
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int ad9009_TALISE_checkRfPllLock(int argc, char *argv[]);
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//int TALISE_initArmMcu(int argc, char *argv[]);
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//int TALISE_loadArm(int argc, char *argv[]);
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int ad9009_TALISE_chkArmState(int argc, char *argv[]);
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int ad9009_TALISE_gtArmVersion(int argc, char *argv[]);
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int ad9009_TALISE_rstExtTxLolChannel(int argc, char *argv[]);
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int ad9009_TALISE_radioSwitch(int argc, char *argv[]);
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int ad9009_TALISE_getRadioStatus(int argc, char *argv[]);
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int ad9009_TALISE_enTrackingCals(int argc, char *argv[]);
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int ad9009_TALISE_rescheduleTrkingCal(int argc, char *argv[]);
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int ad9009_TALISE_getPdingTrackingCals(int argc, char *argv[]);
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int ad9009_TALISE_gtTxLolStatus(int argc, char *argv[]);
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int ad9009_TALISE_gtTxQecStatus(int argc, char *argv[]);
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int ad9009_TALISE_gtRxQecStatus(int argc, char *argv[]);
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int ad9009_TALISE_gtOrxQecStatus(int argc, char *argv[]);
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int ad9009_TALISE_rdArmCmdStatus(int argc, char *argv[]);
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int ad9009_TALISE_stupSerializers(int argc, char *argv[]);
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int ad9009_TALISE_stupDeserializers(int argc, char *argv[]);
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int ad9009_TALISE_enbleMultichipSync(int argc, char *argv[]);
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int ad9009_TALISE_gtDeframerFifoDepth(int argc, char *argv[]);
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int ad9009_TALISE_enGainCtrSyncPulse(int argc, char *argv[]);
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int ad9009_TALISE_stGainControlMode(int argc, char *argv[]);
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int ad9009_TALISE_gtObsRxPath(int argc, char *argv[]);
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int ad9009_TALISE_stArmGpioPins(int argc, char *argv[]);
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int ad9009_TALISE_stRadioControlPinMode(int argc, char *argv[]);
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int ad9009_TALISE_setSnifferCh(int argc, char *argv[]);
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int ad9009_TALISE_rstDeframer(int argc, char *argv[]);
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int ad9009_TALISE_setupJesd204b(int argc, char *argv[]);
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int ad9009_TALISE_enableLink(int argc, char *argv[]);
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int ad9009_TALISE_enableSysref(int argc, char *argv[]);
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int ad9009_TALISE_read_framerStatus(int argc, char *argv[]);
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int ad9009_TALISE_enFramerPrbs(int argc, char *argv[]);
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int ad9009_TALISE_enTestFramerPrbsData(int argc, char *argv[]);
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int ad9009_TALISE_enDeFramerPrbs(int argc, char *argv[]);
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int ad9009_TALISE_InjectPrbsError(int argc, char *argv[]);
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int ad9009_TALISE_clrDeframerPrbsCounters(int argc, char *argv[]);
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int ad9009_TALISE_rdDeframerPrbsCounters(int argc, char *argv[]);
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int ad9009_TALISE_setFramerDataSource(int argc, char *argv[]);
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int ad9009_TALISE_setRxManualGain(int argc, char *argv[]);
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int ad9009_TALISE_getRxGain(int argc, char *argv[]);
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int ad9009_TALISE_setTxAttenuation(int argc, char *argv[]);
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int ad9009_TALISE_getTxAttenuation(int argc, char *argv[]);
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int ad9009_TALISE_readDacPower(int argc, char *argv[]);
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int ad9009_TALISE_enTxNco(int argc, char *argv[]);
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int ad9009_TALISE_setObsRxPath(int argc, char *argv[]);
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int ad9009_TALISE_IlasCheck(int argc, char *argv[]);
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int ad9009_TALISE_setupAdc(int argc, char *argv[]);
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int ad9009_TALISE_setAdcChannel(int argc, char *argv[]);
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int ad9009_TALISE_readAdc(int argc, char *argv[]);
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int ad9009_TALISE_setRfPllFreq_cals(int argc, char *argv[]);
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//int TALISE_wrAuxIo(int argc, char *argv[]);
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//int TALISE_setupAuxDac(int argc, char *argv[]);
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int ad9009_TALISE_wrAuxDac(int argc, char *argv[]);
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int ad9009_TALISE_enable_extlol(int argc, char *argv[]);
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int ad9009_enable_extlol(void);
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int ad9009_TALISE_stRx1GainCtrlPin(int argc, char *argv[]);
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int ad9009_TALISE_stRx2GainCtrlPin(int argc, char *argv[]);
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int ad9009_TALISE_setObsGainControlMode(int argc, char *argv[]);
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int ad9009_TALISE_setObsManualGain(int argc, char *argv[]);
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int ad9009_TALISE_resetObsManualGain(int ch);
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int ad9009_TALISE_getObsRxGainValue(int argc, char *argv[]);
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int ad9009_TALISE_enable_extlol_rmOff(int argc, char *argv[]);
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int ad9009_TALISE_enable_extlol_justTrack(int argc, char *argv[]);
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int ad9009_TALISE_runInitCalsManual(int argc, char *argv[]);
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int ad9009_TALISE_getRxDecPower(int argc, char *argv[]);
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int ad9009_TALISE_getTrackingCals(int argc, char *argv[]);
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int ad9009_TALISE_configAd9370(int argc, char *argv[]);
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int ad9009_TALISE_getTempStatus(int argc, char *argv[]);
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int ad9009_TALISE_setTrackCal(int argc, char *argv[]);
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int ad9009_TALISE_getTrackCal(int argc, char *argv[]);
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int ad9009_TALISE_Ext_LOL_Cal_2(int argc, char *argv[]);
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int ad9009_TALISE_Ext_LOL_Cal_1(int argc, char *argv[]);
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int ad9009_TALISE_setRfPllFreq_1(int argc, char *argv[]);
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int ad9009_TALISE_runInitCalsManual_1(int argc, char *argv[]);
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int ad9009_TALISE_Test(int argc, char *argv[]);
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int ad9009_tx1_initTxAttenuation(uint16_t att);
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int ad9009_set_rf_pll_freq( unsigned int channel ,uint64_t freqValue);
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int usr_set_ad9009_tx1_TxAttenuation(uint16_t att);
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int usr_get_ad9009_tx1_getTxAttenuation(void);
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int usr_set_ad9009_TxAttenuation(uint16_t att,uint8_t channel);
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int usr_get_ad9009_getTxAttenuation(uint8_t channel);
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int usr_set_ad9009_RxGain(uint8_t gainIndex, uint8_t channel);
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int usr_get_ad9009_RxGain(uint8_t *prxGainIndex, uint8_t channel);
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void usr_printf_radiooff(char *pstr);
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#endif
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Executable
+357
@@ -0,0 +1,357 @@
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#include <stdio.h>
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#include <unistd.h>
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#include <string.h>
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#include <stdio.h>
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#include <string.h>
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#include <unistd.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <fcntl.h>
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#include <linux/spi/spidev.h>
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#include "../inc/type.h"
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#include "../inc/i2c_drv.h"
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#include "../inc/ispi.h"
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#include "../inc/isys_com.h"
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#include "adrv9009.h"
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#define ADRV9009_SPI_NODE "/dev/spidev32766.1"
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struct ad9009_chip_init ad9009_config =
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{
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0x2, //chip_count
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{
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// ad9009_0
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{
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0x61, //写使能寄存器 write_en_reg
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0, //写使能寄存器的控制位 write_en_bit
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0x60, //读使能寄存器 read_en_reg
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0, //读使能寄存器的控制位 read_en_bit
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0x62, //操作寄存器 addr_reg
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0x63, //写数据寄存器 write_data_reg
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0x98, //读数据寄存器 read_data_reg
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0x99, //写数据状态寄存器 write_status_reg
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0, //写数据状态寄存器的标志位 write_status_bit
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0x99, //读数据状态寄存器 read_status_reg
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0, //读数据状态寄存器的标志位 read_status_bit
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0x12, //复位寄存器 read_status_bit
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0, //复位寄存器的标志位
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1, //reset_level
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4, //每次发送休眠时间(us)
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},
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// ad9009_1
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{
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0x65, //写使能寄存器
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0, //写使能寄存器的控制位
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0x64, //读使能寄存器
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0, //读使能寄存器的控制位
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0x66, //操作寄存器
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0x67, //写数据寄存器
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0x9A, //读数据寄存器
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0x9B, //写数据状态寄存器
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0, //写数据状态寄存器的标志位
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0x9B, //读数据状态寄存器
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0, //读数据状态寄存器的标志位
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0x22, //复位寄存器
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0, //复位寄存器的标志位
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1, //reset_level
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4, //每次发送休眠时间(us)
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}
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}
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};
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#if 1
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int adrv9009_spi_fd = -1;
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void spi_9009_init(void)
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{
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unsigned char mode = SPI_MODE_3 ; // 1 0 -- 1 闲时高电平， 0第一个边沿采样
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unsigned char bits = 8;
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unsigned int speed = 100000;
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uint16 u16data = 0;
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init_spi_dev(ADRV9009_SPI_NODE, &adrv9009_spi_fd, mode, bits, speed);
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printf("spi init 9009 fd=%d\n", adrv9009_spi_fd);
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}
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static s8 spi_write_9009(u16 addr, u8 data)
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{
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int ret;
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//printf("spi_write addr=0x%x data=0x%x\n", addr, data);
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ret = spi_w_addr16_data8(adrv9009_spi_fd, addr, data);
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if(ret == 0) {
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return 0;
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} else {
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if(ret == -1)
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log_printf(LOG_ERR,I_SYS_STATUS,"9009_spi_fd err, < 0 \n");
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else if(ret == -2)
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log_printf(LOG_ERR,I_SYS_STATUS,"can't send spi message, for write 9009_spi_fd\n");
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return -1;
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}
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}
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static s8 spi_read_9009(u16 addr, u8 *pdata)
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{
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int ret;
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//printf("spi_read addr=0x%x \n", addr);
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ret = spi_r_addr16_data8(adrv9009_spi_fd, addr, pdata);
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if(ret == 0) {
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return 0;
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} else {
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if(ret == -1)
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log_printf(LOG_ERR,I_SYS_STATUS,"9009_spi_fd err, < 0 \n");
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else if(ret == -2)
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log_printf(LOG_ERR,I_SYS_STATUS,"can't send spi message, for read 9009_spi_fd\n");
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return -1;
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}
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}
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int ad9009_write_hw_spi(int num, u32 addr, u32 *pdata, u32 count)
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{
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int ret = OK;
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struct ad9009_init *p;
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if(num > ad9009_config.chip_count){
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printf("ERROR:ad9009_write:chip num(%d) >%d.! \r\n", num, ad9009_config.chip_count);
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return ERROR;
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}
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if(num == 1){
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p = (struct ad9009_init *)&ad9009_config.data;
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}
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else{
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p = &ad9009_config.data[1];
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}
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uint8 *p8data = (uint8 *)pdata;
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while (count--){
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spi_write_9009((uint16)(addr&0xffff), *p8data);
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addr++;
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p8data++;
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}
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return ret;
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}
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int ad9009_read_hw_spi(int num, u32 addr, u32 *pdata, u32 count)
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{
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int ret = OK;
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struct ad9009_init *p;
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if(num >ad9009_config.chip_count){
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printf("ERROR:ad9009_read:chip num(%d) >%d.! \r\n",num,ad9009_config.chip_count);
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return ERROR;
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}
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if(num==1){
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p = (struct ad9009_init *)&ad9009_config.data;
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}
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else{
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p = &ad9009_config.data[1];
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}
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uint8 *p8data = (uint8 *)pdata;
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while (count--){
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if(addr>0xffff){
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printf("warning, addr=0x%x over range!\n", addr);
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}
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spi_read_9009((uint16)(addr&0xffff), p8data);
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addr++;
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p8data++;
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}
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return ret;
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}
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#if 0
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int ad9009_write_sim_spi(int num, u32 addr, u32 *pdata, u32 count)
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{
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int ret = OK;
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struct ad9009_init *p;
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u32 write_status = 0;
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u32 timeout_count = 0;
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u32 write_data;
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if(num > ad9009_config.chip_count){
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printf("ERROR:ad9009_write:chip num(%d) >%d.! \r\n", num, ad9009_config.chip_count);
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return ERROR;
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}
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if(num == 1){
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p = (struct ad9009_init *)&ad9009_config.data;
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}
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else{
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p = &ad9009_config.data[1];
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}
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/*int fd = open(FPGA_ADRV9009_NODE, O_RDWR);
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if (fd < 0) {
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printf("\n\n[ ad9009_write_sim_spi ] node err.\n");
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return ERROR;
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}*/
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while (count--){
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fpga_write_axi0(p->addr_reg, addr, 1);
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fpga_write_axi0(p->write_data_reg, *pdata, 1);
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write_data = 0;
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fpga_write_axi0(p->write_en_reg, write_data, 1);
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write_data = 1;
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fpga_write_axi0(p->write_en_reg, write_data, 1);
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timeout_count = 0;
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do{
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usleep(p->sleep_time);
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//if(OK != (fpga_getbit(fd, p->write_status_reg, p->write_status_bit, 1, &write_status)))
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if(OK != (fpga_read_axi0(p->write_status_reg, &write_status, 1))){
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ret = ERROR;
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printf("ERROR:read status reg[0x%x]=0x%x failed! \n", p->write_status_reg, write_status);
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break;
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}
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timeout_count++;
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write_status = (write_status >> p->write_status_bit);
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if ((RETRY_GET_STATUS_COUNT_MAX) < timeout_count){ //最多尝试100次
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ret = ERROR;
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printf("[%s,%d]ERROR:read reg[0x%x]=0x%x timeout! \r\n", __FUNCTION__, __LINE__, p->write_status_reg,write_status);
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break;
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}
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}while (write_status != 1);
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addr++;
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pdata++;
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}
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//close(fd);
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return ret;
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}
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int ad9009_read_sim_spi(int num, u32 addr, u32 *pdata, u32 count)
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{
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int ret = OK;
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struct ad9009_init *p;
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u32 read_status = 0;
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u32 timeout_count = 0;
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u32 write_data;
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if(num >ad9009_config.chip_count){
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printf("ERROR:ad9009_read:chip num(%d) >%d.! \r\n",num,ad9009_config.chip_count);
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return ERROR;
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}
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||||
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if(num==1){
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p = (struct ad9009_init *)&ad9009_config.data;
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}
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else{
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p = &ad9009_config.data[1];
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}
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|
||||
/*int fd = open(FPGA_ADRV9009_NODE, O_RDWR);
|
||||
if (fd < 0) {
|
||||
printf("\n\n[ ad9009_read_sim_spi ] node err.\n");
|
||||
return ERROR;
|
||||
}*/
|
||||
|
||||
while (count--){
|
||||
fpga_write_axi0(p->addr_reg, addr, 1);
|
||||
|
||||
write_data = 0;
|
||||
fpga_write_axi0(p->read_en_reg, write_data, 1);
|
||||
|
||||
write_data = 1;
|
||||
fpga_write_axi0(p->read_en_reg, write_data, 1);
|
||||
|
||||
timeout_count = 0;
|
||||
|
||||
do{
|
||||
usleep(p->sleep_time);
|
||||
//if (OK != fpga_getbit(fd, p->read_status_reg, p->read_status_bit, 1, &read_status))
|
||||
if (OK != fpga_read_axi0(p->read_status_reg, &read_status, 1)){
|
||||
ret = ERROR;
|
||||
printf("ERROR:read status reg[0x%x] =0x%xfailed! \r\n", p->read_status_reg, read_status);
|
||||
break;
|
||||
}
|
||||
read_status = (read_status >> p->read_status_bit);
|
||||
timeout_count++;
|
||||
if ((RETRY_GET_STATUS_COUNT_MAX) < timeout_count){ //最多尝试100次
|
||||
ret = ERROR;
|
||||
printf("[%s,%d]ERROR:read reg[0x%x] timeout! \r\n", __FUNCTION__, __LINE__, p->write_status_reg);
|
||||
break;
|
||||
}
|
||||
|
||||
}while (read_status != 1);
|
||||
|
||||
if (1 != read_status){
|
||||
ret = ERROR;
|
||||
printf("ERROR:time out, read_status = %d\r\n",read_status);
|
||||
break;
|
||||
}
|
||||
|
||||
if (OK != fpga_read_axi0(p->read_data_reg, pdata, 1)){
|
||||
printf("[%s%d]ERROR: read reg[0x%x] failed! \r\n", __FUNCTION__, __LINE__, addr);
|
||||
ret = ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
addr++;
|
||||
pdata++;
|
||||
}
|
||||
|
||||
//close(fd);
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
int ad9009_reset(int num)
|
||||
{
|
||||
int ret = OK;
|
||||
//分开寄存器控制
|
||||
struct ad9009_init *p;
|
||||
u32 write_data;
|
||||
|
||||
if(num >ad9009_config.chip_count){
|
||||
printf("ERROR:ad9009_reset:chip num(%d) >%d.! \r\n",num,ad9009_config.chip_count);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
if(num==1){
|
||||
p = (struct ad9009_init *)&ad9009_config.data;
|
||||
}
|
||||
else{
|
||||
p = &ad9009_config.data[1];
|
||||
}
|
||||
|
||||
/*int fd = open(FPGA_ADRV9009_NODE, O_RDWR);
|
||||
if (fd < 0) {
|
||||
printf("\n\n[ ad9009_reset ] node err.\n");
|
||||
return ERROR;
|
||||
}*/
|
||||
|
||||
//@cc参照原来的程序 reset adrv9009 0x12 先 1后0
|
||||
//write_data = (p->reset_level<<p->reset_bit);
|
||||
write_data = p->reset_level;
|
||||
fpga_write_axi0(p->reset_reg, write_data, 1);
|
||||
|
||||
usleep(100*1000);
|
||||
write_data = !(p->reset_level);
|
||||
fpga_write_axi0(p->reset_reg, write_data, 1);
|
||||
|
||||
//close(fd);
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif
|
||||
Executable
+73
@@ -0,0 +1,73 @@
|
||||
|
||||
#ifndef _ADRV9009_H_
|
||||
#define _ADRV9009_H_
|
||||
|
||||
#define USR_AD9009_FPGA_WR 1
|
||||
|
||||
//#define FPGA_NODE "/dev/zynq_axi0"
|
||||
//#define FPGA_NODE "/dev/spidev1.0"
|
||||
|
||||
#define FPGA_ADRV9009_NODE "/dev/zynq_axi0"
|
||||
|
||||
#include "fcntl.h"
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define RETRY_GET_STATUS_COUNT_MAX 100
|
||||
|
||||
|
||||
|
||||
// 使用fpga作为转发时使用以下结构体
|
||||
//分开寄存器控制
|
||||
#if 1
|
||||
|
||||
struct ad9009_init
|
||||
{
|
||||
u32 write_en_reg; //写使能寄存器
|
||||
u32 write_en_bit; //写使能寄存器的控制位
|
||||
u32 read_en_reg; //读使能寄存器
|
||||
u32 read_en_bit; //读使能寄存器的控制位
|
||||
u32 addr_reg; //操作寄存器
|
||||
u32 write_data_reg; //写数据寄存器
|
||||
u32 read_data_reg; //读数据寄存器
|
||||
u32 write_status_reg; //写数据状态寄存器
|
||||
u32 write_status_bit; //写数据状态寄存器的标志位
|
||||
u32 read_status_reg; //读数据状态寄存器
|
||||
u32 read_status_bit; //读数据状态寄存器的标志位
|
||||
u32 reset_reg; //复位寄存器
|
||||
u32 reset_bit; //复位寄存器的标志位
|
||||
u32 reset_level; //reset level
|
||||
u32 sleep_time; //每次发送休眠时间
|
||||
};
|
||||
|
||||
struct ad9009_chip_init
|
||||
{
|
||||
u32 chip_count;
|
||||
struct ad9009_init data[4];
|
||||
};
|
||||
|
||||
//int write_ad9009(u32 num, u32 addr, u32 data);
|
||||
//int read_ad9009(u32 num, u32 addr, u32 count);
|
||||
//int read_ad9009_value(int num,int addr, unsigned int *value);
|
||||
//int ad9009_read(int num, u32 addr, u32 *pdata, u32 count);
|
||||
int ad9009_reset(int num);
|
||||
|
||||
|
||||
#define ad9009_write_spi ad9009_write_hw_spi
|
||||
#define ad9009_read_spi ad9009_read_hw_spi
|
||||
|
||||
//#define ad9009_write_spi ad9009_write_sim_spi
|
||||
//#define ad9009_read_spi ad9009_read_sim_spi
|
||||
|
||||
|
||||
int ad9009_write_spi(int num, u32 addr, u32 *pdata, u32 count);
|
||||
int ad9009_read_spi(int num, u32 addr, u32 *pdata, u32 count);
|
||||
void spi_9009_init(void);
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
Executable
+1675
File diff suppressed because it is too large
Load Diff
Executable
+243
@@ -0,0 +1,243 @@
|
||||
|
||||
#ifndef _ADRV9009_CONFIG_H_
|
||||
#define _ADRV9009_CONFIG_H_
|
||||
//#include "../type.h"
|
||||
|
||||
|
||||
|
||||
typedef enum{
|
||||
ADRV9009_0=0,
|
||||
ADRV9009_1
|
||||
}ADRV9009_NUM;
|
||||
|
||||
|
||||
typedef struct{
|
||||
u32 reg00;
|
||||
u32 reg01;
|
||||
u32 reg0C;
|
||||
u32 reg18;
|
||||
|
||||
u32 cpri_rec_cl_lost;
|
||||
u32 ad9528_status_ld;
|
||||
|
||||
// // reg addr 0x00
|
||||
// u8 summary_alarm; // bit4
|
||||
// u8 status_code; // bit3-0
|
||||
// // reg addr 0x01
|
||||
// u8 latched_ver_loacl_LOF; // bit15
|
||||
// u8 latched_ver_loacl_LOS; // bit14
|
||||
// u8 latched_ver_loacl_RAI; // bit13
|
||||
// u8 latched_ver_remote_LOF; // bit12
|
||||
// u8 latched_ver_remote_LOS; // bit11
|
||||
// u8 latched_ver_remote_SAP; // bit10
|
||||
// u8 latched_ver_remote_RAI; // bit9
|
||||
// u8 latched_ver_remote_rst; // bit8
|
||||
// u8 core_type; // bit7 1-core is a master port, 0 -- core is a slave port
|
||||
// u8 core_genered; // bit6 1-core has been generated using a hardware evaluation license
|
||||
// u8 local_LOF; // bit1
|
||||
// u8 local_LOS; // bit0
|
||||
// // reg addr 0x0C Current Line Speed Register
|
||||
// u16 speed_index; // bit15
|
||||
// // reg addr 0x18 General Debug Register
|
||||
}ST_REG_STATUS;
|
||||
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------------------
|
||||
|
||||
#if 1//something may not used
|
||||
#define AXI_ADDR_VERSION1 0x86
|
||||
#define AXI_ADDR_DPD_CTRL1 0x110
|
||||
#define AXI_ADDR_DPD_CTRL2 0x111
|
||||
#define AXI_ADDR_DPD_CTRL3 0x112
|
||||
#define AXI_ADDR_CFR_CTRL1 0x113
|
||||
#define AXI_ADDR_CFR_CTRL2 0x114
|
||||
#define AXI_ADDR_SIG_SHIFT 0x115
|
||||
#define AXI_ADDR_DPD_FIXDLY 0x116
|
||||
#define AXI_ADDR_DPD_AGCPWR 0x117
|
||||
#define AXI_ADDR_DPD_TEST 0x118
|
||||
#define AXI_ADDR_FBROUTE 0x11A
|
||||
#define AXI_ADDR_ERR_CHECK 0x11B
|
||||
#define AXI_ADDR_AMP_SAT 0x11C
|
||||
#define AXI_ADDR_BW_MODE 0x12D
|
||||
#define AXI_ADDR_CRST_TAP_MAP 0x11D
|
||||
#define AXI_ADDR_CRST_ADREF_TAP0 0x11E
|
||||
#define AXI_ADDR_CRST_ADREF_TAP1 0x11F
|
||||
#define AXI_ADDR_CRST_ADREF_TAP2 0x120
|
||||
#define AXI_ADDR_CRST_ADREF_TAP3 0x121
|
||||
#define AXI_ADDR_CRST_ADREF_TAP4 0x122
|
||||
#define AXI_ADDR_CRST_ADREF_TAP5 0x123
|
||||
#define AXI_ADDR_CRST_ADREF_TAP6 0x124
|
||||
#define AXI_ADDR_CRST_ADREF_TAP7 0x125
|
||||
#define AXI_ADDR_CRST_ADREF_TAP8 0x126
|
||||
#define AXI_ADDR_CRST_ADREF_TAP9 0x127
|
||||
#define AXI_ADDR_CRST_ADREF_TAP10 0x128
|
||||
#define AXI_ADDR_CRST_ADREF_TAP11 0x129
|
||||
#define AXI_ADDR_CRST_ADREF_TAP12 0x130
|
||||
#define AXI_ADDR_CRST_ADREF_TAP13 0x131
|
||||
#define AXI_ADDR_CRST_ADREF_TAP14 0x132
|
||||
|
||||
#define AXI_ADDR_DPD_STATUS1 0x200
|
||||
#define AXI_ADDR_DPD_AGCCWORD 0x201
|
||||
#define AXI_ADDR_DPD_SYNCOFFSET 0x202
|
||||
|
||||
/*#define MASK_DPD_ERR (0x0001)
|
||||
#define MASK_DPD_PWRHIGH (0x0001<<1)
|
||||
#define MASK_DPD_PWRLOW (0x0001<<2)
|
||||
#define MASK_DPD_ERR_ABORT (0x0001<<3)
|
||||
#define MASK_DPD_TRX_SYNC_OK (0x0001<<4)
|
||||
#define MASK_DPD_DAGC_TOOHIGH (0x0001<<5)
|
||||
#define MASK_DPD_DAGC_TOOLOW (0x0001<<6)
|
||||
|
||||
#define DPD_CTRL1_DPD_START (0x0001)
|
||||
#define DPD_CTRL1_DPD_ALLCLR (0x0001<<1)
|
||||
#define DPD_CTRL1_ALL_BYPS (0x0001<<2)
|
||||
|
||||
#define DPD_CTRL2_LIN_UPDATE (0x0001)
|
||||
#define DPD_CTRL2_NONLIN_UPDATE (0x0001<<1)
|
||||
#define DPD_CTRL2_SET_NONLIN_UDP_MOD(x) (((x)&0x07)<<2) //01 : POLY; 10: CRST, 100 SELF
|
||||
#define DPD_CTRL2_AMP_CHK (0x0001<<4)
|
||||
*/
|
||||
#define DPD_CTRL3_FAGC_UPDATE (0x0001)
|
||||
#define DPD_CTRL3_FAGC_SLOWDN (0x0001<<1)
|
||||
#define DPD_CTRL3_DAGC_UPDATE (0x0001<<2)
|
||||
#define DPD_CTRL3_DAGC_SLOWDN (0x0001<<3)
|
||||
#define DPD_CTRL3_DCRM_UPDATE (0x0001<<4)
|
||||
#define DPD_CTRL3_ROT_UPDATE (0x0001<<5)
|
||||
#define DPD_CTRL3_SYNC_UPDATE (0x0001<<6)
|
||||
#define DPD_CTRL3_SYNC_RESTART (0x0001<<7)
|
||||
#define DPD_CTRL3_IQB_UPDATE (0x0001<<8)
|
||||
|
||||
#define DPD_SET_100M (0x00)
|
||||
#define DPD_SET_25M (0x01)
|
||||
|
||||
#define SET_DPDFAGC_REFPWR(x) ((x))
|
||||
#define DPD_SET_CRST_ADDR_STRUCT_2 ((0x01)<<17)
|
||||
#define DPD_SET_ERR_TH(x) (((x)&0xffff))
|
||||
#define DPD_SET_ERR_CNT_TH(x) (((x)&0xff)<<16)
|
||||
#define DPD_SET_DGAIN(x) (((x)&0xffff)<<2)
|
||||
#define DPD_SET_FIX_DLY(x) (0x8000 & ((x)&0x7ff))
|
||||
#define DPD_SET_CRST_REFAD(x) ((x)[0] | ((x)[1]<<4) | ((x)[2]<<8) | ((x)[3]<<12) | ((x)[4]<<16) | ((x)[5]<<20))
|
||||
|
||||
#define DPD_MAX_TX_AMP_SAT 65535
|
||||
//#define TX_FREQ_IN_HZ 2595000000
|
||||
|
||||
//#define TX_FREQ_IN_HZ 3550000000 //3550000000 //h210809 2595000000 => 3550000000
|
||||
//#define TX_FREQ_IN_HZ (2595000000*1.024) //3550000000 //h210809 2595000000 => 3550000000
|
||||
//#define TX_FREQ_IN_HZ (3550000000*1.024) //3550000000 //h210809 2595000000 => 3550000000
|
||||
//#define TX_FREQ_IN_HZ (698000000*1.024) //3550000000 //h210809 2595000000 => 3550000000
|
||||
//#define TX_FREQ_IN_HZ (2595000000*1.024) //3550000000 //h210809 2595000000 => 3550000000
|
||||
//#define TX_FREQ_IN_HZ (698000000*1.024) //3550000000 //h210809 2595000000 => 3550000000
|
||||
|
||||
#define TX_FREQ_IN_HZ (300000000) //3550000000 //h210809 2595000000 => 3550000000
|
||||
|
||||
#define D_SET_ATT 8000
|
||||
// note index msg
|
||||
enum
|
||||
{
|
||||
NOTE_M_DPD_STEP = 1,
|
||||
NOTE_E_TX_POWER_TOO_MUCH,
|
||||
NOTE_FEEDBACK_POWER_LOW,
|
||||
NOTE_FEEDBACK_POWER_HIGH,
|
||||
NOTE_DPD_ABORT_DUE_TO_LARGE_ERR,
|
||||
NOTE_DPD_ABORT_DUE_TO_DAGC_INPUT_LOW,
|
||||
NOTE_DPD_ABORT_DUE_TO_DAGC_INPUT_HIGH,
|
||||
NOTE_TXRX_SYNC_OK,
|
||||
NOTE_TXRX_SYNC_FAILED,
|
||||
NOTE_STEP_FINISHED_DO_NEXT_STEP,
|
||||
NOTE_STEP_DONE,
|
||||
NOTE_STEP_SUCCESS,
|
||||
NOTE_PROCESS_ABORT,
|
||||
NOTE_END
|
||||
};
|
||||
|
||||
#if 1
|
||||
//area1
|
||||
#define A1_ADDR_TAP_START 0
|
||||
#define A1_ADDR_TAP_STOP 14
|
||||
|
||||
#define A1_ADDR_SUB_TAP_START 4
|
||||
#define A1_ADDR_SUB_TAP_STOP 4
|
||||
|
||||
#define A1_ADDR_CRST_START 0
|
||||
#define A1_ADDR_CRST_STOP 511
|
||||
|
||||
#define A1_ADDR_WORD_START 1 //����
|
||||
#define A1_ADDR_WORD_STOP 0
|
||||
|
||||
#define A1_TOTAL_LEN ((A1_ADDR_TAP_STOP-A1_ADDR_TAP_START+1)*(A1_ADDR_SUB_TAP_STOP-A1_ADDR_SUB_TAP_START+1)*(A1_ADDR_CRST_STOP-A1_ADDR_CRST_START+1)*(A1_ADDR_WORD_START-A1_ADDR_WORD_STOP+1))
|
||||
|
||||
//area2
|
||||
#define A2_ADDR_TAP_START 4
|
||||
#define A2_ADDR_TAP_STOP 10
|
||||
|
||||
#define A2_ADDR_SUB_TAP_START 2
|
||||
#define A2_ADDR_SUB_TAP_STOP 3
|
||||
|
||||
#define A2_ADDR_CRST_START 0
|
||||
#define A2_ADDR_CRST_STOP 1023
|
||||
|
||||
#define A2_ADDR_WORD_START 3 //����
|
||||
#define A2_ADDR_WORD_STOP 0
|
||||
|
||||
#define A2_TOTAL_LEN ((A2_ADDR_TAP_STOP-A2_ADDR_TAP_START+1)*(A2_ADDR_SUB_TAP_STOP-A2_ADDR_SUB_TAP_START+1)*(A2_ADDR_CRST_STOP-A2_ADDR_CRST_START+1)*(A2_ADDR_WORD_START-A2_ADDR_WORD_STOP+1))
|
||||
|
||||
//area3
|
||||
#define A3_ADDR_TAP_START 4
|
||||
#define A3_ADDR_TAP_STOP 10
|
||||
|
||||
#define A3_ADDR_SUB_TAP_START 0
|
||||
#define A3_ADDR_SUB_TAP_STOP 1
|
||||
|
||||
#define A3_ADDR_CRST_START 0
|
||||
#define A3_ADDR_CRST_STOP 1023
|
||||
|
||||
#define A3_ADDR_WORD_START 4 //����
|
||||
#define A3_ADDR_WORD_STOP 0
|
||||
|
||||
#define A3_TOTAL_LEN ((A3_ADDR_TAP_STOP-A3_ADDR_TAP_START+1)*(A3_ADDR_SUB_TAP_STOP-A3_ADDR_SUB_TAP_START+1)*(A3_ADDR_CRST_STOP-A3_ADDR_CRST_START+1)*(A3_ADDR_WORD_START-A3_ADDR_WORD_STOP+1))
|
||||
|
||||
|
||||
//area4
|
||||
#define A4_ADDR_TAP_START 15
|
||||
#define A4_ADDR_TAP_STOP 15
|
||||
|
||||
#define A4_ADDR_SUB_TAP_START 0
|
||||
#define A4_ADDR_SUB_TAP_STOP 6
|
||||
|
||||
#define A4_ADDR_CRST_START 0
|
||||
#define A4_ADDR_CRST_STOP 31
|
||||
|
||||
#define A4_TOTAL_LEN ((A4_ADDR_TAP_STOP-A4_ADDR_TAP_START+1)*(A4_ADDR_SUB_TAP_STOP-A4_ADDR_SUB_TAP_START+1)*(A4_ADDR_CRST_STOP-A4_ADDR_CRST_START+1))
|
||||
|
||||
#define AREA_TATAL_LEN (A1_TOTAL_LEN+A2_TOTAL_LEN+A3_TOTAL_LEN+A4_TOTAL_LEN)
|
||||
#endif
|
||||
|
||||
|
||||
//static int g_dpd_up_flg=E_DPD_IDLE;
|
||||
|
||||
#define MASK_SPI_EN_SPI1_ENABLE (0x1<<0)
|
||||
#define MASK_SPI_EN_SPI2_ENABLE (0x1<<1)
|
||||
#define MASK_SPI_EN_EXT_SPI_ENABLE (0x1<<2)
|
||||
#define MASK_SPI_EN_MCU_SPI1_ENABLE (0x1<<3)
|
||||
|
||||
|
||||
#endif
|
||||
//---------------------------------------------------------------------------------------
|
||||
|
||||
int adrv9009_cfg(int which_9009);
|
||||
int adrv9009_orx_gain_thr();
|
||||
void adrv9009_orx_gain_stop(void);
|
||||
int Adrv9009_Ext_LOL_Cal_1(int which_9009);
|
||||
int Adrv9009_Ext_LOL_Cal_2(int which_9009);
|
||||
extern void * status_monitor_thr (void * args);
|
||||
extern void read_fpga_version(char *pVer);
|
||||
|
||||
|
||||
extern void adrv9009_init(void);
|
||||
extern void chang_freq(uint8 radio_ctl, int freq_changed);
|
||||
extern void chang_cw(int cw);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
Executable
+123
@@ -0,0 +1,123 @@
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <unistd.h>
|
||||
#include <pthread.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "../inc/type.h"
|
||||
#include "talise_config.h"
|
||||
#include "adrv9009_config.h"
|
||||
|
||||
#define FPGA_ORX1_GAIN_REG 0xC4
|
||||
#define ORX_GAIN_POLL_MS 100//100
|
||||
|
||||
static pthread_t g_orx_poll_thread;
|
||||
static volatile int g_orx_poll_running = 0;
|
||||
pthread_mutex_t g_orx_gain_lock = PTHREAD_MUTEX_INITIALIZER;
|
||||
static uint8_t g_last_orx1_gain = 0xFF;
|
||||
static taliseDevice_t *g_dev = NULL;
|
||||
|
||||
extern int fpga_read_axi0(uint32 addr, uint32 *pdata, uint32 count);
|
||||
extern taliseInit_t *p_myTalInit;
|
||||
extern taliseDevice_t *p_myTaliseDevice_shm;;
|
||||
|
||||
static int set_orx_gain_index_safe(unsigned int ch, uint8_t gain)
|
||||
{
|
||||
taliseObsRxChannels_t channel;
|
||||
uint8_t min_idx, max_idx;
|
||||
|
||||
switch (ch) {
|
||||
case 1:
|
||||
channel = TAL_ORX1;
|
||||
min_idx = p_myTalInit->obsRx.orxGainCtrl.orx1MinGainIndex;
|
||||
max_idx = p_myTalInit->obsRx.orxGainCtrl.orx1MaxGainIndex;
|
||||
break;
|
||||
case 2:
|
||||
channel = TAL_ORX2;
|
||||
min_idx = p_myTalInit->obsRx.orxGainCtrl.orx2MinGainIndex;
|
||||
max_idx = p_myTalInit->obsRx.orxGainCtrl.orx2MaxGainIndex;
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (gain < min_idx) gain = min_idx;
|
||||
if (gain > max_idx) gain = max_idx;
|
||||
|
||||
printf("start TALISE_setObsRxManualGain\n");
|
||||
pthread_mutex_lock(&g_orx_gain_lock);
|
||||
int ret = TALISE_setObsRxManualGain(g_dev, channel, gain);
|
||||
pthread_mutex_unlock(&g_orx_gain_lock);
|
||||
printf("end TALISE_setObsRxManualGain\n");
|
||||
|
||||
if (ret == TALACT_NO_ACTION) {
|
||||
printf("[ORxGain] set ORx%u gain=0x%02X (range %u-%u)\n", ch, gain, min_idx, max_idx);
|
||||
return 0;
|
||||
}
|
||||
|
||||
printf("[ORxGain] FAIL: set ORx%u gain=0x%02X, ret=%d\n", ch, gain, ret);
|
||||
return -1;
|
||||
}
|
||||
|
||||
static void *orx_gain_poll_loop(void *arg)
|
||||
{
|
||||
(void)arg;
|
||||
uint8_t reg_val;
|
||||
int ret;
|
||||
|
||||
|
||||
g_dev = (taliseDevice_t *)p_myTaliseDevice_shm;
|
||||
g_last_orx1_gain = 0xFF;
|
||||
|
||||
printf("[ORxGain] Polling thread started, period=%dms\n", ORX_GAIN_POLL_MS);
|
||||
|
||||
while (1) {
|
||||
ret = fpga_read_axi0(FPGA_ORX1_GAIN_REG, (uint32_t *)®_val, 1);
|
||||
if (ret != OK) {
|
||||
usleep(ORX_GAIN_POLL_MS * 1000);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (reg_val == g_last_orx1_gain) {
|
||||
usleep(ORX_GAIN_POLL_MS * 1000);
|
||||
continue;
|
||||
}
|
||||
|
||||
if(g_dev){
|
||||
ret = set_orx_gain_index_safe(TAL_ORX1, reg_val);
|
||||
if (ret == 0) {
|
||||
printf("chg orx1_gain %d->%d\n", g_last_orx1_gain, reg_val);
|
||||
g_last_orx1_gain = reg_val;
|
||||
}
|
||||
}
|
||||
else{
|
||||
printf("warning, dev null\n");
|
||||
}
|
||||
|
||||
usleep(ORX_GAIN_POLL_MS * 1000);
|
||||
}
|
||||
|
||||
printf("[ORxGain] Polling thread exited\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
int adrv9009_orx_gain_thr()
|
||||
{
|
||||
if (pthread_create(&g_orx_poll_thread, NULL, orx_gain_poll_loop, NULL) != 0) {
|
||||
printf("[ORxGain] Failed to create polling thread\n");
|
||||
g_orx_poll_running = 0;
|
||||
return -1;
|
||||
}
|
||||
//pthread_detach(g_orx_poll_thread);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void adrv9009_orx_gain_stop(void)
|
||||
{
|
||||
if (!g_orx_poll_running)
|
||||
return;
|
||||
|
||||
g_orx_poll_running = 0;
|
||||
usleep(ORX_GAIN_POLL_MS * 2);
|
||||
printf("[ORxGain] Polling stopped\n");
|
||||
}
|
||||
Executable
+79
@@ -0,0 +1,79 @@
|
||||
|
||||
#include <unistd.h>
|
||||
#include <stdio.h>
|
||||
|
||||
//#include "../type.h"
|
||||
//#include "jesd204b.h"
|
||||
//#include "../fpga.h"
|
||||
//#include "../common.h"
|
||||
|
||||
|
||||
//#include "../cfg.h"
|
||||
|
||||
|
||||
#if 0
|
||||
//APB_write
|
||||
|
||||
#define READ_TIME_OUT 1000
|
||||
|
||||
|
||||
//[]
|
||||
int apb_jesd204b_read(u32 addr, u32 *pdata)
|
||||
{
|
||||
int i =0;
|
||||
read_reg_data((ANYWAVE_AXI_APB_204B_BASE_ADDR+( (addr+i) << 2)), pdata, 1);
|
||||
return OK;
|
||||
}
|
||||
// ext give addr have been << 2, so apb_jesd204b_write do not need to << 2
|
||||
int apb_jesd204b_write(u32 addr, u32 data)
|
||||
{
|
||||
return (write_reg_data((ANYWAVE_AXI_APB_204B_BASE_ADDR+addr), data));
|
||||
}
|
||||
|
||||
|
||||
//[jesd]
|
||||
u32 apb_jesd_read(u32 addr, u32 *pdata)
|
||||
{
|
||||
int i =0;
|
||||
read_reg_data((ANYWAVE_AXI_APB_JESD_BASE_ADDR+( (addr+i) << 2)), pdata, 1);
|
||||
return (ANYWAVE_AXI_APB_JESD_BASE_ADDR+( (addr+i) << 2));
|
||||
}
|
||||
// ext give addr have been << 2, so apb_jesd204b_write do not need to << 2
|
||||
int apb_jesd_write(u32 addr, u32 data)
|
||||
{
|
||||
return (write_reg_data((ANYWAVE_AXI_APB_JESD_BASE_ADDR+addr), data));
|
||||
}
|
||||
|
||||
|
||||
//[jesd_serdes2]
|
||||
u32 apb_serdes2_read(u32 addr, u32 *pdata)
|
||||
{
|
||||
int i =0;
|
||||
read_reg_data((ANYWAVE_AXI_APB_JESD_SERDES2_BASE_ADDR+( (addr+i) << 2)), pdata, 1);
|
||||
return (ANYWAVE_AXI_APB_JESD_SERDES2_BASE_ADDR+( (addr+i) << 2));
|
||||
}
|
||||
// ext give addr have been << 2, so apb_jesd204b_write do not need to << 2
|
||||
int apb_serdes2_write(u32 addr, u32 data)
|
||||
{
|
||||
return (write_reg_data((ANYWAVE_AXI_APB_JESD_SERDES2_BASE_ADDR+addr), data));
|
||||
}
|
||||
|
||||
|
||||
//[jesd_serdes3]
|
||||
u32 apb_serdes3_read(u32 addr, u32 *pdata)
|
||||
{
|
||||
int i =0;
|
||||
read_reg_data((ANYWAVE_AXI_APB_JESD_SERDES3_BASE_ADDR+( (addr+i) << 2)), pdata, 1);
|
||||
return (ANYWAVE_AXI_APB_JESD_SERDES3_BASE_ADDR+( (addr+i) << 2));
|
||||
}
|
||||
// ext give addr have been << 2, so apb_jesd204b_write do not need to << 2
|
||||
int apb_serdes3_write(u32 addr, u32 data)
|
||||
{
|
||||
return (write_reg_data((ANYWAVE_AXI_APB_JESD_SERDES3_BASE_ADDR+addr), data));
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
Executable
+1334
File diff suppressed because it is too large
Load Diff
Executable
+427
@@ -0,0 +1,427 @@
|
||||
#include <unistd.h>
|
||||
#include <stdio.h>
|
||||
|
||||
|
||||
//#include"../common.h"
|
||||
//#include"../fpga.h"
|
||||
#include "../inc/i2c_drv.h"
|
||||
#include "../inc/isys_config.h"
|
||||
|
||||
/*
|
||||
//for tx0
|
||||
#define TX0_CFG_ENABLE_REG 0x76 //bit4->rd bit5->wr
|
||||
#define TX0_CFG_ADDR_REG 0x74
|
||||
#define TX0_CFG_WR_DATA_REG 0x75
|
||||
#define TX0_CFG_RD_DATA_REG 0xb6
|
||||
#define TX0_CFG_RD_UPDATA_FLAG_REG 0xb3 //bit2 is avalid
|
||||
|
||||
//for fb0
|
||||
#define FB0_CFG_ENABLE_REG 0x76 //bit2->rd bit3->wr
|
||||
#define FB0_CFG_ADDR_REG 0x72
|
||||
#define FB0_CFG_WR_DATA_REG 0x73
|
||||
#define FB0_CFG_RD_DATA_REG 0xb5
|
||||
#define FB0_CFG_RD_UPDATA_FLAG_REG 0xb3 //bit1 is avalid
|
||||
|
||||
//for rx0
|
||||
#define RX0_CFG_ENABLE_REG 0x76 //bit0->rd bit1->wr
|
||||
#define RX0_CFG_ADDR_REG 0x70
|
||||
#define RX0_CFG_WR_DATA_REG 0x71
|
||||
#define RX0_CFG_RD_DATA_REG 0xb4
|
||||
#define RX0_CFG_RD_UPDATA_FLAG_REG 0xb3 //bit0 is avalid
|
||||
*/
|
||||
|
||||
//for tx0/fb0/rx0 (共享 0xB1~0xB8 I2C 寄存器)
|
||||
#define TX0_CFG_ENABLE_REG 0xB5 //bit1->rd bit2->wr
|
||||
#define TX0_CFG_ADDR_H_REG 0xB7
|
||||
#define TX0_CFG_ADDR_L_REG 0xB6
|
||||
#define TX0_CFG_WR_DATA_REG 0xB8
|
||||
|
||||
#define TX0_CFG_RD_DATA_REG 0xb6
|
||||
#define TX0_CFG_RD_UPDATA_FLAG_REG 0xb3 //bit2 is avalid
|
||||
|
||||
//for fb0 (registers from Task11.md §3.1 — FPGA I2C->JESD AXI bridge)
|
||||
#define FB0_CFG_ENABLE_REG 0xBC // bit0->rd bit1->wr
|
||||
#define FB0_CFG_ADDR_L_REG 0xBD // addr[7:0]
|
||||
#define FB0_CFG_ADDR_H_REG 0xBE // addr[11:8] (仅低4位有效)
|
||||
#define FB0_CFG_WR_DATA_REG 0xBF // write data[7:0]
|
||||
|
||||
#define FB0_CFG_MON_REG 0xBB // monitor: bit2=rd_update, bit1=fb_sync, bit0=fb_tvalid
|
||||
#define FB0_CFG_RD_DATA0_REG 0xC0 // read data[7:0]
|
||||
#define FB0_CFG_RD_DATA1_REG 0xC1 // read data[15:8]
|
||||
#define FB0_CFG_RD_DATA2_REG 0xC2 // read data[23:16]
|
||||
#define FB0_CFG_RD_DATA3_REG 0xC3 // read data[31:24]
|
||||
|
||||
|
||||
|
||||
//for rx0
|
||||
#define RX0_CFG_ENABLE_REG 0xB5 //bit1->rd bit2->wr
|
||||
#define RX0_CFG_ADDR_REG 0x70
|
||||
#define RX0_CFG_WR_DATA_REG 0x71
|
||||
#define RX0_CFG_RD_DATA_REG 0xb4
|
||||
#define RX0_CFG_RD_UPDATA_FLAG_REG 0xb3 //bit2 is avalid
|
||||
|
||||
//----------------------------------------------------------
|
||||
|
||||
//for tx1/fb1/rx1 (共享 0x50~0x5F I2C 寄存器)
|
||||
#define TX1_CFG_ENABLE_REG 0x56 //bit1->rd bit2->wr
|
||||
#define TX1_CFG_ADDR_REG 0x54
|
||||
#define TX1_CFG_WR_DATA_REG 0x55
|
||||
#define TX1_CFG_RD_DATA_REG 0xc6
|
||||
#define TX1_CFG_RD_UPDATA_FLAG_REG 0xc3 //bit2 is avalid
|
||||
//for fb1
|
||||
#define FB1_CFG_ENABLE_REG 0x56 //bit1->rd bit2->wr
|
||||
#define FB1_CFG_ADDR_REG 0x52
|
||||
#define FB1_CFG_WR_DATA_REG 0x53
|
||||
#define FB1_CFG_RD_DATA_REG 0xc5
|
||||
#define FB1_CFG_RD_UPDATA_FLAG_REG 0xc3 //bit2 is avalid
|
||||
//for rx1
|
||||
#define RX1_CFG_ENABLE_REG 0x56 //bit1->rd bit2->wr
|
||||
#define RX1_CFG_ADDR_REG 0x50
|
||||
#define RX1_CFG_WR_DATA_REG 0x51
|
||||
#define RX1_CFG_RD_DATA_REG 0xc4
|
||||
#define RX1_CFG_RD_UPDATA_FLAG_REG 0xc3 //bit2 is avalid
|
||||
|
||||
void jesd204b_rd_test(void)
|
||||
{
|
||||
printf(" >>jesd204b_rd_test\n");
|
||||
uint32 data[10];
|
||||
fpga_read_axi0(0xB1,&data[0],1);
|
||||
fpga_read_axi0(0xB2,&data[1],1);
|
||||
fpga_read_axi0(0xB3,&data[2],1);
|
||||
fpga_read_axi0(0xB4,&data[3],1);
|
||||
fpga_read_axi0(0xB5,&data[4],1);
|
||||
fpga_read_axi0(0xB6,&data[5],1);
|
||||
fpga_read_axi0(0xB7,&data[6],1);
|
||||
fpga_read_axi0(0xB8,&data[7],1);
|
||||
printf(" rd [B1=0x%x B2=0x%x B3=0x%x B4=0x%x] [B7=0x%x B6=0x%x B8=0x%x B5=0x%x] \n",
|
||||
data[0],data[1],data[2],data[3], data[6],data[5],data[7],data[4]
|
||||
);
|
||||
usleep(1000);
|
||||
}
|
||||
|
||||
void jesd204b_tx0_wr(u32 addr,u32 dat)
|
||||
{
|
||||
printf(" >>W [jesd_wr_tx0] addr=0x%x data=0x%x\n", addr, dat);
|
||||
fpga_write_axi0(TX0_CFG_ADDR_H_REG,(addr>>8)&0xff,1);//B7
|
||||
fpga_write_axi0(TX0_CFG_ADDR_L_REG,addr&0xff,1);//B6
|
||||
fpga_write_axi0(TX0_CFG_WR_DATA_REG,dat,1);//B8
|
||||
fpga_write_axi0(TX0_CFG_ENABLE_REG,0x0,1);//B5
|
||||
fpga_write_axi0(TX0_CFG_ENABLE_REG,0x04,1);
|
||||
fpga_write_axi0(TX0_CFG_ENABLE_REG,0x0,1);
|
||||
usleep(1000);
|
||||
}
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
void jesd204b_fb0_wr(u32 addr,u32 dat) //验证OK
|
||||
{
|
||||
printf(" >>W [jesd_wr_fb0] addr=0x%x data=0x%x\n", addr, dat);
|
||||
/* FB0 bridge: 写时序 (Task11 §3.2)
|
||||
1. 写 FB0_CFG_ADDR_L_REG = addr[7:0] (0xBD)
|
||||
2. 写 FB0_CFG_ADDR_H_REG = addr[11:8] (0xBE)
|
||||
3. 写 FB0_CFG_WR_DATA_REG = dat[7:0] (0xBF, 仅8-bit 宽)
|
||||
4. 清 FB0_CFG_ENABLE_REG (0xBC)
|
||||
5. 置位 bit1 (wr) (0xBC = 0x02)
|
||||
6. 清 FB0_CFG_ENABLE_REG (0xBC = 0x00)
|
||||
*/
|
||||
fpga_write_axi0(FB0_CFG_ADDR_L_REG, addr & 0xFF, 1);
|
||||
fpga_write_axi0(FB0_CFG_ADDR_H_REG, (addr >> 8) & 0x0F, 1);
|
||||
fpga_write_axi0(FB0_CFG_WR_DATA_REG, dat & 0xFF, 1);
|
||||
fpga_write_axi0(FB0_CFG_ENABLE_REG, 0x00, 1);
|
||||
fpga_write_axi0(FB0_CFG_ENABLE_REG, 0x02, 1); // bit1 = wr
|
||||
fpga_write_axi0(FB0_CFG_ENABLE_REG, 0x00, 1);
|
||||
usleep(1000);
|
||||
}
|
||||
|
||||
u32 jesd204b_fb0_rd(u32 addr) //验证OK
|
||||
{
|
||||
u32 data = 0;
|
||||
u32 mon = 0;
|
||||
int timeout = 10;
|
||||
|
||||
/* FB0 bridge: 读时序 (Task11 §3.2)
|
||||
1. 写 FB0_CFG_ADDR_L_REG = addr[7:0] (0xBD)
|
||||
2. 写 FB0_CFG_ADDR_H_REG = addr[11:8] (0xBE)
|
||||
3. 清 FB0_CFG_ENABLE_REG (0xBC)
|
||||
4. 置位 bit0 (rd) (0xBC = 0x01)
|
||||
5. 清 FB0_CFG_ENABLE_REG (0xBC = 0x00)
|
||||
6. 等待 ~1ms
|
||||
7. 轮询 FB0_CFG_MON_REG bit2 (0xBB), 超时退出
|
||||
8. 读 0xC0~0xC3 组合为 32-bit (小端序)
|
||||
*/
|
||||
fpga_write_axi0(FB0_CFG_ADDR_L_REG, addr & 0xFF, 1);
|
||||
fpga_write_axi0(FB0_CFG_ADDR_H_REG, (addr >> 8) & 0x0F, 1);
|
||||
fpga_write_axi0(FB0_CFG_ENABLE_REG, 0x00, 1);
|
||||
fpga_write_axi0(FB0_CFG_ENABLE_REG, 0x01, 1); // bit0 = rd
|
||||
fpga_write_axi0(FB0_CFG_ENABLE_REG, 0x00, 1);
|
||||
|
||||
usleep(1000);
|
||||
|
||||
do {
|
||||
fpga_read_axi0(FB0_CFG_MON_REG, &mon, 1);
|
||||
if (mon & 0x04)
|
||||
break;
|
||||
usleep(1000);
|
||||
} while (--timeout > 0);
|
||||
|
||||
if (timeout <= 0) {
|
||||
printf(" >>R [jesd_rd_fb0] addr=0x%x TIMEOUT\n", addr);
|
||||
return 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
/* 读 4 字节并组合为小端序 32-bit 数据 */
|
||||
{
|
||||
u32 tmp;
|
||||
u8 c0, c1, c2, c3;
|
||||
|
||||
fpga_read_axi0(FB0_CFG_RD_DATA0_REG, &tmp, 1); c0 = tmp & 0xFF;
|
||||
fpga_read_axi0(FB0_CFG_RD_DATA1_REG, &tmp, 1); c1 = tmp & 0xFF;
|
||||
fpga_read_axi0(FB0_CFG_RD_DATA2_REG, &tmp, 1); c2 = tmp & 0xFF;
|
||||
fpga_read_axi0(FB0_CFG_RD_DATA3_REG, &tmp, 1); c3 = tmp & 0xFF;
|
||||
|
||||
data = ((u32)c3 << 24) | ((u32)c2 << 16) | ((u32)c1 << 8) | c0;
|
||||
}
|
||||
|
||||
printf(" >>R [jesd_rd_fb0] addr=0x%x data=0x%08x\n", addr, data);
|
||||
return data;
|
||||
}
|
||||
|
||||
void jesd204b_rx0_wr(u32 addr,u32 dat)
|
||||
{
|
||||
// printf(" >>W [jesd_rx_tx0] addr=0x%x data=0x%x\n", addr, dat);
|
||||
/*fpga_write_axi0(RX0_CFG_ADDR_REG,addr,1);
|
||||
fpga_write_axi0(RX0_CFG_WR_DATA_REG,dat,1);
|
||||
fpga_write_axi0(RX0_CFG_ENABLE_REG,0x0,1);
|
||||
fpga_write_axi0(RX0_CFG_ENABLE_REG,0x04,1);
|
||||
fpga_write_axi0(RX0_CFG_ENABLE_REG,0x0,1);
|
||||
usleep(1000);*/
|
||||
}
|
||||
|
||||
void jesd204b_tx1_wr(u32 addr,u32 dat)
|
||||
{
|
||||
// printf(" >>W [jesd_wr_tx1] addr=0x%x data=0x%x\n", addr, dat);
|
||||
/*fpga_write_axi0(TX1_CFG_ADDR_REG,addr,1);
|
||||
fpga_write_axi0(TX1_CFG_WR_DATA_REG,dat,1);
|
||||
fpga_write_axi0(TX1_CFG_ENABLE_REG,0x0,1);
|
||||
fpga_write_axi0(TX1_CFG_ENABLE_REG,0x04,1);
|
||||
fpga_write_axi0(TX1_CFG_ENABLE_REG,0x0,1);
|
||||
usleep(1000);*/
|
||||
}
|
||||
|
||||
void jesd204b_fb1_wr(u32 addr,u32 dat)
|
||||
{
|
||||
// printf(" >>W [jesd_wr_fb1] addr=0x%x data=0x%x\n", addr, dat);
|
||||
/*fpga_write_axi0(FB1_CFG_ADDR_REG,addr,1);
|
||||
fpga_write_axi0(FB1_CFG_WR_DATA_REG,dat,1);
|
||||
fpga_write_axi0(FB1_CFG_ENABLE_REG,0x0,1);
|
||||
fpga_write_axi0(FB1_CFG_ENABLE_REG,0x04,1);
|
||||
fpga_write_axi0(FB1_CFG_ENABLE_REG,0x0,1);
|
||||
usleep(1000);*/
|
||||
}
|
||||
|
||||
void jesd204b_rx1_wr(u32 addr,u32 dat)
|
||||
{
|
||||
// printf(" >>W [jesd_wr_rx1] addr=0x%x data=0x%x\n", addr, dat);
|
||||
/*fpga_write_axi0(RX1_CFG_ADDR_REG,addr,1);
|
||||
fpga_write_axi0(RX1_CFG_WR_DATA_REG,dat,1);
|
||||
fpga_write_axi0(RX1_CFG_ENABLE_REG,0x0,1);
|
||||
fpga_write_axi0(RX1_CFG_ENABLE_REG,0x04,1);
|
||||
fpga_write_axi0(RX1_CFG_ENABLE_REG,0x0,1);
|
||||
usleep(1000);*/
|
||||
}
|
||||
|
||||
|
||||
void jesd204b_tx0_cfg(void)
|
||||
{
|
||||
// printf("jesd204b_tx0_cfg start...\n");
|
||||
//initial
|
||||
fpga_write_axi0(TX0_CFG_ENABLE_REG,0x0,1);
|
||||
fpga_write_axi0(TX0_CFG_ADDR_H_REG,0x0,1);
|
||||
fpga_write_axi0(TX0_CFG_ADDR_L_REG,0x0,1);
|
||||
fpga_write_axi0(TX0_CFG_WR_DATA_REG,0x0,1);
|
||||
|
||||
|
||||
jesd204b_tx0_wr(0x04,0x01);
|
||||
jesd204b_tx0_wr(0x08,0x01);
|
||||
jesd204b_tx0_wr(0x0c,0x0);
|
||||
jesd204b_tx0_wr(0x10,0x00); /* PR06-2: SYSREF handling OFF (SMOD board has NO SYSREF wired) */
|
||||
jesd204b_tx0_wr(0x14,0x03);
|
||||
jesd204b_tx0_wr(0x18,0x0);
|
||||
jesd204b_tx0_wr(0x20,0x01);
|
||||
jesd204b_tx0_wr(0x24,0x1f);
|
||||
|
||||
jesd204b_tx0_wr(0x28,0x03); /* PR06-2: lanes-in-use mask = 2 lanes (was 0xf) */
|
||||
jesd204b_tx0_wr(0x2c,0x00); /* PR06-2: Subclass 0 (was 1) - no SYSREF -> align on SYNC~/ILAS only, avoids divergent LMFC phase -> fixes TX no-RF at mixed 60/120/120 rates */
|
||||
|
||||
jesd204b_tx0_wr(0x80c,0x01000a55);
|
||||
jesd204b_tx0_wr(0x810,0x000f0d03);
|
||||
|
||||
jesd204b_tx0_wr(0x814,0x0);
|
||||
jesd204b_tx0_wr(0x818,0x0);
|
||||
jesd204b_tx0_wr(0x81c,0x0);
|
||||
|
||||
printf("jesd204b_tx0_cfg done.\n");
|
||||
}
|
||||
|
||||
|
||||
void jesd204b_fb0_cfg(void)
|
||||
{
|
||||
printf("jesd204b_fb0_cfg start...\n");
|
||||
/* PR06-2 ORx-only: o_fb 核走 IP 默认(F=2/2lane) 匹配 ADRV framerB(M=2/2lane/120M), 不写寄存器 */
|
||||
printf("jesd204b_fb0_cfg done.\n");
|
||||
}
|
||||
|
||||
void jesd204b_rx0_cfg(void)
|
||||
{
|
||||
printf("jesd204b_rx0_cfg start...\n");
|
||||
//PR06-2: 取消注释并配 RX0(framerA/RX1) 核为 subclass 0 匹配 ADRV framerA(M=4/F=4/2lane) + 无SYSREF
|
||||
fpga_write_axi0(RX0_CFG_ENABLE_REG,0x0,1);
|
||||
fpga_write_axi0(RX0_CFG_ADDR_REG,0x0,1);
|
||||
fpga_write_axi0(RX0_CFG_WR_DATA_REG,0x0,1);
|
||||
|
||||
jesd204b_rx0_wr(0x04,0x01);
|
||||
jesd204b_rx0_wr(0x08,0x01);
|
||||
jesd204b_rx0_wr(0x0C,0x0);
|
||||
|
||||
jesd204b_rx0_wr(0x10,0x00); /* PR06-2: SYSREF off */
|
||||
jesd204b_rx0_wr(0x18,0x0);
|
||||
jesd204b_rx0_wr(0x20,0x03); /* F-1=3 -> F=4 */
|
||||
jesd204b_rx0_wr(0x24,0x1f); /* K-1=31 -> K=32 */
|
||||
jesd204b_rx0_wr(0x28,0x03); /* PR06-2 ORx-only: 2 lanes (回退, o_rx核未用) */
|
||||
jesd204b_rx0_wr(0x2c,0x00); /* PR06-2: Subclass 0 (无SYSREF) */
|
||||
jesd204b_rx0_wr(0x30,0x0);
|
||||
jesd204b_rx0_wr(0x34,0x0);
|
||||
|
||||
printf("jesd204b_rx0_cfg done\n");
|
||||
}
|
||||
|
||||
|
||||
void jesd204b_tx1_cfg(void)
|
||||
{
|
||||
//initial
|
||||
/*fpga_write_axi0(TX1_CFG_ENABLE_REG,0x0,1);
|
||||
fpga_write_axi0(TX1_CFG_ADDR_REG,0x0,1);
|
||||
fpga_write_axi0(TX1_CFG_WR_DATA_REG,0x0,1);
|
||||
|
||||
jesd204b_tx1_wr(0x04,0x01);
|
||||
jesd204b_tx1_wr(0x08,0x01);
|
||||
jesd204b_tx1_wr(0x0c,0x0);
|
||||
jesd204b_tx1_wr(0x10,0x01);
|
||||
jesd204b_tx1_wr(0x14,0x03);
|
||||
jesd204b_tx1_wr(0x18,0x0);
|
||||
jesd204b_tx1_wr(0x20,0x01);
|
||||
jesd204b_tx1_wr(0x24,0x1f);
|
||||
jesd204b_tx1_wr(0x28,0x0f);
|
||||
jesd204b_tx1_wr(0x2c,0x01);
|
||||
jesd204b_tx1_wr(0x80c,0x01000a55);
|
||||
jesd204b_tx1_wr(0x810,0x000f0d03);
|
||||
|
||||
jesd204b_tx1_wr(0x814,0x0);
|
||||
jesd204b_tx1_wr(0x818,0x0);
|
||||
jesd204b_tx1_wr(0x81c,0x0);*/
|
||||
|
||||
|
||||
}
|
||||
|
||||
void jesd204b_fb1_cfg(void)
|
||||
{
|
||||
//initial
|
||||
/*fpga_write_axi0(FB1_CFG_ENABLE_REG,0x0,1);
|
||||
fpga_write_axi0(FB1_CFG_ADDR_REG,0x0,1);
|
||||
fpga_write_axi0(FB1_CFG_WR_DATA_REG,0x0,1);
|
||||
|
||||
jesd204b_fb1_wr(0x04,0x01);
|
||||
jesd204b_fb1_wr(0x08,0x01);
|
||||
jesd204b_fb1_wr(0x0C,0x0);
|
||||
jesd204b_fb1_wr(0x10,0x01);
|
||||
jesd204b_fb1_wr(0x18,0x0);
|
||||
jesd204b_fb1_wr(0x20,0x01);
|
||||
jesd204b_fb1_wr(0x24,0x1f);
|
||||
jesd204b_fb1_wr(0x28,0x03);
|
||||
jesd204b_fb1_wr(0x2c,0x01);
|
||||
jesd204b_fb1_wr(0x30,0x0);
|
||||
jesd204b_fb1_wr(0x34,0x0);*/
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
void jesd204b_rx1_cfg(void)
|
||||
{
|
||||
//initial
|
||||
/*fpga_write_axi0(RX1_CFG_ENABLE_REG,0x0,1);
|
||||
fpga_write_axi0(RX1_CFG_ADDR_REG,0x0,1);
|
||||
fpga_write_axi0(RX1_CFG_WR_DATA_REG,0x0,1);
|
||||
|
||||
jesd204b_rx1_wr(0x04,0x01);
|
||||
jesd204b_rx1_wr(0x08,0x01);
|
||||
jesd204b_rx1_wr(0x0C,0x0);
|
||||
|
||||
jesd204b_rx1_wr(0x10,0x01);
|
||||
jesd204b_rx1_wr(0x18,0x0);
|
||||
jesd204b_rx1_wr(0x20,0x03);
|
||||
jesd204b_rx1_wr(0x24,0x1f);
|
||||
jesd204b_rx1_wr(0x28,0x03);
|
||||
jesd204b_rx1_wr(0x2c,0x01);
|
||||
jesd204b_rx1_wr(0x30,0x0);
|
||||
jesd204b_rx1_wr(0x34,0x0);*/
|
||||
}
|
||||
|
||||
/*
|
||||
//add 260427
|
||||
//0xB1 — JESD_CTRL（链路复位控制）
|
||||
bit 名称 默认 说明
|
||||
7 RX_GT_RST1 0 RX GT 复位通道 1（写 1 复位，写 0 释放）
|
||||
6 RX_GT_RST0 0 RX GT 复位通道 0（写 1 复位，写 0 释放）
|
||||
5 TX_GT_RST 0 TX GT（收发器）复位（写 1 复位，写 0 释放）
|
||||
4 FBRX_RST 0 Feedback RX 链路复位（写 1 复位，写 0 释放）
|
||||
3 RX_RST 0 RX 链路复位（写 1 复位，写 0 释放）
|
||||
2 TX_RST 0 TX 链路复位（写 1 复位，写 0 释放）
|
||||
1 PHY_RST 0 PHY 全局复位（写 1 复位，写 0 释放）
|
||||
0 AXI_RST 0 AXI 总线复位（写 1 复位，写 0 释放）
|
||||
典型复位序列（JESD 链路重新初始化）：
|
||||
|
||||
1. 写 0xB1 = 0xFF // 全部复位
|
||||
2. 延时 ≥ 1ms
|
||||
3. 写 0xB1 = 0x00 // 释放所有复位
|
||||
4. 等待 0xB4[0] = 1 // 轮询 TX 就绪
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 执行 JESD204B 链路软复位序列
|
||||
* @note 对应寄存器 0xB1 JESD_CTRL
|
||||
*/
|
||||
void jesd204b_reset_add(void)
|
||||
{
|
||||
uint8_t status = 0;
|
||||
int timeout = 10000; // 防止死循环的超时计数
|
||||
|
||||
// 1. 写 0xB1 = 0xFF -> 全部复位
|
||||
// 注意：这里假设 fpga_byte_write 的参数顺序是 (基地址, 偏移地址, 数据)
|
||||
// 原代码中的 (addr)&0xff 看起来像是笔误，这里修正为直接写入 0xFF
|
||||
fpga_byte_write(JESD_SEG_ADDR, 0xB1, 0xFF);
|
||||
|
||||
// 2. 延时 ≥ 1ms
|
||||
// 根据你的系统环境选择延时函数，如 usleep, delay_ms 等
|
||||
usleep(2000); // 建议稍微多给一点余量，这里延时 2ms
|
||||
|
||||
// 3. 写 0xB1 = 0x00 -> 释放所有复位
|
||||
fpga_byte_write(JESD_SEG_ADDR, 0xB1, 0x00);
|
||||
|
||||
// 4. 等待 0xB4[0] = 1 -> 轮询 TX 就绪
|
||||
// 假设 0xB4 是状态寄存器，Bit 0 为 1 表示 TX 准备好
|
||||
do {
|
||||
status = fpga_byte_read(JESD_SEG_ADDR, 0xB4);
|
||||
timeout--;
|
||||
usleep(10);
|
||||
} while (((status & 0x01) == 0) && (timeout > 0));
|
||||
|
||||
if (timeout <= 0) {
|
||||
// 处理超时错误（可选）
|
||||
printf("JESD Reset Timeout!\n");
|
||||
}
|
||||
else{
|
||||
printf("JESD Reset Done!\n");
|
||||
}
|
||||
}
|
||||
|
||||
Executable
+27
@@ -0,0 +1,27 @@
|
||||
#ifndef _JESD204B_CONFIG_H_
|
||||
#define _JESD204B_CONFIG_H_
|
||||
|
||||
|
||||
void jesd204b_tx0_wr(u32 addr,u32 dat);
|
||||
void jesd204b_fb0_wr(u32 addr,u32 dat);
|
||||
void jesd204b_rx0_wr(u32 addr,u32 dat);
|
||||
void jesd204b_tx1_wr(u32 addr,u32 dat);
|
||||
void jesd204b_fb1_wr(u32 addr,u32 dat);
|
||||
void jesd204b_rx1_wr(u32 addr,u32 dat);
|
||||
|
||||
void jesd204b_tx0_cfg(void);
|
||||
void jesd204b_fb0_cfg(void);
|
||||
void jesd204b_rx0_cfg(void);
|
||||
void jesd204b_tx1_cfg(void);
|
||||
void jesd204b_fb1_cfg(void);
|
||||
void jesd204b_rx1_cfg(void);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
Executable
+9561
File diff suppressed because it is too large
Load Diff
Executable
+52
@@ -0,0 +1,52 @@
|
||||
/**
|
||||
* \file talise_config.h
|
||||
* \brief Talise configuration external declarations
|
||||
*
|
||||
* \brief Contains structure definitions for tal_config.c
|
||||
*
|
||||
* Copyright 2015-2017 Analog Devices Inc.
|
||||
* Released under the AD9378-AD9379 API license, for more information see the "LICENSE.txt" file in this zip file.
|
||||
*
|
||||
* The top level structure taliseDevice_t talDevice uses keyword
|
||||
* extern to allow the application layer main() to have visibility
|
||||
* to these settings.
|
||||
*/
|
||||
|
||||
#ifndef TAL_INIT_H_
|
||||
#define TAL_INIT_H_
|
||||
|
||||
#include "../talise/talise_types.h"
|
||||
#include "../talise/talise_error.h"
|
||||
#include "../talise/talise_agc.h"
|
||||
#include "../talise/talise_arm_types.h"
|
||||
#include "../talise/talise_arm.h"
|
||||
#include "../talise/talise.h"
|
||||
#include "../talise/talise_radioctrl.h"
|
||||
#include "../talise/talise_cals.h"
|
||||
#include "../talise/talise_jesd204.h"
|
||||
#include "../talise/talise_rx_types.h"
|
||||
#include "../talise/talise_rx.h"
|
||||
#include "../talise/talise_tx_types.h"
|
||||
#include "../talise/talise_tx.h"
|
||||
#include "../talise/talise_gpio_types.h"
|
||||
#include "../talise/talise_gpio.h"
|
||||
#include "../talise/talise_error_types.h"
|
||||
typedef struct {
|
||||
taliseDevice_t *ptalDevice;
|
||||
taliseInit_t *ptalInit;
|
||||
}taliseDeviceInfo;
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern taliseDeviceInfo taliseDeviceInfo1;
|
||||
extern taliseDeviceInfo taliseDeviceInfo2;
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Executable
+421
@@ -0,0 +1,421 @@
|
||||
/**
|
||||
* \file talise_config.c
|
||||
* \brief Contains Talise configuration settings for the Talise API
|
||||
*
|
||||
* Copyright 2015-2017 Analog Devices Inc.
|
||||
* Released under the AD9378-AD9379 API license, for more information see the "LICENSE.txt" file in this zip file.
|
||||
*
|
||||
* The top level structure taliseDevice_t talDevice uses keyword
|
||||
* extern to allow the application layer main() to have visibility
|
||||
* to these settings.
|
||||
*
|
||||
* This file may not be fully complete for the end user application and
|
||||
* may need to updated for AGC, GPIO, and DAC full scale settings.
|
||||
* To create a full initialisation routine, the user should also refer to the
|
||||
* Iron Python initialisation routine generated by the GUI, and also the Talise User Guide.
|
||||
*
|
||||
*/
|
||||
|
||||
//#include "talise_types.h"
|
||||
//#include "talise_config_1.h"
|
||||
//#include "talise_error.h"
|
||||
//#include "talise_agc.h"
|
||||
#ifdef ADI_ZYNQ_PLATFORM
|
||||
#include "zynq_platform.h"
|
||||
#endif
|
||||
|
||||
#include "talise_config.h"
|
||||
|
||||
|
||||
#if 1//_HJX_CONFIG_ modify
|
||||
static int16_t txFirCoefs[80] = {0, 0, 0, 0, 0, 0, 1, 0, -3, 1, 8, -2, -20, 5, 43, -10, -85, 19, 158, -34, -272, 61, 463, -62, -702, 71, 1044, -36, -1482, -64, 2044, 302, -2770, -803, 3786, 1895, -5503, -4768, 10723, 27650, 27650, 10723, -4768, -5503, 1895, 3786, -803, -2770, 302, 2044, -64, -1482, -36, 1044, 71, -702, -62, 463, 61, -272, -34, 158, 19, -85, -10, 43, 5, -20, -2, 8, 1, -3, 0, 1, 0, 0, 0, 0, 0, 0};
|
||||
|
||||
static int16_t rxFirCoefs[72] = {0, 0, -1, -2, -4, -2, 5, 17, 27, 21, -12, -67, -114, -105, -2, 181, 354, 375, 133, -350, -858, -1043, -606, 462, 1737, 2456, 1880, -215, -3172, -5492, -5359, -1489, 6092, 15765, 24755, 30169, 30169, 24755, 15765, 6092, -1489, -5359, -5492, -3172, -215, 1880, 2456, 1737, 462, -606, -1043, -858, -350, 133, 375, 354, 181, -2, -105, -114, -67, -12, 21, 27, 17, 5, -2, -4, -2, -1, 0, 0};
|
||||
|
||||
static int16_t obsrxFirCoefs[72] = {-3, 10, 15, 8, -18, -41, -29, 29, 86, 76, -29, -154, -166, 1, 239, 316, 83, -328, -541, -260, 393, 856, 581, -393, -1287, -1145, 236, 1855, 2111, 196, -2816, -4260, -1648, 5281, 13824, 19693, 19693, 13824, 5281, -1648, -4260, -2816, 196, 2111, 1855, 236, -1145, -1287, -393, 581, 856, 393, -260, -541, -328, 83, 316, 239, 1, -166, -154, -29, 76, 86, 29, -29, -41, -18, 8, 15, 10, -3}; /* PR06-2: TES 120M obsRx 72抽头(相干) */
|
||||
|
||||
#ifdef ADI_ZYNQ_PLATFORM /** < Insert Customer Platform HAL State Container here>*/
|
||||
/*
|
||||
* Platform Layer SPI settings - this structure is specific to ADI's platform layer code.
|
||||
* User should replace with their own structure or settings for their hardware
|
||||
*/
|
||||
zynqSpiSettings_t spiDev1 =
|
||||
{
|
||||
.chipSelectIndex = 1,
|
||||
.writeBitPolarity = 0,
|
||||
.longInstructionWord = 1,
|
||||
.CPHA = 0,
|
||||
.CPOL = 0,
|
||||
.mode = 0,
|
||||
.spiClkFreq_Hz = 25000000
|
||||
};
|
||||
|
||||
/*
|
||||
* Platform Layer settings - this structure is specific to ADI's platform layer code.
|
||||
* User should replace with their own structure or settings for their hardware
|
||||
* The structure is held in taliseDevice_t below as a void pointer, allowing
|
||||
* the customer to pass any information for their specific hardware down to the
|
||||
* hardware layer code.
|
||||
*/
|
||||
zynqAdiDev_t talDevHalInfo =
|
||||
{
|
||||
.devIndex = 1,
|
||||
.spiSettings = &spiDev1,
|
||||
.spiErrCode = 0,
|
||||
.timerErrCode = 0,
|
||||
.gpioErrCode = 0,
|
||||
.logLevel = ADIHAL_LOG_ALL
|
||||
};
|
||||
#endif
|
||||
/**
|
||||
* TalDevice a structure used by the Talise API to hold the platform hardware
|
||||
* structure information, as well as an internal Talise API state container
|
||||
* (devStateInfo) of runtime information used by the API.
|
||||
**/
|
||||
|
||||
|
||||
//---------------------------------------
|
||||
#define SCRAMBLE_USR 0
|
||||
//---------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
static taliseInit_t talInit =
|
||||
{//ref_from 7g 2lan start
|
||||
/* SPI settings */
|
||||
.spiSettings =
|
||||
{
|
||||
.MSBFirst = 1, /* 1 = MSBFirst, 0 = LSBFirst */
|
||||
.enSpiStreaming = 0, /* Not implemented in ADIs platform layer. SW feature to improve SPI throughput */
|
||||
.autoIncAddrUp = 1, /* Not implemented in ADIs platform layer. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr=addr-1 */
|
||||
.fourWireMode = 1, /* 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode */
|
||||
.cmosPadDrvStrength = TAL_CMOSPAD_DRV_2X /* Drive strength of CMOS pads when used as outputs (SDIO, SDO, GP_INTERRUPT, GPIO 1, GPIO 0) */
|
||||
},
|
||||
|
||||
/* Rx settings */
|
||||
.rx =
|
||||
{
|
||||
.rxProfile =
|
||||
{
|
||||
.rxFir =
|
||||
{
|
||||
.gain_dB = -6, /* filter gain */
|
||||
.numFirCoefs = 72, /* number of coefficients in the FIR filter */
|
||||
.coefs = &rxFirCoefs[0]
|
||||
},
|
||||
.rxFirDecimation = 4, /* Rx FIR decimation (1,2,4) - PR06-2: 4 for 60M out */
|
||||
.rxDec5Decimation = 4, /* Decimation of Dec5 or Dec4 filter (5,4) */
|
||||
.rhb1Decimation = 2, /* RX Half band 1 decimation (1 or 2) */
|
||||
.rxOutputRate_kHz = 60000, /* Rx IQ data rate in kHz - PR06-2: 120->60M */
|
||||
.rfBandwidth_Hz = 30000000, /* The Rx RF passband bandwidth for the profile - PR06-2: 60->30M */
|
||||
.rxBbf3dBCorner_kHz = 100000, /* Rx BBF 3dB corner in kHz */
|
||||
.rxAdcProfile = {272, 150, 181, 90, 1280, 366, 1256, 27, 1228, 17, 701, 39, 48, 45, 27, 161, 0, 0, 0, 0, 40, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905}, /* pointer to custom ADC profile */
|
||||
.rxDdcMode = TAL_RXDDC_BYPASS, /* Rx DDC mode */
|
||||
.rxNcoShifterCfg =
|
||||
{
|
||||
.bandAInputBandWidth_kHz = 0,
|
||||
.bandAInputCenterFreq_kHz = 0,
|
||||
.bandANco1Freq_kHz = 0,
|
||||
.bandANco2Freq_kHz = 0,
|
||||
.bandBInputBandWidth_kHz = 0,
|
||||
.bandBInputCenterFreq_kHz = 0,
|
||||
.bandBNco1Freq_kHz = 0,
|
||||
.bandBNco2Freq_kHz = 0
|
||||
}
|
||||
},
|
||||
.framerSel = TAL_FRAMER_A, /* Rx JESD204b framer configuration */
|
||||
.rxGainCtrl =
|
||||
{
|
||||
.gainMode = TAL_MGC, /* taliserxGainMode_t gainMode */
|
||||
.rx1GainIndex = 210, /* PR06-2: 降增益去饱和(255满量程削顶); 电缆TX信号强 */
|
||||
.rx2GainIndex = 255, /* uint8_t rx2GainIndex */
|
||||
.rx1MaxGainIndex = 255, /* uint8_t rx1MaxGainIndex */
|
||||
.rx1MinGainIndex = 195, /* uint8_t rx1MinGainIndex (gain table hard floor) */
|
||||
.rx2MaxGainIndex = 255, /* uint8_t rx2MaxGainIndex */
|
||||
.rx2MinGainIndex = 195 /* uint8_t rx2MinGainIndex */
|
||||
},
|
||||
.rxChannels = TAL_RX1, /* PR06-2 统一M=2: 1通道RX1(匹配TES profile Rx_OR60 + DTMB). RX1 I/Q 从 o_fb tdata[31:0] 提取 */
|
||||
},
|
||||
|
||||
|
||||
/* Tx settings */
|
||||
.tx =
|
||||
{
|
||||
.txProfile =
|
||||
{
|
||||
.dacDiv = 1, /* The divider used to generate the DAC clock */
|
||||
.txFir =
|
||||
{
|
||||
.gain_dB = 0, /* filter gain */
|
||||
.numFirCoefs = 80, /* number of coefficients in the FIR filter - PR06-2: 20->80 (TES 120M) */
|
||||
.coefs = &txFirCoefs[0]
|
||||
},
|
||||
.txFirInterpolation = 2, /* The Tx digital FIR filter interpolation (1,2,4) - PR06-2: 1->2 for 120M in */
|
||||
.thb1Interpolation = 2, /* Tx Halfband1 filter interpolation (1,2) */
|
||||
.thb2Interpolation = 2, /* Tx Halfband2 filter interpolation (1,2)*/
|
||||
.thb3Interpolation = 2, /* Tx Halfband3 filter interpolation (1,2)*/
|
||||
.txInt5Interpolation = 1, /* Tx Int5 filter interpolation (1,5) */
|
||||
.txInputRate_kHz = 120000, /* Primary Signal BW - PR06-2: 240->120M */
|
||||
.primarySigBandwidth_Hz = 40000000, /* The Rx RF passband bandwidth for the profile - PR06-2: 60->40M */
|
||||
.rfBandwidth_Hz = 80000000, /* The Tx RF passband bandwidth for the profile - PR06-2: 120->80M */
|
||||
.txDac3dBCorner_kHz = 200000, /* The DAC filter 3dB corner in kHz */
|
||||
.txBbf3dBCorner_kHz = 100000, /* The BBF 3dB corner in kHz */
|
||||
.loopBackAdcProfile = {269, 149, 181, 90, 1280, 378, 1258, 28, 1235, 17, 710, 39, 48, 45, 27, 163, 0, 0, 0, 0, 41, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905}
|
||||
},
|
||||
.deframerSel = TAL_DEFRAMER_A, /* Talise JESD204b deframer config for the Tx data path */
|
||||
.txChannels = TAL_TX1, /* The desired Tx channels to enable during initialization */
|
||||
.txAttenStepSize = TAL_TXATTEN_0P05_DB, /* Tx Attenuation step size */
|
||||
.tx1Atten_mdB = 0, /* PR06-2 修复②: TX满功率(同260702), 强化ORx环回观测 */
|
||||
.tx2Atten_mdB = 0, /* Initial Tx2 Attenuation */
|
||||
.disTxDataIfPllUnlock = TAL_TXDIS_TX_RAMP_DOWN_TO_ZERO /* Options to disable the transmit data when the RFPLL unlocks. */
|
||||
},
|
||||
|
||||
|
||||
/* ObsRx settings */
|
||||
.obsRx =
|
||||
{
|
||||
.orxProfile =
|
||||
{
|
||||
.rxFir =
|
||||
{
|
||||
.gain_dB = 0, /* PR06-2 修复③: obsRx FIR gain 0(同260702), 补回6dB数字增益 */
|
||||
.numFirCoefs = 72, /* PR06-2: TES 120M obsRx 72抽头 */
|
||||
.coefs = &obsrxFirCoefs[0]
|
||||
},
|
||||
.rxFirDecimation = 2, /* Rx FIR decimation (1,2,4) */
|
||||
.rxDec5Decimation = 4, /* Decimation of Dec5 or Dec4 filter (5,4) */
|
||||
.rhb1Decimation = 2, /* PR06-2: HB1 dec2 (120M out, 2.4G GT) */
|
||||
.orxOutputRate_kHz = 120000, /* PR06-2: ORx 120M (2.4G GT) */
|
||||
.rfBandwidth_Hz = 60000000, /* The Rx RF passband bandwidth for the profile */
|
||||
.rxBbf3dBCorner_kHz = 225000, /* Rx BBF 3dB corner in kHz */
|
||||
.orxLowPassAdcProfile = {272, 150, 181, 90, 1280, 366, 1256, 27, 1228, 17, 701, 39, 48, 45, 27, 161, 0, 0, 0, 0, 40, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905},
|
||||
.orxBandPassAdcProfile = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
.orxDdcMode = TAL_ORXDDC_DISABLED, /* ORx DDC mode */
|
||||
.orxMergeFilter = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
|
||||
},
|
||||
.orxGainCtrl =
|
||||
{
|
||||
.gainMode = TAL_MGC,
|
||||
.orx1GainIndex = 255,
|
||||
.orx2GainIndex = 255,
|
||||
.orx1MaxGainIndex = 255,
|
||||
.orx1MinGainIndex = 195,
|
||||
.orx2MaxGainIndex = 255,
|
||||
.orx2MinGainIndex = 195
|
||||
},
|
||||
.framerSel = TAL_FRAMER_B, /* ObsRx JESD204b framer configuration */
|
||||
.obsRxChannelsEnable = TAL_ORX1, /* PR06-2 ORx模式(golden): ORx1 观测 TX */
|
||||
.obsRxLoSource = TAL_OBSLO_RF_PLL /* The ORx mixers can use the TX_PLL */
|
||||
},
|
||||
|
||||
/* Digital Clock Settings */
|
||||
.clocks =
|
||||
{
|
||||
.deviceClock_kHz = 120000, /* CLKPLL and device reference clock frequency in kHz */
|
||||
.clkPllVcoFreq_kHz = 9600000, /* CLKPLL VCO frequency in kHz */
|
||||
.clkPllHsDiv = TAL_HSDIV_2P5, /* CLKPLL high speed clock divider */
|
||||
.rfPllUseExternalLo = 0, /* 1= Use external LO for RF PLL, 0 = use internal LO generation for RF PLL */
|
||||
.rfPllPhaseSyncMode = TAL_RFPLLMCS_NOSYNC /* RFPLL MCS (Phase sync) mode */
|
||||
},
|
||||
|
||||
/* JESD204B settings */
|
||||
.jesd204Settings =
|
||||
{
|
||||
/* Framer A settings */
|
||||
.framerA =
|
||||
{
|
||||
.bankId = 1, /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15) */
|
||||
.deviceId = 0, /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */
|
||||
.lane0Id = 0, /* JESD204B Configuration starting Lane ID. If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */
|
||||
.M = 2, /* PR06-2 统一M=2(匹配TES profile Rx_OR60 + FB核C_DEFAULT_F=2 + DTMB). o_fb tdata[15:0]=RX1_I,[31:16]=RX1_Q */
|
||||
.K = 32, /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */
|
||||
.F = 4, /* PR06-2 ORx模式(DTMB): framerA M=2/1lane(0x04) -> F=4, 让位给framerB */
|
||||
.Np = 16, /* Np (converter sample resolution) */
|
||||
.scramble = SCRAMBLE_USR, /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */
|
||||
.externalSysref = 0, /* 0=use internal SYSREF, 1= use external SYSREF (SMOD: NO external SYSREF wired) */
|
||||
.serializerLanesEnabled = 0x04, /* PR06-2 ORx-only: framerA/RX1 到 lane2(未接线, 关闭), 让出 SERDOUT0/1 给 framerB/ORx */
|
||||
.serializerLaneCrossbar = 0xE4, /* serializerLaneCrossbar */
|
||||
.lmfcOffset = 31, /* lmfcOffset - LMFC offset value for deterministic latency setting */
|
||||
.newSysrefOnRelink = 0, /* newSysrefOnRelink */
|
||||
.syncbInSelect = 0, /* syncbInSelect; */
|
||||
.overSample = 0, /* 1=overSample, 0=bitRepeat */
|
||||
.syncbInLvdsMode = 1,
|
||||
.syncbInLvdsPnInvert = 0,
|
||||
.enableManualLaneXbar = 0 /* 0=auto, 1=manual */
|
||||
},
|
||||
/* Framer B settings */
|
||||
.framerB =
|
||||
{
|
||||
.bankId = 0, /* golden ORx */
|
||||
.deviceId = 0, /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */
|
||||
.lane0Id = 0, /* JESD204B Configuration starting Lane ID. If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */
|
||||
.M = 2, /* PR06-2 ORx-only: ORx M=2 (o_fb tdata[15:0]=ORx1_I,[31:16]=ORx1_Q) */
|
||||
.K = 32, /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */
|
||||
.F = 2, /* PR06-2 ORx-only: F=2 (M=2/2lane, 120M) */
|
||||
.Np = 16, /* Np (converter sample resolution) */
|
||||
.scramble = SCRAMBLE_USR, /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */
|
||||
.externalSysref = 0, /* 0=use internal SYSREF (SMOD: NO external SYSREF wired) */
|
||||
.serializerLanesEnabled = 0x03, /* PR06-2 ORx-only: framerB/ORx 用 SERDOUT0/1(2 lane, 120M) */
|
||||
.serializerLaneCrossbar = 0xE4, /* serializerLaneCrossbar */
|
||||
.lmfcOffset = 31, /* lmfcOffset - LMFC offset value for deterministic latency setting */
|
||||
.newSysrefOnRelink = 0, /* newSysrefOnRelink */
|
||||
.syncbInSelect = 1, /* golden ORx: syncbInSelect=1 */
|
||||
.overSample = 0, /* 1=overSample, 0=bitRepeat */
|
||||
.syncbInLvdsMode = 1,
|
||||
.syncbInLvdsPnInvert = 0,
|
||||
.enableManualLaneXbar = 0 /* 0=auto, 1=manual */
|
||||
},
|
||||
/* Deframer A settings */
|
||||
.deframerA =
|
||||
{
|
||||
.bankId = 0, /* bankId extension to Device ID (Valid 0..15) */
|
||||
.deviceId = 0, /* deviceId link identification number. (Valid 0..255) */
|
||||
.lane0Id = 0, /* lane0Id Lane0 ID. (Valid 0..31) */
|
||||
.M = 2, /* M number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
|
||||
.K = 32, /* K #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */
|
||||
.scramble = SCRAMBLE_USR, /* scramble scrambling off if scramble= 0 */
|
||||
.externalSysref = 0, /* 0=use internal SYSREF (SMOD: NO external SYSREF wired) */
|
||||
.deserializerLanesEnabled = 0x03, /* deserializerLanesEnabled bit per lane, [0] = Lane0 enabled */
|
||||
.deserializerLaneCrossbar = 0xE4, /* deserializerLaneCrossbar */
|
||||
.lmfcOffset = 17, /* lmfcOffset LMFC offset value to adjust deterministic latency */
|
||||
.newSysrefOnRelink = 0, /* newSysrefOnRelink */
|
||||
.syncbOutSelect = 0, /* SYNCBOUT0/1 select */
|
||||
.Np = 16, /* Np (converter sample resolution) */
|
||||
.syncbOutLvdsMode = 1,
|
||||
.syncbOutLvdsPnInvert = 0,
|
||||
.syncbOutCmosSlewRate = 0,
|
||||
.syncbOutCmosDriveLevel = 0,
|
||||
.enableManualLaneXbar = 0 /* 0=auto, 1=manual */
|
||||
},
|
||||
/* Deframer B settings */
|
||||
.deframerB =
|
||||
{
|
||||
.bankId = 0, /* bankId extension to Device ID (Valid 0..15) */
|
||||
.deviceId = 0, /* deviceId link identification number. (Valid 0..255) */
|
||||
.lane0Id = 0, /* lane0Id Lane0 ID. (Valid 0..31) */
|
||||
.M = 0, /* M number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
|
||||
.K = 32, /* K #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */
|
||||
.scramble = SCRAMBLE_USR, /* scramble scrambling off if scramble= 0 */
|
||||
.externalSysref = 1, /* externalSysref 0= use internal SYSREF, 1= external SYSREF */
|
||||
.deserializerLanesEnabled = 0x00, /* deserializerLanesEnabled bit per lane, [0] = Lane0 enabled */
|
||||
.deserializerLaneCrossbar = 0xE4, /* deserializerLaneCrossbar */
|
||||
.lmfcOffset = 0, /* lmfcOffset LMFC offset value to adjust deterministic latency */
|
||||
.newSysrefOnRelink = 0, /* newSysrefOnRelink */
|
||||
.syncbOutSelect = 1, /* SYNCBOUT0/1 select */
|
||||
.Np = 16, /* Np (converter sample resolution) */
|
||||
.syncbOutLvdsMode = 1,
|
||||
.syncbOutLvdsPnInvert = 0,
|
||||
.syncbOutCmosSlewRate = 0,
|
||||
.syncbOutCmosDriveLevel = 0,
|
||||
.enableManualLaneXbar = 0 /* 0=auto, 1=manual */
|
||||
},
|
||||
.serAmplitude = 15, /* Serializer amplitude setting. Default = 15. Range is 0..15 */
|
||||
.serPreEmphasis = 1, /* Serializer pre-emphasis setting. Default = 1 Range is 0..4 */
|
||||
.serInvertLanePolarity = 0, /* Serializer Lane PN inversion select. Default = 0. Where, bit[0] = 1 will invert lane [0], bit[1] = 1 will invert lane 1, etc. */
|
||||
.desInvertLanePolarity = 0, /* Deserializer Lane PN inversion select. bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc */
|
||||
.desEqSetting = 1, /* Deserializer Equalizer setting. Applied to all deserializer lanes. Range is 0..4 */
|
||||
.sysrefLvdsMode = 1, /* Use LVDS inputs on Talise for SYSREF */
|
||||
.sysrefLvdsPnInvert = 0 /*0= Do not PN invert SYSREF */
|
||||
}
|
||||
};
|
||||
|
||||
#endif //ref_from 7g 2lan end
|
||||
|
||||
//Only needs to be called if user wants to setup AGC parameters
|
||||
static taliseAgcCfg_t rxAgcCtrl =
|
||||
{
|
||||
4,
|
||||
255,
|
||||
195,
|
||||
255,
|
||||
195,
|
||||
30720, /* AGC gain update time in us (125us-250us - based on IQ data rate - set for 125us @ 245.76 Mhz) */
|
||||
10,
|
||||
10,
|
||||
16,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
31,
|
||||
246,
|
||||
4,
|
||||
1, /*!<1- bit field to enable the multiple time constants in AGC loop for fast attack and fast recovery to max gain. */
|
||||
/* agcPower */
|
||||
{
|
||||
1, /*!<1-bit field, enables the Rx power measurement block. */
|
||||
1, /*!<1-bit field, allows using Rx PFIR for power measurement. */
|
||||
0, /*!<1-bit field, allows to use the output of the second digital offset block in the Rx datapath for power measurement. */
|
||||
9, /*!<AGC power measurement detect lower 0 threshold. Default = -12dBFS == 5, 7-bit register value where max = 0x7F, min = 0x00 */
|
||||
2, /*!<AGC power measurement detect lower 1 threshold. Default = (offset) 4dB == 0, 4-bit register value where max = 0xF, min = 0x00 */
|
||||
4, /*!<AGC power measurement detect lower 0 recovery gain step. Default = 2dB - based on gain table step size, 5-bit register value where max = 0x1F, min = 0x00 */
|
||||
4, /*!<AGC power measurement detect lower 1 recovery gain step. Default = 4dB - based on gain table step size, 5-bit register value where max = 0x1F, min = 0x00 */
|
||||
5, /*!< power measurement duration used by the decimated power block. Default = 0x05, 5-bit register value where max = 0x1F, min = 0x00 */
|
||||
5, /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
|
||||
1, /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
|
||||
5, /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
|
||||
1, /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
|
||||
2, /*!<Default value should be 2*/
|
||||
0,
|
||||
0
|
||||
},
|
||||
/* agcPeak */
|
||||
{
|
||||
205, /*!<1st update interval for the multiple time constant in AGC loop mode, Default:205. */
|
||||
2, /*!<sets the 2nd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of agcUnderRangeLowInterval , Default: 4 */
|
||||
4, /*!<sets the 3rd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of agcUnderRangeMidInterval and agcUnderRangeLowInterval, Default: 4 */
|
||||
39, /*!<AGC APD high threshold. Default=0x1F, 6-bit register value where max=0x3F, min =0x00 */
|
||||
49, /*!<AGC APD peak detect high threshold. default = 0x1F, 6-bit register value where max = 0x3F, min = 0x00. Set to 3dB below apdHighThresh */
|
||||
23, /*!<AGC APD peak detect low threshold. default = 3dB below high threshold, 6-bit register value where max =0x3F, min = 0x00 */
|
||||
19, /*!<AGC APD peak detect low threshold. default = 3dB below high threshold, 6-bit register value where max = 0x3F, min = 0x00 . Set to 3dB below apdLowThresh */
|
||||
6, /*!<AGC APD peak detect upper threshold count. Default = 0x06 8-bit register value where max = 0xFF, min = 0x20 */
|
||||
3, /*!<AGC APD peak detect lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00 */
|
||||
4, /*!<AGC APD peak detect attack gain step. Default = 2dB step - based on gain table step size, 5-bit register value, where max = 0x1F, min = 0x00 */
|
||||
2, /*!<AGC APD gain index step size. Recommended to be same as hb2GainStepRecovery. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00 */
|
||||
1, /*!<1-bit field, enables or disables the HB2 overload detector. */
|
||||
1, /*!<3-bit field. Sets the window of clock cycles (at the HB2 output rate) to meet the overload count. */
|
||||
1, /*!<4-bit field. Sets the number of actual overloads required to trigger the overload signal. */
|
||||
181, /*!<AGC decimator output high threshold. Default = 0xB5, 8-bit register value where max = 0xFF, min = 0x00 */
|
||||
45, /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
|
||||
90, /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
|
||||
128, /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
|
||||
6, /*!<AGC HB2 output upper threshold count. Default = 0x06, 8-bit register value where max = 0xFF, min = 0x20 */
|
||||
3, /*!<AGC HB2 output lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00 */
|
||||
2, /*!<AGC decimator gain index step size. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00 */
|
||||
4, /*!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 0 triggers a programmable number of times. Default = 0x08, 5-bit register value where max = 0x1F, min = 0x00 */
|
||||
8, /*!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 1 triggers a programmable number of times. Default = 0x04, 5-bit register value where max = 0x1F, min = 0x00 */
|
||||
4, /*!<AGC decimator output attack gain step. Default = 2dB step - based on gain table step size, 5-bit register value, where max = 0x1F, min = 0x00 */
|
||||
1,
|
||||
0,
|
||||
0
|
||||
}
|
||||
};
|
||||
|
||||
static int chipSelectIndex = 1;
|
||||
|
||||
static taliseDevice_t talDevice =
|
||||
{
|
||||
#if 0
|
||||
#ifdef ADI_ZYNQ_PLATFORM
|
||||
/* Void pointer of users platform HAL settings to pass to HAL layer calls
|
||||
* Talise API does not use the devHalInfo member */
|
||||
.devHalInfo = &talDevHalInfo,
|
||||
#else
|
||||
.devHalInfo = &(talInit.spiSettings),//NULL, /*/** < Insert Customer Platform HAL State Container here>*/
|
||||
#endif
|
||||
#else
|
||||
.devHalInfo = &chipSelectIndex,
|
||||
#endif
|
||||
/* devStateInfo is maintained internal to the Talise API, just create the memory */
|
||||
.devStateInfo = {0}
|
||||
|
||||
};
|
||||
|
||||
taliseDeviceInfo taliseDeviceInfo1 =
|
||||
{
|
||||
.ptalDevice = &talDevice,
|
||||
.ptalInit = &talInit
|
||||
};
|
||||
Executable
+29
@@ -0,0 +1,29 @@
|
||||
/**
|
||||
* \file talise_config.h
|
||||
* \brief Talise configuration external declarations
|
||||
*
|
||||
* \brief Contains structure definitions for tal_config.c
|
||||
*
|
||||
* Copyright 2015-2017 Analog Devices Inc.
|
||||
* Released under the AD9378-AD9379 API license, for more information see the "LICENSE.txt" file in this zip file.
|
||||
*
|
||||
* The top level structure taliseDevice_t talDevice uses keyword
|
||||
* extern to allow the application layer main() to have visibility
|
||||
* to these settings.
|
||||
*/
|
||||
|
||||
#ifndef TAL_INIT_1_H_
|
||||
#define TAL_INIT_1_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern taliseDevice_t talDevice1;
|
||||
extern taliseInit_t talInit1;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Executable
+422
@@ -0,0 +1,422 @@
|
||||
/**
|
||||
* \file talise_config.c
|
||||
* \brief Contains Talise configuration settings for the Talise API
|
||||
*
|
||||
* Copyright 2015-2017 Analog Devices Inc.
|
||||
* Released under the AD9378-AD9379 API license, for more information see the "LICENSE.txt" file in this zip file.
|
||||
*
|
||||
* The top level structure taliseDevice_t talDevice uses keyword
|
||||
* extern to allow the application layer main() to have visibility
|
||||
* to these settings.
|
||||
*
|
||||
* This file may not be fully complete for the end user application and
|
||||
* may need to updated for AGC, GPIO, and DAC full scale settings.
|
||||
* To create a full initialisation routine, the user should also refer to the
|
||||
* Iron Python initialisation routine generated by the GUI, and also the Talise User Guide.
|
||||
*
|
||||
*/
|
||||
|
||||
//#include "talise_types.h"
|
||||
//#include "talise_config_2.h"
|
||||
//#include "talise_error.h"
|
||||
//#include "talise_agc.h"
|
||||
#ifdef ADI_ZYNQ_PLATFORM
|
||||
#include "zynq_platform.h"
|
||||
#endif
|
||||
|
||||
#include "talise_config.h"
|
||||
|
||||
|
||||
|
||||
static int16_t txFirCoefs[20] = {-39, 24, -62, 112, -175, 298, -574, 1284, -2814, 20281, -2814, 1284, -574, 298, -175, 112, -62, 24, -39, 0};
|
||||
|
||||
static int16_t rxFirCoefs[48] = {-2, 23, 46, -17, -104, 10, 208, 23, -370, -97, 607, 240, -942, -489, 1407, 910, -2065, -1637, 3058, 2995, -4912, -6526, 9941, 30489, 30489, 9941, -6526, -4912, 2995, 3058, -1637, -2065, 910, 1407, -489, -942, 240, 607, -97, -370, 23, 208, 10, -104, -17, 46, 23, -2};
|
||||
|
||||
static int16_t obsrxFirCoefs[24] = {-15, 9, -13, 19, -28, 38, -73, 110, -195, 409, -1006, 17711, -1006, 409, -195, 110, -73, 38, -28, 19, -13, 9, -15, 0};
|
||||
|
||||
#ifdef ADI_ZYNQ_PLATFORM /** < Insert Customer Platform HAL State Container here>*/
|
||||
/*
|
||||
* Platform Layer SPI settings - this structure is specific to ADI's platform layer code.
|
||||
* User should replace with their own structure or settings for their hardware
|
||||
*/
|
||||
zynqSpiSettings_t spiDev1 =
|
||||
{
|
||||
.chipSelectIndex = 1,
|
||||
.writeBitPolarity = 0,
|
||||
.longInstructionWord = 1,
|
||||
.CPHA = 0,
|
||||
.CPOL = 0,
|
||||
.mode = 0,
|
||||
.spiClkFreq_Hz = 25000000
|
||||
};
|
||||
|
||||
/*
|
||||
* Platform Layer settings - this structure is specific to ADI's platform layer code.
|
||||
* User should replace with their own structure or settings for their hardware
|
||||
* The structure is held in taliseDevice_t below as a void pointer, allowing
|
||||
* the customer to pass any information for their specific hardware down to the
|
||||
* hardware layer code.
|
||||
*/
|
||||
zynqAdiDev_t talDevHalInfo =
|
||||
{
|
||||
.devIndex = 1,
|
||||
.spiSettings = &spiDev1,
|
||||
.spiErrCode = 0,
|
||||
.timerErrCode = 0,
|
||||
.gpioErrCode = 0,
|
||||
.logLevel = ADIHAL_LOG_ALL
|
||||
};
|
||||
#endif
|
||||
/**
|
||||
* TalDevice a structure used by the Talise API to hold the platform hardware
|
||||
* structure information, as well as an internal Talise API state container
|
||||
* (devStateInfo) of runtime information used by the API.
|
||||
**/
|
||||
|
||||
|
||||
static taliseInit_t talInit =
|
||||
{
|
||||
/* SPI settings */
|
||||
.spiSettings =
|
||||
{
|
||||
.MSBFirst = 1, /* 1 = MSBFirst, 0 = LSBFirst */
|
||||
.enSpiStreaming = 0, /* Not implemented in ADIs platform layer. SW feature to improve SPI throughput */
|
||||
.autoIncAddrUp = 1, /* Not implemented in ADIs platform layer. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr=addr-1 */
|
||||
.fourWireMode = 1, /* 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode */
|
||||
.cmosPadDrvStrength = TAL_CMOSPAD_DRV_2X /* Drive strength of CMOS pads when used as outputs (SDIO, SDO, GP_INTERRUPT, GPIO 1, GPIO 0) */
|
||||
},
|
||||
|
||||
/* Rx settings */
|
||||
.rx =
|
||||
{
|
||||
.rxProfile =
|
||||
{
|
||||
.rxFir =
|
||||
{
|
||||
.gain_dB = -6, /* filter gain */
|
||||
.numFirCoefs = 48, /* number of coefficients in the FIR filter */
|
||||
.coefs = &rxFirCoefs[0]
|
||||
},
|
||||
.rxFirDecimation = 2, /* Rx FIR decimation (1,2,4) */
|
||||
.rxDec5Decimation = 4, /* Decimation of Dec5 or Dec4 filter (5,4) */
|
||||
.rhb1Decimation = 1, /* RX Half band 1 decimation (1 or 2) */
|
||||
.rxOutputRate_kHz = 240000, /* Rx IQ data rate in kHz - 从245760调整为240000以匹配120MHz参考时钟 */
|
||||
.rfBandwidth_Hz = 200000000, /* The Rx RF passband bandwidth for the profile */
|
||||
.rxBbf3dBCorner_kHz = 200000, /* Rx BBF 3dB corner in kHz */
|
||||
.rxAdcProfile = {182, 142, 173, 90, 1280, 982, 1335, 96, 1369, 48, 1012, 18, 48, 48, 37, 208, 0, 0, 0, 0, 52, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905}, /* pointer to custom ADC profile */
|
||||
.rxDdcMode = TAL_RXDDC_BYPASS, /* Rx DDC mode */
|
||||
.rxNcoShifterCfg =
|
||||
{
|
||||
.bandAInputBandWidth_kHz = 0,
|
||||
.bandAInputCenterFreq_kHz = 0,
|
||||
.bandANco1Freq_kHz = 0,
|
||||
.bandANco2Freq_kHz = 0,
|
||||
.bandBInputBandWidth_kHz = 0,
|
||||
.bandBInputCenterFreq_kHz = 0,
|
||||
.bandBNco1Freq_kHz = 0,
|
||||
.bandBNco2Freq_kHz = 0
|
||||
}
|
||||
},
|
||||
.framerSel = TAL_FRAMER_A, /* Rx JESD204b framer configuration */
|
||||
.rxGainCtrl =
|
||||
{
|
||||
.gainMode = TAL_MGC, /* taliserxGainMode_t gainMode */
|
||||
.rx1GainIndex = 255, /* uint8_t rx1GainIndex */
|
||||
.rx2GainIndex = 255, /* uint8_t rx2GainIndex */
|
||||
.rx1MaxGainIndex = 255, /* uint8_t rx1MaxGainIndex */
|
||||
.rx1MinGainIndex = 195, /* uint8_t rx1MinGainIndex */
|
||||
.rx2MaxGainIndex = 255, /* uint8_t rx2MaxGainIndex */
|
||||
.rx2MinGainIndex = 195 /* uint8_t rx2MinGainIndex */
|
||||
},
|
||||
//.rxChannels = TAL_RX1RX2, /* The desired Rx Channels to enable during initialization */
|
||||
.rxChannels = TAL_RX1RX2, /* The desired Rx Channels to enable during initialization */
|
||||
},
|
||||
|
||||
|
||||
/* Tx settings */
|
||||
.tx =
|
||||
{
|
||||
.txProfile =
|
||||
{
|
||||
.dacDiv = 1, /* The divider used to generate the DAC clock */
|
||||
.txFir =
|
||||
{
|
||||
.gain_dB = 6, /* filter gain */
|
||||
.numFirCoefs = 20, /* number of coefficients in the FIR filter */
|
||||
.coefs = &txFirCoefs[0]
|
||||
},
|
||||
.txFirInterpolation = 1, /* The Tx digital FIR filter interpolation (1,2,4) */
|
||||
.thb1Interpolation = 2, /* Tx Halfband1 filter interpolation (1,2) */
|
||||
.thb2Interpolation = 2, /* Tx Halfband2 filter interpolation (1,2)*/
|
||||
.thb3Interpolation = 1, /* Tx Halfband3 filter interpolation (1,2)*/
|
||||
.txInt5Interpolation = 1, /* Tx Int5 filter interpolation (1,5) */
|
||||
.txInputRate_kHz = 480000, /* Primary Signal BW - 从491520调整为480000以匹配120MHz参考时钟 */
|
||||
.primarySigBandwidth_Hz = 200000000, /* The Rx RF passband bandwidth for the profile */
|
||||
.rfBandwidth_Hz = 450000000, /* The Tx RF passband bandwidth for the profile */
|
||||
.txDac3dBCorner_kHz = 450000, /* The DAC filter 3dB corner in kHz */
|
||||
.txBbf3dBCorner_kHz = 225000, /* The BBF 3dB corner in kHz */
|
||||
.loopBackAdcProfile = {150, 178, 181, 90, 1280, 1338, 1699, 493, 1386, 162, 934, 4, 48, 46, 35, 201, 0, 0, 0, 0, 50, 0, 0, 6, 24, 0, 0, 6, 24, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 15, 905}
|
||||
},
|
||||
.deframerSel = TAL_DEFRAMER_A, /* Talise JESD204b deframer config for the Tx data path */
|
||||
.txChannels = TAL_TX1TX2, /* The desired Tx channels to enable during initialization */
|
||||
.txAttenStepSize = TAL_TXATTEN_0P05_DB, /* Tx Attenuation step size */
|
||||
.tx1Atten_mdB = 0, /* Initial Tx1 Attenuation */
|
||||
.tx2Atten_mdB = 0, /* Initial Tx2 Attenuation */
|
||||
.disTxDataIfPllUnlock = TAL_TXDIS_TX_RAMP_DOWN_TO_ZERO /* Options to disable the transmit data when the RFPLL unlocks. */
|
||||
},
|
||||
|
||||
|
||||
/* ObsRx settings */
|
||||
.obsRx =
|
||||
{
|
||||
.orxProfile =
|
||||
{
|
||||
.rxFir =
|
||||
{
|
||||
.gain_dB = 6, /* filter gain */
|
||||
.numFirCoefs = 24, /* number of coefficients in the FIR filter */
|
||||
.coefs = &obsrxFirCoefs[0]
|
||||
},
|
||||
.rxFirDecimation = 1, /* Rx FIR decimation (1,2,4) */
|
||||
.rxDec5Decimation = 4, /* Decimation of Dec5 or Dec4 filter (5,4) */
|
||||
.rhb1Decimation = 1, /* RX Half band 1 decimation (1 or 2) */
|
||||
.orxOutputRate_kHz = 480000, /* Rx IQ data rate in kHz - 从491520调整为480000以匹配120MHz参考时钟 */
|
||||
.rfBandwidth_Hz = 450000000, /* The Rx RF passband bandwidth for the profile */
|
||||
.rxBbf3dBCorner_kHz = 225000, /* Rx BBF 3dB corner in kHz */
|
||||
.orxLowPassAdcProfile = {155, 163, 181, 90, 1280, 1254, 1572, 340, 1431, 142, 973, 8, 48, 47, 36, 205, 0, 0, 0, 0, 51, 0, 0, 6, 24, 0, 0, 6, 24, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 15, 905},
|
||||
.orxBandPassAdcProfile = {124, 131, 154, 90, 1280, 2779, 1986, 0, 1037, 839, 988, 109, 11, 15, 28, 179, 0, 0, 0, 0, 45, 0, 0, 0, 24, 0, 0, 0, 24, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 15, 905},
|
||||
.orxDdcMode = TAL_ORXDDC_DISABLED, /* ORx DDC mode */
|
||||
.orxMergeFilter = {-167, 419, -208, -498, 968, -320, -1273, 2154, -402, -4155, 9170, 21413}
|
||||
},
|
||||
.orxGainCtrl =
|
||||
{
|
||||
.gainMode = TAL_MGC,
|
||||
.orx1GainIndex = 255,
|
||||
.orx2GainIndex = 255,
|
||||
.orx1MaxGainIndex = 255,
|
||||
.orx1MinGainIndex = 195,
|
||||
.orx2MaxGainIndex = 255,
|
||||
.orx2MinGainIndex = 195
|
||||
},
|
||||
.framerSel = TAL_FRAMER_B, /* ObsRx JESD204b framer configuration */
|
||||
.obsRxChannelsEnable = TAL_ORX1,//@cc TAL_ORX1, /* The desired ObsRx Channels to enable during initialization */
|
||||
.obsRxLoSource = TAL_OBSLO_RF_PLL /* The ORx mixers can use the TX_PLL */
|
||||
},
|
||||
|
||||
/* Digital Clock Settings */
|
||||
.clocks =
|
||||
{
|
||||
.deviceClock_kHz = 120000, /* CLKPLL and device reference clock frequency in kHz - 从122880改为120000 */
|
||||
.clkPllVcoFreq_kHz = 9600000, /* CLKPLL VCO frequency in kHz - 从9830400改为9600000 (120MHz * 80) */
|
||||
.clkPllHsDiv = TAL_HSDIV_2P5, /* CLKPLL high speed clock divider */
|
||||
.rfPllUseExternalLo = 0, /* 1= Use external LO for RF PLL, 0 = use internal LO generation for RF PLL */
|
||||
.rfPllPhaseSyncMode = TAL_RFPLLMCS_NOSYNC /* RFPLL MCS (Phase sync) mode - 为120MHz操作改为NOSYNC */
|
||||
},
|
||||
|
||||
/* JESD204B settings */
|
||||
.jesd204Settings =
|
||||
{
|
||||
/* Framer A settings */
|
||||
.framerA =
|
||||
{
|
||||
.bankId = 1, /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15) */
|
||||
.deviceId = 0, /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */
|
||||
.lane0Id = 0, /* JESD204B Configuration starting Lane ID. If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */
|
||||
//.M = 4, /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain */
|
||||
.M = 4, /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain */
|
||||
.K = 32, /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */
|
||||
.F = 4, /* F (number of bytes per frame) */
|
||||
.Np = 16, /* Np (converter sample resolution) */
|
||||
.scramble = 0, /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */
|
||||
.externalSysref = 1, /* 0=use internal SYSREF, 1= use external SYSREF */
|
||||
//.serializerLanesEnabled = 0x0A, /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled */
|
||||
.serializerLanesEnabled = 0x0A, /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled */
|
||||
.serializerLaneCrossbar = 0xE4, /* serializerLaneCrossbar */
|
||||
.lmfcOffset = 31, /* lmfcOffset - LMFC offset value for deterministic latency setting */
|
||||
.newSysrefOnRelink = 0, /* newSysrefOnRelink */
|
||||
.syncbInSelect = 0, /* syncbInSelect; */
|
||||
.overSample = 0, /* 1=overSample, 0=bitRepeat */
|
||||
.syncbInLvdsMode = 1,
|
||||
.syncbInLvdsPnInvert = 0,
|
||||
.enableManualLaneXbar = 0 /* 0=auto, 1=manual */
|
||||
},
|
||||
/* Framer B settings */
|
||||
.framerB =
|
||||
{
|
||||
.bankId = 0, /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15) */
|
||||
.deviceId = 0, /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */
|
||||
.lane0Id = 0, /* JESD204B Configuration starting Lane ID. If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */
|
||||
.M = 2, /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain */
|
||||
.K = 32, /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */
|
||||
.F = 2, /* F (number of bytes per frame) */
|
||||
.Np = 16, /* Np (converter sample resolution) */
|
||||
.scramble = 0, /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */
|
||||
.externalSysref = 1,
|
||||
|
||||
/* 0=use internal SYSREF, 1= use external SYSREF */
|
||||
.serializerLanesEnabled = 0x05, /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled */
|
||||
.serializerLaneCrossbar = 0xE4, /* serializerLaneCrossbar */
|
||||
.lmfcOffset = 31, /* lmfcOffset - LMFC offset value for deterministic latency setting */
|
||||
.newSysrefOnRelink = 0, /* newSysrefOnRelink */
|
||||
.syncbInSelect = 1, /* syncbInSelect; */
|
||||
.overSample = 0, /* 1=overSample, 0=bitRepeat */
|
||||
.syncbInLvdsMode = 1,
|
||||
.syncbInLvdsPnInvert = 0,
|
||||
.enableManualLaneXbar = 1 /* 0=auto, 1=manual */
|
||||
},
|
||||
/* Deframer A settings */
|
||||
.deframerA =
|
||||
{
|
||||
.bankId = 0, /* bankId extension to Device ID (Valid 0..15) */
|
||||
.deviceId = 0, /* deviceId link identification number. (Valid 0..255) */
|
||||
.lane0Id = 0, /* lane0Id Lane0 ID. (Valid 0..31) */
|
||||
.M = 4, /* M number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
|
||||
.K = 32, /* K #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */
|
||||
.scramble = 0, /* scramble scrambling off if scramble= 0 */
|
||||
.externalSysref = 1, /* externalSysref 0= use internal SYSREF, 1= external SYSREF */
|
||||
.deserializerLanesEnabled = 0x0F, /* deserializerLanesEnabled bit per lane, [0] = Lane0 enabled */
|
||||
.deserializerLaneCrossbar = 0x27, /* deserializerLaneCrossbar */
|
||||
.lmfcOffset = 17, /* lmfcOffset LMFC offset value to adjust deterministic latency */
|
||||
.newSysrefOnRelink = 0, /* newSysrefOnRelink */
|
||||
.syncbOutSelect = 0, /* SYNCBOUT0/1 select */
|
||||
.Np = 16, /* Np (converter sample resolution) */
|
||||
.syncbOutLvdsMode = 1,
|
||||
.syncbOutLvdsPnInvert = 0,
|
||||
.syncbOutCmosSlewRate = 0,
|
||||
.syncbOutCmosDriveLevel = 0,
|
||||
.enableManualLaneXbar = 1 /* 0=auto, 1=manual */
|
||||
},
|
||||
/* Deframer B settings */
|
||||
.deframerB =
|
||||
{
|
||||
.bankId = 0, /* bankId extension to Device ID (Valid 0..15) */
|
||||
.deviceId = 0, /* deviceId link identification number. (Valid 0..255) */
|
||||
.lane0Id = 0, /* lane0Id Lane0 ID. (Valid 0..31) */
|
||||
.M = 0, /* M number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
|
||||
.K = 32, /* K #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */
|
||||
.scramble = 1, /* scramble scrambling off if scramble= 0 */
|
||||
.externalSysref = 1, /* externalSysref 0= use internal SYSREF, 1= external SYSREF */
|
||||
.deserializerLanesEnabled = 0x00, /* deserializerLanesEnabled bit per lane, [0] = Lane0 enabled */
|
||||
.deserializerLaneCrossbar = 0xB4, /* deserializerLaneCrossbar */
|
||||
.lmfcOffset = 0, /* lmfcOffset LMFC offset value to adjust deterministic latency */
|
||||
.newSysrefOnRelink = 0, /* newSysrefOnRelink */
|
||||
.syncbOutSelect = 1, /* SYNCBOUT0/1 select */
|
||||
.Np = 16, /* Np (converter sample resolution) */
|
||||
.syncbOutLvdsMode = 1,
|
||||
.syncbOutLvdsPnInvert = 0,
|
||||
.syncbOutCmosSlewRate = 0,
|
||||
.syncbOutCmosDriveLevel = 0,
|
||||
.enableManualLaneXbar = 1 /* 0=auto, 1=manual */
|
||||
},
|
||||
.serAmplitude = 15, /* Serializer amplitude setting. Default = 15. Range is 0..15 */
|
||||
.serPreEmphasis = 1, /* Serializer pre-emphasis setting. Default = 1 Range is 0..4 */
|
||||
.serInvertLanePolarity = 0, /* Serializer Lane PN inversion select. Default = 0. Where, bit[0] = 1 will invert lane [0], bit[1] = 1 will invert lane 1, etc. */
|
||||
.desInvertLanePolarity = 0, /* Deserializer Lane PN inversion select. bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc */
|
||||
.desEqSetting = 1, /* Deserializer Equalizer setting. Applied to all deserializer lanes. Range is 0..4 */
|
||||
.sysrefLvdsMode = 1, /* Use LVDS inputs on Talise for SYSREF */
|
||||
.sysrefLvdsPnInvert = 0 /*0= Do not PN invert SYSREF */
|
||||
}
|
||||
};
|
||||
|
||||
//Only needs to be called if user wants to setup AGC parameters
|
||||
static taliseAgcCfg_t rxAgcCtrl =
|
||||
{
|
||||
4,
|
||||
255,
|
||||
195,
|
||||
255,
|
||||
195,
|
||||
30720, /* AGC gain update time in us (125us-250us - based on IQ data rate - set for 125us @ 245.76 Mhz) */
|
||||
10,
|
||||
10,
|
||||
16,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
31,
|
||||
246,
|
||||
4,
|
||||
1, /*!<1- bit field to enable the multiple time constants in AGC loop for fast attack and fast recovery to max gain. */
|
||||
/* agcPower */
|
||||
{
|
||||
1, /*!<1-bit field, enables the Rx power measurement block. */
|
||||
1, /*!<1-bit field, allows using Rx PFIR for power measurement. */
|
||||
0, /*!<1-bit field, allows to use the output of the second digital offset block in the Rx datapath for power measurement. */
|
||||
9, /*!<AGC power measurement detect lower 0 threshold. Default = -12dBFS == 5, 7-bit register value where max = 0x7F, min = 0x00 */
|
||||
2, /*!<AGC power measurement detect lower 1 threshold. Default = (offset) 4dB == 0, 4-bit register value where max = 0xF, min = 0x00 */
|
||||
4, /*!<AGC power measurement detect lower 0 recovery gain step. Default = 2dB - based on gain table step size, 5-bit register value where max = 0x1F, min = 0x00 */
|
||||
4, /*!<AGC power measurement detect lower 1 recovery gain step. Default = 4dB - based on gain table step size, 5-bit register value where max = 0x1F, min = 0x00 */
|
||||
5, /*!< power measurement duration used by the decimated power block. Default = 0x05, 5-bit register value where max = 0x1F, min = 0x00 */
|
||||
5, /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
|
||||
1, /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
|
||||
5, /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
|
||||
1, /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
|
||||
2, /*!<Default value should be 2*/
|
||||
0,
|
||||
0
|
||||
},
|
||||
/* agcPeak */
|
||||
{
|
||||
205, /*!<1st update interval for the multiple time constant in AGC loop mode, Default:205. */
|
||||
2, /*!<sets the 2nd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of agcUnderRangeLowInterval , Default: 4 */
|
||||
4, /*!<sets the 3rd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of agcUnderRangeMidInterval and agcUnderRangeLowInterval, Default: 4 */
|
||||
39, /*!<AGC APD high threshold. Default=0x1F, 6-bit register value where max=0x3F, min =0x00 */
|
||||
49, /*!<AGC APD peak detect high threshold. default = 0x1F, 6-bit register value where max = 0x3F, min = 0x00. Set to 3dB below apdHighThresh */
|
||||
23, /*!<AGC APD peak detect low threshold. default = 3dB below high threshold, 6-bit register value where max =0x3F, min = 0x00 */
|
||||
19, /*!<AGC APD peak detect low threshold. default = 3dB below high threshold, 6-bit register value where max = 0x3F, min = 0x00 . Set to 3dB below apdLowThresh */
|
||||
6, /*!<AGC APD peak detect upper threshold count. Default = 0x06 8-bit register value where max = 0xFF, min = 0x20 */
|
||||
3, /*!<AGC APD peak detect lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00 */
|
||||
4, /*!<AGC APD peak detect attack gain step. Default = 2dB step - based on gain table step size, 5-bit register value, where max = 0x1F, min = 0x00 */
|
||||
2, /*!<AGC APD gain index step size. Recommended to be same as hb2GainStepRecovery. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00 */
|
||||
1, /*!<1-bit field, enables or disables the HB2 overload detector. */
|
||||
1, /*!<3-bit field. Sets the window of clock cycles (at the HB2 output rate) to meet the overload count. */
|
||||
1, /*!<4-bit field. Sets the number of actual overloads required to trigger the overload signal. */
|
||||
181, /*!<AGC decimator output high threshold. Default = 0xB5, 8-bit register value where max = 0xFF, min = 0x00 */
|
||||
45, /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
|
||||
90, /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
|
||||
128, /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
|
||||
6, /*!<AGC HB2 output upper threshold count. Default = 0x06, 8-bit register value where max = 0xFF, min = 0x20 */
|
||||
3, /*!<AGC HB2 output lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00 */
|
||||
2, /*!<AGC decimator gain index step size. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00 */
|
||||
4, /*!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 0 triggers a programmable number of times. Default = 0x08, 5-bit register value where max = 0x1F, min = 0x00 */
|
||||
8, /*!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 1 triggers a programmable number of times. Default = 0x04, 5-bit register value where max = 0x1F, min = 0x00 */
|
||||
4, /*!<AGC decimator output attack gain step. Default = 2dB step - based on gain table step size, 5-bit register value, where max = 0x1F, min = 0x00 */
|
||||
1,
|
||||
0,
|
||||
0
|
||||
}
|
||||
};
|
||||
/**
|
||||
* TalDevice a structure used by the Talise API to hold the platform hardware
|
||||
* structure information, as well as an internal Talise API state container
|
||||
* (devStateInfo) of runtime information used by the API.
|
||||
**/
|
||||
|
||||
static int chipSelectIndex = 2;
|
||||
|
||||
static taliseDevice_t talDevice =
|
||||
{
|
||||
#if 0
|
||||
#ifdef ADI_ZYNQ_PLATFORM
|
||||
/* Void pointer of users platform HAL settings to pass to HAL layer calls
|
||||
* Talise API does not use the devHalInfo member */
|
||||
.devHalInfo = &talDevHalInfo,
|
||||
#else
|
||||
.devHalInfo = &(talInit.spiSettings),//NULL, /*/** < Insert Customer Platform HAL State Container here>*/
|
||||
#endif
|
||||
#else
|
||||
.devHalInfo = &chipSelectIndex,
|
||||
#endif
|
||||
/* devStateInfo is maintained internal to the Talise API, just create the memory */
|
||||
.devStateInfo = {0}
|
||||
|
||||
};
|
||||
|
||||
taliseDeviceInfo taliseDeviceInfo2 =
|
||||
{
|
||||
.ptalDevice = &talDevice,
|
||||
.ptalInit = &talInit
|
||||
};
|
||||
Executable
+29
@@ -0,0 +1,29 @@
|
||||
/**
|
||||
* \file talise_config.h
|
||||
* \brief Talise configuration external declarations
|
||||
*
|
||||
* \brief Contains structure definitions for tal_config.c
|
||||
*
|
||||
* Copyright 2015-2017 Analog Devices Inc.
|
||||
* Released under the AD9378-AD9379 API license, for more information see the "LICENSE.txt" file in this zip file.
|
||||
*
|
||||
* The top level structure taliseDevice_t talDevice uses keyword
|
||||
* extern to allow the application layer main() to have visibility
|
||||
* to these settings.
|
||||
*/
|
||||
|
||||
#ifndef TAL_INIT_2_H_
|
||||
#define TAL_INIT_2_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern taliseDevice_t talDevice2;
|
||||
extern taliseInit_t talInit2;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Executable
+345
@@ -0,0 +1,345 @@
|
||||
const uint8_t streamBinary[] = {
|
||||
0x00, 0x02, 0x00, 0x20, 0x10, 0x02, 0x00, 0x20, 0x32, 0x00, 0x00, 0x10,
|
||||
0x0e, 0x02, 0x00, 0x00, 0xa0, 0x03, 0x00, 0x20, 0xa4, 0x05, 0x00, 0x20,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0x03, 0x00, 0x20,
|
||||
0xa8, 0x05, 0x00, 0x20, 0xbc, 0x03, 0x00, 0x20, 0xdc, 0x05, 0x00, 0x20,
|
||||
0xe4, 0x03, 0x00, 0x20, 0x44, 0x06, 0x00, 0x20, 0xfc, 0x03, 0x00, 0x20,
|
||||
0x78, 0x06, 0x00, 0x20, 0x24, 0x04, 0x00, 0x20, 0xe0, 0x06, 0x00, 0x20,
|
||||
0x50, 0x04, 0x00, 0x20, 0x60, 0x07, 0x00, 0x20, 0x7c, 0x04, 0x00, 0x20,
|
||||
0xe0, 0x07, 0x00, 0x20, 0x94, 0x04, 0x00, 0x20, 0x18, 0x08, 0x00, 0x20,
|
||||
0xa8, 0x04, 0x00, 0x20, 0x44, 0x08, 0x00, 0x20, 0xc0, 0x04, 0x00, 0x20,
|
||||
0x7c, 0x08, 0x00, 0x20, 0xd4, 0x04, 0x00, 0x20, 0xa8, 0x08, 0x00, 0x20,
|
||||
0xf4, 0x04, 0x00, 0x20, 0xf4, 0x08, 0x00, 0x20, 0x14, 0x05, 0x00, 0x20,
|
||||
0x40, 0x09, 0x00, 0x20, 0x24, 0x05, 0x00, 0x20, 0x64, 0x09, 0x00, 0x20,
|
||||
0x34, 0x05, 0x00, 0x20, 0x88, 0x09, 0x00, 0x20, 0x44, 0x05, 0x00, 0x20,
|
||||
0xb0, 0x09, 0x00, 0x20, 0x54, 0x05, 0x00, 0x20, 0xd8, 0x09, 0x00, 0x20,
|
||||
0x58, 0x05, 0x00, 0x20, 0xdc, 0x09, 0x00, 0x20, 0x60, 0x05, 0x00, 0x20,
|
||||
0xe8, 0x09, 0x00, 0x20, 0x64, 0x05, 0x00, 0x20, 0xf0, 0x09, 0x00, 0x20,
|
||||
0x68, 0x05, 0x00, 0x20, 0xf8, 0x09, 0x00, 0x20, 0x6c, 0x05, 0x00, 0x20,
|
||||
0x00, 0x0a, 0x00, 0x20, 0x70, 0x05, 0x00, 0x20, 0x08, 0x0a, 0x00, 0x20,
|
||||
0x78, 0x05, 0x00, 0x20, 0x18, 0x0a, 0x00, 0x20, 0x80, 0x05, 0x00, 0x20,
|
||||
0x28, 0x0a, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x05, 0x00, 0x20,
|
||||
0x30, 0x0a, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xcf, 0xc6, 0x00,
|
||||
0xce, 0xd0, 0xc1, 0xc1, 0xcf, 0xc0, 0xc0, 0xc0, 0xcd, 0xc0, 0xc0, 0xcd,
|
||||
0xc0, 0xc0, 0xcd, 0xc0, 0xc0, 0xc1, 0xcf, 0xd1, 0xc6, 0x00, 0x00, 0x00,
|
||||
0xce, 0xd0, 0xc1, 0xc1, 0xc1, 0xcf, 0xc0, 0xc0, 0xcd, 0xc1, 0xc1, 0xcd,
|
||||
0x98, 0x48, 0x98, 0x48, 0xc0, 0xc1, 0xc0, 0xc0, 0xc1, 0xc0, 0xc0, 0xc0,
|
||||
0xcd, 0xc1, 0xc1, 0xc0, 0xcd, 0xc0, 0xc0, 0xc1, 0xc1, 0xc1, 0xcf, 0xd1,
|
||||
0xc6, 0x00, 0x00, 0x00, 0xce, 0xd0, 0xc1, 0xc1, 0xcf, 0xc0, 0xc0, 0xc0,
|
||||
0xcd, 0xc0, 0xc0, 0xcd, 0xc0, 0xc0, 0xcd, 0xc0, 0xc0, 0xc1, 0xcf, 0xd1,
|
||||
0xc6, 0x00, 0x00, 0x00, 0xce, 0xd0, 0xc1, 0xc1, 0xc1, 0xcf, 0xc0, 0xc0,
|
||||
0xcd, 0xc1, 0xc1, 0x98, 0x48, 0x98, 0x48, 0xcd, 0xc0, 0xc1, 0xc0, 0xc0,
|
||||
0xc1, 0xc0, 0xc0, 0xc0, 0xcd, 0xc1, 0xc1, 0xc0, 0xcd, 0xc0, 0xc0, 0xc1,
|
||||
0xc1, 0xc1, 0xcf, 0xd1, 0xc6, 0x00, 0x00, 0x00, 0xce, 0xd0, 0xc1, 0xc1,
|
||||
0xc1, 0xcf, 0xc0, 0xc0, 0x98, 0x48, 0xc0, 0xc1, 0xcd, 0xc1, 0xc1, 0xc1,
|
||||
0xc1, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0x98, 0x48, 0x98, 0x48,
|
||||
0xc0, 0xc0, 0xcd, 0xc1, 0xc1, 0xc0, 0xc0, 0xc1, 0xc0, 0xc0, 0xcd, 0xc1,
|
||||
0xc1, 0xcf, 0xd1, 0xc6, 0xce, 0xd0, 0xc1, 0xc1, 0xc1, 0xcf, 0xc0, 0xc0,
|
||||
0xc0, 0xc1, 0x98, 0x48, 0xcd, 0xc1, 0xc1, 0xc1, 0xc1, 0xc0, 0xc0, 0xc0,
|
||||
0xc0, 0xc0, 0xc0, 0xc0, 0x98, 0x48, 0x98, 0x48, 0xc0, 0xc0, 0xcd, 0xc1,
|
||||
0xc1, 0xc0, 0xc0, 0xc1, 0xc0, 0xc0, 0xcd, 0xc1, 0xc1, 0xcf, 0xd1, 0xc6,
|
||||
0xce, 0xd0, 0xc1, 0xcf, 0xc0, 0xc0, 0xcd, 0xc0, 0xcd, 0xc0, 0xcd, 0xc0,
|
||||
0xc0, 0xcd, 0xc0, 0xc0, 0xc0, 0xc1, 0xc1, 0xcf, 0xd1, 0xc6, 0x00, 0x00,
|
||||
0xce, 0xd0, 0xc1, 0xcf, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xcd, 0xc0, 0xc1,
|
||||
0xc1, 0xc1, 0xcf, 0xd1, 0xc6, 0x00, 0x00, 0x00, 0xce, 0xd0, 0xc1, 0xcf,
|
||||
0xc0, 0xc0, 0xcd, 0xc0, 0xcd, 0xc0, 0xcd, 0xc0, 0xc0, 0xcd, 0xc0, 0xc0,
|
||||
0xc0, 0xc1, 0xc1, 0xcf, 0xd1, 0xc6, 0x00, 0x00, 0xce, 0xd0, 0xc1, 0xcf,
|
||||
0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xcd, 0xc0, 0xc1, 0xc1, 0xc1, 0xcf, 0xd1,
|
||||
0xc6, 0x00, 0x00, 0x00, 0xce, 0xd0, 0xc1, 0xcf, 0xc0, 0xc1, 0xc0, 0xc0,
|
||||
0x98, 0x48, 0x98, 0x48, 0xc0, 0xc0, 0xcd, 0xc1, 0xc0, 0xc0, 0xc0, 0xc0,
|
||||
0xcd, 0xc0, 0xc0, 0xc1, 0xc1, 0xc1, 0xcf, 0xd1, 0xc6, 0x00, 0x00, 0x00,
|
||||
0xce, 0xd0, 0xc1, 0xcf, 0xc0, 0xc1, 0xc0, 0xc0, 0x98, 0x48, 0x98, 0x48,
|
||||
0xc0, 0xc0, 0xcd, 0xc1, 0xc0, 0xc0, 0xc0, 0xc0, 0xcd, 0xc0, 0xc0, 0xc1,
|
||||
0xc1, 0xc1, 0xcf, 0xd1, 0xc6, 0x00, 0x00, 0x00, 0xce, 0xd0, 0xc1, 0xc1,
|
||||
0xcf, 0xc0, 0xc0, 0xc1, 0xc0, 0xc0, 0xc1, 0xcf, 0xd1, 0xc6, 0x00, 0x00,
|
||||
0xce, 0xd0, 0xc1, 0xc1, 0xcf, 0xc0, 0xc0, 0xcd, 0xc0, 0xc0, 0xc1, 0xcf,
|
||||
0xd1, 0xc6, 0x00, 0x00, 0xce, 0xd0, 0xc1, 0xcf, 0xc1, 0xc0, 0xc0, 0xc0,
|
||||
0xc1, 0xcd, 0xc1, 0xc1, 0xcf, 0xd1, 0xc6, 0x00, 0xce, 0xd0, 0xc1, 0xcf,
|
||||
0xc1, 0xc0, 0xc0, 0xc0, 0xc1, 0xcd, 0xc1, 0xc1, 0xcf, 0xd1, 0xc6, 0x00,
|
||||
0xce, 0xc6, 0x00, 0x00, 0xce, 0xc1, 0xcd, 0xc1, 0xc6, 0x00, 0x00, 0x00,
|
||||
0xce, 0xc1, 0xc6, 0x00, 0xce, 0xc1, 0xc6, 0x00, 0xce, 0x98, 0xc0, 0xc6,
|
||||
0xce, 0xc1, 0xc6, 0x00, 0xce, 0xc1, 0xcd, 0xc1, 0xc1, 0xc6, 0x00, 0x00,
|
||||
0xce, 0xc1, 0xcd, 0xc1, 0xc1, 0xc6, 0x00, 0x00, 0xce, 0x98, 0xc0, 0xc6,
|
||||
0xce, 0x50, 0x91, 0xae, 0x98, 0x81, 0xaf, 0x98, 0x86, 0x8f, 0x48, 0xa1,
|
||||
0xc8, 0xa9, 0x50, 0x91, 0xae, 0xa7, 0xc8, 0xaf, 0x55, 0x95, 0x81, 0xaf,
|
||||
0x98, 0x86, 0x8f, 0x48, 0xc6, 0x00, 0x00, 0x00, 0xf8, 0x14, 0x33, 0x04,
|
||||
0x05, 0x00, 0x00, 0x85, 0xfc, 0x14, 0x40, 0x40, 0xfb, 0x14, 0x40, 0x40,
|
||||
0x01, 0x87, 0x02, 0x02, 0x07, 0x03, 0x00, 0x09, 0x03, 0x39, 0x50, 0x00,
|
||||
0x56, 0x0f, 0x00, 0x09, 0x03, 0x29, 0x08, 0x00, 0x09, 0x03, 0x21, 0x92,
|
||||
0x0e, 0x01, 0x50, 0x00, 0x87, 0x02, 0x03, 0x28, 0x16, 0x00, 0xfc, 0x14,
|
||||
0x00, 0x40, 0x02, 0x00, 0x05, 0x00, 0x00, 0x86, 0xfc, 0x14, 0x01, 0x01,
|
||||
0xfb, 0x14, 0x01, 0x01, 0x5a, 0x15, 0x40, 0x40, 0x01, 0x05, 0x03, 0x08,
|
||||
0x85, 0x02, 0x00, 0x08, 0x00, 0x86, 0x02, 0x00, 0x16, 0x04, 0x03, 0x40,
|
||||
0x40, 0xf0, 0x00, 0xfa, 0x14, 0x02, 0x01, 0xf9, 0x14, 0x09, 0x08, 0x80,
|
||||
0x08, 0x30, 0x44, 0x08, 0x00, 0x33, 0x0b, 0x03, 0x7f, 0xdb, 0x07, 0x00,
|
||||
0x85, 0x07, 0x00, 0x18, 0x03, 0x03, 0x60, 0x05, 0x03, 0x00, 0x89, 0x02,
|
||||
0x00, 0x02, 0x00, 0x81, 0x07, 0x00, 0x21, 0xc2, 0x16, 0x00, 0x03, 0x85,
|
||||
0x02, 0x08, 0x08, 0x00, 0x85, 0x02, 0x09, 0x8c, 0x02, 0x00, 0x32, 0x15,
|
||||
0x00, 0x40, 0x45, 0x0a, 0x40, 0x40, 0xfc, 0x14, 0x00, 0x01, 0x02, 0x00,
|
||||
0x05, 0x00, 0x00, 0x87, 0xfc, 0x14, 0x80, 0x80, 0xfb, 0x14, 0x80, 0x80,
|
||||
0x01, 0x88, 0x02, 0x02, 0x08, 0x03, 0x00, 0x0a, 0x03, 0x39, 0x50, 0x00,
|
||||
0x57, 0x0f, 0x00, 0x0a, 0x03, 0x29, 0x08, 0x00, 0x0a, 0x03, 0x21, 0x93,
|
||||
0x0e, 0x01, 0x50, 0x00, 0x88, 0x02, 0x03, 0x29, 0x16, 0x00, 0xfc, 0x14,
|
||||
0x00, 0x80, 0x02, 0x00, 0x05, 0x00, 0x00, 0x88, 0xfc, 0x14, 0x02, 0x02,
|
||||
0xfb, 0x14, 0x02, 0x02, 0x5a, 0x15, 0x40, 0x40, 0x01, 0x06, 0x03, 0x08,
|
||||
0x86, 0x02, 0x00, 0x08, 0x00, 0x85, 0x02, 0x00, 0x16, 0x03, 0x03, 0x40,
|
||||
0x40, 0xfa, 0x14, 0x02, 0x01, 0xf9, 0x14, 0x0a, 0x08, 0xf0, 0x00, 0x80,
|
||||
0x08, 0x30, 0x44, 0x08, 0x00, 0x33, 0x0b, 0x03, 0x7f, 0xdb, 0x07, 0x00,
|
||||
0x85, 0x07, 0x00, 0x18, 0x04, 0x03, 0x60, 0x06, 0x03, 0x00, 0x89, 0x02,
|
||||
0x00, 0x02, 0x00, 0x81, 0x07, 0x00, 0x21, 0xc2, 0x16, 0x00, 0x03, 0x86,
|
||||
0x02, 0x08, 0x08, 0x00, 0x86, 0x02, 0x09, 0x8d, 0x02, 0x00, 0x32, 0x15,
|
||||
0x00, 0x40, 0x45, 0x0a, 0x80, 0x80, 0xfc, 0x14, 0x00, 0x02, 0x02, 0x00,
|
||||
0x10, 0x00, 0x00, 0x89, 0xfc, 0x14, 0x04, 0x04, 0xfb, 0x14, 0x0c, 0x0c,
|
||||
0x32, 0x15, 0x40, 0x40, 0x01, 0x05, 0x03, 0x08, 0x06, 0x03, 0x08, 0xf9,
|
||||
0x14, 0x09, 0x08, 0x85, 0x02, 0x00, 0x86, 0x02, 0x00, 0x14, 0x02, 0x80,
|
||||
0x80, 0x08, 0x30, 0x3f, 0x44, 0x08, 0x00, 0x33, 0x85, 0x0a, 0xc0, 0xc0,
|
||||
0x85, 0x07, 0x00, 0x18, 0x0b, 0x03, 0x7f, 0xdb, 0x07, 0x00, 0x03, 0x03,
|
||||
0x50, 0x04, 0x03, 0x70, 0x05, 0x03, 0x00, 0x06, 0x03, 0x00, 0x89, 0x02,
|
||||
0x01, 0xed, 0x14, 0x81, 0x0c, 0xee, 0x14, 0x82, 0x0c, 0x85, 0x02, 0x08,
|
||||
0x86, 0x02, 0x08, 0x08, 0x00, 0x81, 0x07, 0x00, 0x21, 0xc2, 0x16, 0x00,
|
||||
0x03, 0x85, 0x02, 0x0a, 0x86, 0x02, 0x0a, 0x82, 0x0c, 0x00, 0x40, 0x8c,
|
||||
0x02, 0x00, 0x8d, 0x02, 0x00, 0x80, 0x00, 0x5a, 0x15, 0x00, 0x40, 0xfc,
|
||||
0x14, 0x00, 0x04, 0x02, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x8a,
|
||||
0xfc, 0x14, 0x08, 0x08, 0xfb, 0x14, 0x0c, 0x0c, 0x32, 0x15, 0x40, 0x40,
|
||||
0x01, 0x05, 0x03, 0x08, 0x06, 0x03, 0x08, 0x86, 0x02, 0x00, 0x85, 0x02,
|
||||
0x00, 0x14, 0xf9, 0x14, 0x0a, 0x08, 0x02, 0x80, 0x80, 0x08, 0x30, 0x3f,
|
||||
0x44, 0x08, 0x00, 0x33, 0x85, 0x0a, 0xc0, 0xc0, 0x85, 0x07, 0x08, 0x18,
|
||||
0x0b, 0x03, 0x7f, 0xdb, 0x07, 0x00, 0x03, 0x03, 0x70, 0x04, 0x03, 0x50,
|
||||
0x05, 0x03, 0x00, 0x06, 0x03, 0x00, 0x89, 0x02, 0x01, 0xef, 0x14, 0x84,
|
||||
0x0c, 0xf0, 0x14, 0x85, 0x0c, 0x85, 0x02, 0x08, 0x86, 0x02, 0x08, 0x08,
|
||||
0x00, 0x81, 0x07, 0x00, 0x21, 0xc2, 0x16, 0x00, 0x03, 0x85, 0x02, 0x0a,
|
||||
0x86, 0x02, 0x0a, 0x85, 0x0c, 0x00, 0x40, 0x8c, 0x02, 0x00, 0x8d, 0x02,
|
||||
0x00, 0x80, 0x00, 0x5a, 0x15, 0x00, 0x40, 0xfc, 0x14, 0x00, 0x08, 0x02,
|
||||
0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x8b, 0xfc, 0x14, 0x40, 0x40,
|
||||
0x01, 0x87, 0x02, 0x02, 0x28, 0x16, 0x03, 0x30, 0x00, 0x92, 0x0e, 0x02,
|
||||
0x50, 0x00, 0x09, 0x03, 0x29, 0x0a, 0x00, 0x09, 0x03, 0x39, 0x56, 0x0f,
|
||||
0xee, 0x02, 0x00, 0x09, 0x03, 0x3f, 0x07, 0x03, 0x07, 0x87, 0x02, 0x00,
|
||||
0xfb, 0x14, 0x00, 0x40, 0xfc, 0x14, 0x00, 0x40, 0x02, 0x00, 0x00, 0x00,
|
||||
0x05, 0x00, 0x00, 0x8c, 0xfc, 0x14, 0x01, 0x01, 0x01, 0x0b, 0x03, 0x7f,
|
||||
0x8c, 0x02, 0x03, 0x85, 0x02, 0x08, 0x03, 0x03, 0x77, 0x05, 0x03, 0x5d,
|
||||
0x40, 0x00, 0x85, 0x02, 0x00, 0x45, 0x0a, 0x00, 0x40, 0xfb, 0x14, 0x00,
|
||||
0x01, 0xfc, 0x14, 0x00, 0x01, 0x02, 0x00, 0x00, 0x05, 0x00, 0x00, 0x8d,
|
||||
0xfc, 0x14, 0x80, 0x80, 0x01, 0x88, 0x02, 0x02, 0x29, 0x16, 0x03, 0x30,
|
||||
0x00, 0x93, 0x0e, 0x02, 0x50, 0x00, 0x0a, 0x03, 0x29, 0x0a, 0x00, 0x0a,
|
||||
0x03, 0x39, 0x57, 0x0f, 0xee, 0x02, 0x00, 0x0a, 0x03, 0x3f, 0x08, 0x03,
|
||||
0x07, 0x88, 0x02, 0x00, 0xfb, 0x14, 0x00, 0x80, 0xfc, 0x14, 0x00, 0x80,
|
||||
0x02, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x8e, 0xfc, 0x14, 0x02, 0x02,
|
||||
0x01, 0x0b, 0x03, 0x7f, 0x8d, 0x02, 0x03, 0x86, 0x02, 0x08, 0x04, 0x03,
|
||||
0x77, 0x06, 0x03, 0x5d, 0x40, 0x00, 0x86, 0x02, 0x00, 0x45, 0x0a, 0x00,
|
||||
0x80, 0xfb, 0x14, 0x00, 0x02, 0xfc, 0x14, 0x00, 0x02, 0x02, 0x00, 0x00,
|
||||
0x05, 0x00, 0x00, 0x8f, 0xfc, 0x14, 0x04, 0x04, 0x01, 0x0b, 0x03, 0x7f,
|
||||
0x80, 0x08, 0x00, 0x0f, 0x8c, 0x02, 0x03, 0x8d, 0x02, 0x03, 0xe9, 0x14,
|
||||
0x81, 0x0c, 0xea, 0x14, 0x82, 0x0c, 0x85, 0x02, 0x08, 0x86, 0x02, 0x08,
|
||||
0x02, 0x00, 0x82, 0x0c, 0x00, 0x40, 0x03, 0x03, 0x77, 0x04, 0x03, 0x77,
|
||||
0x05, 0x03, 0x1d, 0x06, 0x03, 0x1d, 0x40, 0x00, 0x85, 0x02, 0x00, 0x86,
|
||||
0x02, 0x00, 0x85, 0x0a, 0x00, 0xc0, 0xfb, 0x14, 0x00, 0x0c, 0xfc, 0x14,
|
||||
0x00, 0x04, 0x02, 0x00, 0x05, 0x00, 0x00, 0x90, 0xfc, 0x14, 0x08, 0x08,
|
||||
0x01, 0x0b, 0x03, 0x7f, 0x80, 0x08, 0x00, 0x0f, 0x8c, 0x02, 0x03, 0x8d,
|
||||
0x02, 0x03, 0xeb, 0x14, 0x84, 0x0c, 0xec, 0x14, 0x85, 0x0c, 0x85, 0x02,
|
||||
0x08, 0x86, 0x02, 0x08, 0x02, 0x00, 0x85, 0x0c, 0x00, 0x40, 0x03, 0x03,
|
||||
0x77, 0x04, 0x03, 0x77, 0x05, 0x03, 0x1d, 0x06, 0x03, 0x1d, 0x40, 0x00,
|
||||
0x85, 0x02, 0x00, 0x86, 0x02, 0x00, 0x85, 0x0a, 0x00, 0xc0, 0xfb, 0x14,
|
||||
0x00, 0x0c, 0xfc, 0x14, 0x00, 0x08, 0x02, 0x00, 0x05, 0x00, 0x00, 0x91,
|
||||
0xfc, 0x14, 0x10, 0x10, 0xfb, 0x14, 0x10, 0x10, 0x01, 0x89, 0x02, 0x02,
|
||||
0x05, 0x03, 0x00, 0x44, 0x08, 0x01, 0x01, 0x85, 0x02, 0x14, 0x03, 0x03,
|
||||
0x30, 0xfc, 0x14, 0x00, 0x10, 0x02, 0x00, 0x00, 0x05, 0x00, 0x00, 0x93,
|
||||
0xfc, 0x14, 0x20, 0x20, 0xfb, 0x14, 0x20, 0x20, 0x01, 0x89, 0x02, 0x02,
|
||||
0x06, 0x03, 0x00, 0x02, 0x00, 0x86, 0x02, 0x14, 0x04, 0x03, 0x30, 0xfc,
|
||||
0x14, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x93,
|
||||
0xfc, 0x14, 0x10, 0x10, 0x01, 0x44, 0x08, 0x00, 0x03, 0x03, 0x03, 0x70,
|
||||
0x0b, 0x03, 0x7f, 0x85, 0x02, 0x00, 0x44, 0x08, 0x00, 0x03, 0x20, 0x00,
|
||||
0xfb, 0x14, 0x00, 0x10, 0xfc, 0x14, 0x00, 0x10, 0x02, 0x00, 0x00, 0x00,
|
||||
0x05, 0x00, 0x00, 0x94, 0xfc, 0x14, 0x20, 0x20, 0x01, 0x44, 0x08, 0x00,
|
||||
0x30, 0x03, 0x03, 0x70, 0x0b, 0x03, 0x7f, 0x86, 0x02, 0x00, 0x44, 0x08,
|
||||
0x00, 0x30, 0x20, 0x00, 0xfb, 0x14, 0x00, 0x20, 0xfc, 0x14, 0x00, 0x20,
|
||||
0x02, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x05, 0x00, 0xc1, 0x05,
|
||||
0x10, 0x13, 0x04, 0x00, 0xc1, 0x05, 0x00, 0x13, 0x05, 0x00, 0xd0, 0x05,
|
||||
0x00, 0x03, 0x00, 0x00, 0x05, 0x00, 0xe0, 0x05, 0x00, 0x03, 0x00, 0x00,
|
||||
0x05, 0x00, 0xd5, 0x14, 0xd5, 0x14, 0x0c, 0x00, 0x05, 0x00, 0xc1, 0x05,
|
||||
0x03, 0x03, 0x00, 0x00, 0x05, 0x00, 0xc1, 0x05, 0x04, 0x04, 0x02, 0x00,
|
||||
0xd0, 0x05, 0x02, 0x03, 0xc1, 0x05, 0x00, 0x04, 0x05, 0x00, 0xc1, 0x05,
|
||||
0x08, 0x08, 0x02, 0x00, 0xe0, 0x05, 0x02, 0x03, 0xc1, 0x05, 0x00, 0x08,
|
||||
0x05, 0x00, 0xd5, 0x14, 0xd5, 0x14, 0x00, 0x00, 0x05, 0x00, 0xff, 0x00,
|
||||
0xf1, 0x14, 0x80, 0x08, 0x80, 0x08, 0x01, 0xff, 0x00, 0x01, 0xff, 0x00,
|
||||
0x0b, 0x03, 0x0b, 0x03, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0x93, 0x90, 0x0d, 0x7e
|
||||
};
|
||||
unsigned int firmware_TaliseStream_bin_len = 4096;
|
||||
Reference in New Issue
Block a user