提交SMOD ATSC IMX APP版本 V122
This commit is contained in:
@@ -0,0 +1,716 @@
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/*==========================================================================*/
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/* (Copyright (C) 2003 Koninklijke Philips Electronics N.V. */
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/* All rights reserved. */
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/* This source code and any compilation or derivative thereof is the */
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/* proprietary information of Koninklijke Philips Electronics N.V. */
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/* and is confidential in nature. */
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/* Under no circumstances is this software to be exposed to or placed */
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/* under an Open Source License of any type without the expressed */
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/* written permission of Koninklijke Philips Electronics N.V. */
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/*==========================================================================*/
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/*-----------------------------------------------------------------------------
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// MoReUse - 2001-11-12 Continuus Version 16
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//
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// Added
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// CID_COMP_TRICK
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// CID_COMP_TODISK
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// CID_COMP_FROMDISK
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//
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// Removed
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// CID_COMP_RTC Twice the same request - duplicate removed
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//
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// (C) Copyright 2000-2001 Koninklijke Philips Electronics N.V.,
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// All rights reserved
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//
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// This source code and any compilation or derivative thereof is the sole
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// property of Philips Corporation and is provided pursuant to a Software
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// License Agreement. This code is the proprietary information of Philips
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// Corporation and is confidential in nature. Its use and dissemination by
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// any party other than Philips Corporation is strictly limited by the
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// confidential information provisions of the Agreement referenced above.
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*/
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/*-----------------------------------------------------------------------------
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// FILE NAME: tmCompId.h
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//
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// DESCRIPTION: This header file identifies the standard component identifiers
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// for DVP platforms. The objective of DVP component IDs is to
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// enable unique identification of software components at all
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// classes, types, and layers. In addition, standard status
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// values are also defined to make determination of typical error
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// cases much easier. The component identifier bitfields are
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// four bit aligned to ease in reading the hexadecimal value.
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//
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// The process to create a new component ID follows the sequence
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// of steps:
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//
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// 1) Select a component class: The class is the most general
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// component classification. If none of the classifications
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// match and the component can still be uniquely identified
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// by its type/tag/layer combination, use CID_CLASS_NONE.
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// For customers, the CID_CLASS_CUSTOMER value is defined.
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// If that value is used in the CID_CLASS_BITMASK field,
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// all other bits in the component ID are user defined.
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//
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// 2) Select a component type: The component type is used to
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// classify how a component processes data. Components may
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// have only output pins (source), only input pins (sink),
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// input and output pins with or without data modifications
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// (filter), control of data flow without input/output pins
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// (control), data storage/access/retrieval (database),
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// or component group (subsystem). If the component does
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// not fit into any type classification, use CID_TYPE_NONE.
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//
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// 3) Create a component ID: The component ID is used to
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// classify the specific type and/or attributes of a software
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// component API interface. The currently defined list should
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// be scanned for a component match. If no component match
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// can be found, define a new component tag that descibes the
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// component clearly. Component name abbreviations/acronyms
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// are generally used; build a name starting from left to
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// right with the most general ('A' or 'AUD' for audio, 'V' or
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// 'VID' for video, etc.) to the most specific ('AC3' or 'MP3'
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// as specific audio filter types) terms for the component.
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//
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// NOTE: Component layer (CID_LAYER_XXX) and status (CID_ERR_XXX)
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// values are defined within the software component APIs
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// header files, not in this file.
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//
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// DOCUMENT REF: DVP Software Coding Guidelines specification
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// DVP/MoReUse Naming Conventions specification
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//
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// NOTES: The 32 bit component identifier bitfields are defined in the
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// diagram below:
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//
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// +----------------------------------------- 4 bit Component Class
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// / +----------------------------------- 4 bit Component Type
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// / / +-------------------------- 8 bit Component Tag
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// / / / +----------------- 4 bit Component Layer
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// / / / / +----- 12 bit Component Status
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// / / / / /
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// |31 28|27 24|23 16|15 12|11 0| bit
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// +------+------+------------+------+------------------+
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// |Class | Type |ComponentTag|Layer | Error/Progress |
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// +------+------+------------+------+------------------+
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//
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//-----------------------------------------------------------------------------
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*/
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#ifndef TM_COMP_ID_H
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#define TM_COMP_ID_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/*-----------------------------------------------------------------------------
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// Types and defines:
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//-----------------------------------------------------------------------------
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*/
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/*-----------------------------------------------------------------------------
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// TM_OK is the 32 bit global status value used by all DVP software components
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// to indicate successful function/operation status. If a non-zero value is
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// returned as status, it should use the component ID formats defined.
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*/
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#define TM_OK 0 /* Global success return status */
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/*
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// NOTE: Component ID types are defined as unsigned 32 bit integers (UInt32).
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//
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//-----------------------------------------------------------------------------
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// Component Class definitions (bits 31:28, 4 bits)
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// NOTE: A class of 0x0 must not be defined to ensure that the overall 32 bit
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// component ID/status combination is always non-0 (no TM_OK conflict).
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*/
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#define CID_CLASS_BITSHIFT 28 /* Component class bit shift */
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#define CID_CLASS_BITMASK (0xF << CID_CLASS_BITSHIFT) /* Class AND bitmsk */
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#define CID_GET_CLASS(compId) ((compId & CID_CLASS_BITMASK) >> CID_CLASS_BITSHIFT)
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#define CID_CLASS_NONE (0x1 << CID_CLASS_BITSHIFT) /* No class information */
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#define CID_CLASS_VIDEO (0x2 << CID_CLASS_BITSHIFT) /* Video data component */
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#define CID_CLASS_AUDIO (0x3 << CID_CLASS_BITSHIFT) /* Audio data component */
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#define CID_CLASS_GRAPHICS (0x4 << CID_CLASS_BITSHIFT) /* Graphics component */
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#define CID_CLASS_BUS (0x5 << CID_CLASS_BITSHIFT) /* In/out/control bus */
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#define CID_CLASS_INFRASTR (0x6 << CID_CLASS_BITSHIFT) /* Infrastructure comp. */
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/* Up to 0xE = Philips reserved class IDs */
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#define CID_CLASS_CUSTOMER (0xF << CID_CLASS_BITSHIFT) /* Customer rsvd class */
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/*-----------------------------------------------------------------------------
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// Component Type definitions (bits 27:24, 4 bits)
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*/
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#define CID_TYPE_BITSHIFT 24 /* Component type bit shift */
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#define CID_TYPE_BITMASK (0xF << CID_TYPE_BITSHIFT) /* Type AND bitmask */
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#define CID_GET_TYPE(compId) ((compId & CID_TYPE_BITMASK) >> CID_TYPE_BITSHIFT)
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#define CID_TYPE_NONE (0x0 << CID_TYPE_BITSHIFT) /* No data connections */
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#define CID_TYPE_SOURCE (0x1 << CID_TYPE_BITSHIFT) /* Source, output pins */
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#define CID_TYPE_SINK (0x2 << CID_TYPE_BITSHIFT) /* Sink, input pins */
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#define CID_TYPE_ENCODER (0x3 << CID_TYPE_BITSHIFT) /* Data encoder */
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#define CID_TYPE_DECODER (0x4 << CID_TYPE_BITSHIFT) /* Data decoder */
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#define CID_TYPE_MUX (0x5 << CID_TYPE_BITSHIFT) /* Data multiplexer */
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#define CID_TYPE_DEMUX (0x6 << CID_TYPE_BITSHIFT) /* Data demultiplexer */
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#define CID_TYPE_DIGITIZER (0x7 << CID_TYPE_BITSHIFT) /* Data digitizer */
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#define CID_TYPE_RENDERER (0x8 << CID_TYPE_BITSHIFT) /* Data renderer */
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#define CID_TYPE_FILTER (0x9 << CID_TYPE_BITSHIFT) /* Data filter/processr */
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#define CID_TYPE_CONTROL (0xA << CID_TYPE_BITSHIFT) /* Data control/switch */
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#define CID_TYPE_DATABASE (0xB << CID_TYPE_BITSHIFT) /* Data store/access */
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#define CID_TYPE_SUBSYSTEM (0xC << CID_TYPE_BITSHIFT) /* MultiComp subsystem */
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#define CID_TYPE_CUSTOMER (0xF << CID_TYPE_BITSHIFT) /* Customer Defined Type */
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/* Up to 0xF = Philips reserved type IDs */
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/*-----------------------------------------------------------------------------
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// Component Tag definitions (bits 23:16, 8 bits)
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// NOTE: Component tags are defined in groups, dependent on the class and type.
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*/
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#define CID_TAG_BITSHIFT 16 /* Component tag bit shift */
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#define CID_TAG_BITMASK (0xFF << CID_TAG_BITSHIFT) /* Comp tag AND bitmask */
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#define CID_TAG_NONE (0x00 << CID_TAG_BITSHIFT) /* No tag information */
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/* Up to 0xFF = Philips reserved component tags */
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#define CID_TAG_CUSTOMER (0xE0 << CID_TAG_BITSHIFT)
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#define TAG(number) ((number) << CID_TAG_BITSHIFT) /* Create tag from num */
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/*-----------------------------------------------------------------------------
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// Component Layer definitions (bits 15:12, 4 bits)
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*/
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#define CID_LAYER_BITSHIFT 12 /* Component layer bit shift */
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#define CID_LAYER_BITMASK (0xF << CID_LAYER_BITSHIFT) /* Layer AND bitmask */
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#define CID_GET_LAYER(compId) ((compId & CID_LAYER_BITMASK) >> CID_LAYER_BITSHIFT)
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#define CID_LAYER_NONE (0x0 << CID_LAYER_BITSHIFT) /* No layer info */
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#define CID_LAYER_BTM (0x1 << CID_LAYER_BITSHIFT) /* Boot manager layer */
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#define CID_LAYER_HWAPI (0x2 << CID_LAYER_BITSHIFT) /* Hardware API layer */
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#define CID_LAYER_BSL (0x3 << CID_LAYER_BITSHIFT) /* Board Supp. Lib lyr */
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#define CID_LAYER_DEVLIB (0x4 << CID_LAYER_BITSHIFT) /* Device Library lyr */
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#define CID_LAYER_TMAL (0x5 << CID_LAYER_BITSHIFT) /* Application layer */
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#define CID_LAYER_TMOL (0x6 << CID_LAYER_BITSHIFT) /* OSDependent layer */
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#define CID_LAYER_CUSTOMER (0xF << CID_LAYER_BITSHIFT) /* Customer Defined Layer */
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/* Up to 0xF = Philips reserved layer IDs */
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/*-----------------------------------------------------------------------------
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// Component Identifier definitions (bits 31:12, 20 bits)
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// NOTE: These DVP platform component identifiers are designed to be unique
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// within the system. The component identifier encompasses the class
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// (CID_CLASS_XXX), type (CID_TYPE_XXX), tag, and layer (CID_LAYER_XXX)
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// fields to form the unique component identifier. This allows any
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// error/progress status value to be identified as to its original
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// source, whether or not the source component's header file is present.
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// The standard error/progress status definitions should be used
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// whenever possible to ease status interpretation. No layer
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// information is defined at this point; it should be OR'd into the API
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// status values defined in the API's header file.
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*/
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#if (CID_LAYER_NONE != 0)
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#error ERROR: DVP component identifiers require the layer type 'NONE' = 0 !
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#endif
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/*
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// Classless Types/Components (don't fit into other class categories)
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*/
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#define CTYP_NOCLASS_NOTYPE (CID_CLASS_NONE | CID_TYPE_NONE)
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#define CTYP_NOCLASS_SOURCE (CID_CLASS_NONE | CID_TYPE_SOURCE)
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#define CTYP_NOCLASS_SINK (CID_CLASS_NONE | CID_TYPE_SINK)
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#define CTYP_NOCLASS_MUX (CID_CLASS_NONE | CID_TYPE_MUX)
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#define CTYP_NOCLASS_DEMUX (CID_CLASS_NONE | CID_TYPE_DEMUX)
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#define CTYP_NOCLASS_FILTER (CID_CLASS_NONE | CID_TYPE_FILTER)
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#define CTYP_NOCLASS_CONTROL (CID_CLASS_NONE | CID_TYPE_CONTROL)
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#define CTYP_NOCLASS_DATABASE (CID_CLASS_NONE | CID_TYPE_DATABASE)
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#define CTYP_NOCLASS_SUBSYS (CID_CLASS_NONE | CID_TYPE_SUBSYSTEM)
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#define CID_COMP_CLOCK (TAG(0x01) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_DMA (TAG(0x02) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_PIC (TAG(0x03) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_NORFLASH (TAG(0x04) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_NANDFLASH (TAG(0x05) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_GPIO (TAG(0x06) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_SMARTCARD (TAG(0x07) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_UDMA (TAG(0x08) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_DSP (TAG(0x09) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_TIMER (TAG(0x0A) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_TSDMA (TAG(0x0B) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_MMIARB (TAG(0x0C) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_EEPROM (TAG(0x0D) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_PARPORT (TAG(0x0E) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_VSS (TAG(0x0F) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_TSIO (TAG(0x10) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_DBG (TAG(0x11) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_TTE (TAG(0x12) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_AVPROP (TAG(0x13) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_BLASTER (TAG(0x14) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_CAPTURE (TAG(0x15) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_STP (TAG(0x16) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_SYN (TAG(0x17) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_TTX (TAG(0x18) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_MIU (TAG(0x19) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_INTDRV (TAG(0x1A) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_RESET (TAG(0x1B) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_CONFIG (TAG(0x1C) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_VCTRL (TAG(0x1D) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_TUNER (TAG(0x1E) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_DEMOD (TAG(0x1F) | CTYP_NOCLASS_NOTYPE)
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#define CID_COMP_FREAD (TAG(0x01) | CTYP_NOCLASS_SOURCE)
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#define CID_COMP_CDRREAD (TAG(0x02) | CTYP_NOCLASS_SOURCE)
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#define CID_COMP_VSB (TAG(0x03) | CTYP_NOCLASS_SOURCE)
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#define CID_COMP_ANALOGTVTUNER (TAG(0x04) | CTYP_NOCLASS_SOURCE)
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#define CID_COMP_TPINMPEG2 (TAG(0x05) | CTYP_NOCLASS_SOURCE)
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#define CID_COMP_DREAD (TAG(0x06) | CTYP_NOCLASS_SOURCE)
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#define CID_COMP_TREAD (TAG(0x07) | CTYP_NOCLASS_SOURCE)
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#define CID_COMP_RTC (TAG(0x08) | CTYP_NOCLASS_SOURCE)
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#define CID_COMP_TOUCHC (TAG(0x09) | CTYP_NOCLASS_SOURCE)
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#define CID_COMP_KEYPAD (TAG(0x0A) | CTYP_NOCLASS_SOURCE)
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#define CID_COMP_ADC (TAG(0x0B) | CTYP_NOCLASS_SOURCE)
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#define CID_COMP_READLIST (TAG(0x0C) | CTYP_NOCLASS_SOURCE)
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#define CID_COMP_FROMDISK (TAG(0x0D) | CTYP_NOCLASS_SOURCE)
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#define CID_COMP_FWRITE (TAG(0x01) | CTYP_NOCLASS_SINK)
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#define CID_COMP_CDWRITE (TAG(0x02) | CTYP_NOCLASS_SINK)
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#define CID_COMP_CHARLCD (TAG(0x03) | CTYP_NOCLASS_SINK)
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#define CID_COMP_PWM (TAG(0x04) | CTYP_NOCLASS_SINK)
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#define CID_COMP_DAC (TAG(0x05) | CTYP_NOCLASS_SINK)
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#define CID_COMP_TSDMAINJECTOR (TAG(0x06) | CTYP_NOCLASS_SINK)
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#define CID_COMP_TODISK (TAG(0x07) | CTYP_NOCLASS_SINK)
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#define CID_COMP_MUXMPEGPS (TAG(0x01) | CTYP_NOCLASS_MUX)
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#define CID_COMP_MUXMPEG (TAG(0x02) | CTYP_NOCLASS_MUX)
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#define CID_COMP_DEMUXMPEGTS (TAG(0x01) | CTYP_NOCLASS_DEMUX)
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#define CID_COMP_DEMUXMPEGPS (TAG(0x02) | CTYP_NOCLASS_DEMUX)
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||||
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#define CID_COMP_COPYIO (TAG(0x01) | CTYP_NOCLASS_FILTER)
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#define CID_COMP_COPYINPLACE (TAG(0x02) | CTYP_NOCLASS_FILTER)
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||||
#define CID_COMP_UART (TAG(0x03) | CTYP_NOCLASS_FILTER)
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||||
#define CID_COMP_SSI (TAG(0x04) | CTYP_NOCLASS_FILTER)
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||||
#define CID_COMP_MODEMV34 (TAG(0x05) | CTYP_NOCLASS_FILTER)
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||||
#define CID_COMP_MODEMV42 (TAG(0x06) | CTYP_NOCLASS_FILTER)
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||||
#define CID_COMP_HTMLPARSER (TAG(0x07) | CTYP_NOCLASS_FILTER)
|
||||
#define CID_COMP_VMSP (TAG(0x08) | CTYP_NOCLASS_FILTER)
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||||
#define CID_COMP_X (TAG(0x09) | CTYP_NOCLASS_FILTER)
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||||
#define CID_COMP_TXTSUBTDECEBU (TAG(0x0A) | CTYP_NOCLASS_FILTER)
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||||
#define CID_COMP_CPI (TAG(0x0B) | CTYP_NOCLASS_FILTER)
|
||||
#define CID_COMP_TRICK (TAG(0x0C) | CTYP_NOCLASS_FILTER)
|
||||
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||||
#define CID_COMP_REMCTL5 (TAG(0x01) | CTYP_NOCLASS_CONTROL)
|
||||
#define CID_COMP_INFRARED (TAG(0x02) | CTYP_NOCLASS_CONTROL)
|
||||
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||||
#define CID_COMP_PSIP (TAG(0x01) | CTYP_NOCLASS_DATABASE)
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||||
#define CID_COMP_IDE (TAG(0x02) | CTYP_NOCLASS_DATABASE)
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||||
#define CID_COMP_DISKSCHED (TAG(0x03) | CTYP_NOCLASS_DATABASE)
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||||
#define CID_COMP_AVFS (TAG(0x04) | CTYP_NOCLASS_DATABASE)
|
||||
#define CID_COMP_MDB (TAG(0x05) | CTYP_NOCLASS_DATABASE)
|
||||
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||||
#define CID_COMP_IRDMMPEG (TAG(0x01) | CTYP_NOCLASS_SUBSYS)
|
||||
#define CID_COMP_STORSYS (TAG(0x02) | CTYP_NOCLASS_SUBSYS)
|
||||
|
||||
/*
|
||||
// Video Class Types/Components (video types handle video/graphics data)
|
||||
*/
|
||||
#define CTYP_VIDEO_SINK (CID_CLASS_VIDEO | CID_TYPE_SINK)
|
||||
#define CTYP_VIDEO_SOURCE (CID_CLASS_VIDEO | CID_TYPE_SOURCE)
|
||||
#define CTYP_VIDEO_ENCODER (CID_CLASS_VIDEO | CID_TYPE_ENCODER)
|
||||
#define CTYP_VIDEO_DECODER (CID_CLASS_VIDEO | CID_TYPE_DECODER)
|
||||
#define CTYP_VIDEO_DIGITIZER (CID_CLASS_VIDEO | CID_TYPE_DIGITIZER)
|
||||
#define CTYP_VIDEO_RENDERER (CID_CLASS_VIDEO | CID_TYPE_RENDERER)
|
||||
#define CTYP_VIDEO_FILTER (CID_CLASS_VIDEO | CID_TYPE_FILTER)
|
||||
#define CTYP_VIDEO_SUBSYS (CID_CLASS_VIDEO | CID_TYPE_SUBSYSTEM)
|
||||
|
||||
#define CID_COMP_LCD (TAG(0x01) | CTYP_VIDEO_SINK)
|
||||
|
||||
#define CID_COMP_VCAPVI (TAG(0x01) | CTYP_VIDEO_SOURCE)
|
||||
#define CID_COMP_VIP (TAG(0x02) | CTYP_VIDEO_SOURCE)
|
||||
#define CID_COMP_VI (TAG(0x03) | CTYP_VIDEO_SOURCE)
|
||||
#define CID_COMP_VSLICER (TAG(0x04) | CTYP_VIDEO_SOURCE)
|
||||
#define CID_COMP_FBREAD (TAG(0x05) | CTYP_VIDEO_SOURCE)
|
||||
#define CID_COMP_QVI (TAG(0x06) | CTYP_VIDEO_SOURCE)
|
||||
#define CID_COMP_CAMERA (TAG(0x07) | CTYP_VIDEO_SOURCE)
|
||||
|
||||
#define CID_COMP_VENCM1 (TAG(0x01) | CTYP_VIDEO_ENCODER)
|
||||
#define CID_COMP_VENCM2 (TAG(0x02) | CTYP_VIDEO_ENCODER)
|
||||
#define CID_COMP_VENCMJ (TAG(0x03) | CTYP_VIDEO_ENCODER)
|
||||
#define CID_COMP_VENCH263 (TAG(0x04) | CTYP_VIDEO_ENCODER)
|
||||
#define CID_COMP_VENCH261 (TAG(0x05) | CTYP_VIDEO_ENCODER)
|
||||
|
||||
#define CID_COMP_VDECM1 (TAG(0x01) | CTYP_VIDEO_DECODER)
|
||||
#define CID_COMP_VDECM2 (TAG(0x02) | CTYP_VIDEO_DECODER)
|
||||
#define CID_COMP_VDECMPEG (TAG(0x03) | CTYP_VIDEO_DECODER)
|
||||
#define CID_COMP_VDECMJ (TAG(0x04) | CTYP_VIDEO_DECODER)
|
||||
#define CID_COMP_VDECSUBPICSVCD (TAG(0x05) | CTYP_VIDEO_DECODER)
|
||||
#define CID_COMP_VDECH263 (TAG(0x06) | CTYP_VIDEO_DECODER)
|
||||
#define CID_COMP_VDECH261 (TAG(0x07) | CTYP_VIDEO_DECODER)
|
||||
#define CID_COMP_VDEC (TAG(0x08) | CTYP_VIDEO_DECODER)
|
||||
#define CID_COMP_VDECSUBPICDVD (TAG(0x09) | CTYP_VIDEO_DECODER)
|
||||
#define CID_COMP_VDECSUBPICBMPDVD (TAG(0x0A) | CTYP_VIDEO_DECODER)
|
||||
#define CID_COMP_VDECSUBPICRENDDVD (TAG(0x0B) | CTYP_VIDEO_DECODER)
|
||||
#define CID_COMP_M4PP (TAG(0x0C) | CTYP_VIDEO_DECODER)
|
||||
#define CID_COMP_M4MC (TAG(0x0D) | CTYP_VIDEO_DECODER)
|
||||
#define CID_COMP_M4CSC (TAG(0x0E) | CTYP_VIDEO_DECODER)
|
||||
|
||||
#define CID_COMP_VDIG (TAG(0x01) | CTYP_VIDEO_DIGITIZER)
|
||||
#define CID_COMP_VDIGVIRAW (TAG(0x02) | CTYP_VIDEO_DIGITIZER)
|
||||
|
||||
#define CID_COMP_VREND (TAG(0x01) | CTYP_VIDEO_RENDERER)
|
||||
#define CID_COMP_HDVO (TAG(0x02) | CTYP_VIDEO_RENDERER)
|
||||
#define CID_COMP_VRENDGFXVO (TAG(0x03) | CTYP_VIDEO_RENDERER)
|
||||
#define CID_COMP_AICP (TAG(0x04) | CTYP_VIDEO_RENDERER)
|
||||
#define CID_COMP_VRENDVORAW (TAG(0x05) | CTYP_VIDEO_RENDERER)
|
||||
#define CID_COMP_VO (TAG(0x06) | CTYP_VIDEO_RENDERER)
|
||||
#define CID_COMP_QVO (TAG(0x06) | CTYP_VIDEO_RENDERER)
|
||||
#define CID_COMP_VRENDVOICP (TAG(0x07) | CTYP_VIDEO_RENDERER)
|
||||
#define CID_COMP_VMIX (TAG(0x08) | CTYP_VIDEO_RENDERER)
|
||||
#define CID_COMP_GFX (TAG(0x09) | CTYP_VIDEO_RENDERER)
|
||||
|
||||
#define CID_COMP_MBS (TAG(0x01) | CTYP_VIDEO_FILTER)
|
||||
#define CID_COMP_VTRANS (TAG(0x02) | CTYP_VIDEO_FILTER)
|
||||
#define CID_COMP_QNM (TAG(0x03) | CTYP_VIDEO_FILTER)
|
||||
#define CID_COMP_ICP (TAG(0x04) | CTYP_VIDEO_FILTER)
|
||||
#define CID_COMP_VTRANSNM (TAG(0x05) | CTYP_VIDEO_FILTER)
|
||||
#define CID_COMP_QFD (TAG(0x06) | CTYP_VIDEO_FILTER) /* film detector */
|
||||
#define CID_COMP_VRENDDVDVO (TAG(0x07) | CTYP_VIDEO_FILTER)
|
||||
#define CID_COMP_VTRANSCRYSTAL (TAG(0x08) | CTYP_VIDEO_FILTER)
|
||||
|
||||
#define CID_COMP_VSYSMT3 (TAG(0x01) | CTYP_VIDEO_SUBSYS) /* obsolescent */
|
||||
#define CID_COMP_VSYSSTB (TAG(0x01) | CTYP_VIDEO_SUBSYS)
|
||||
#define CID_COMP_DVDVIDSYS (TAG(0x02) | CTYP_VIDEO_SUBSYS)
|
||||
#define CID_COMP_VDECUD (TAG(0x03) | CTYP_VIDEO_SUBSYS)
|
||||
#define CID_COMP_VIDSYS (TAG(0x04) | CTYP_VIDEO_SUBSYS)
|
||||
/*
|
||||
// Audio Class Types/Components (audio types primarily handle audio data)
|
||||
*/
|
||||
#define CTYP_AUDIO_NONE (CID_CLASS_AUDIO | CID_TYPE_NONE)
|
||||
#define CTYP_AUDIO_SINK (CID_CLASS_AUDIO | CID_TYPE_SINK)
|
||||
#define CTYP_AUDIO_SOURCE (CID_CLASS_AUDIO | CID_TYPE_SOURCE)
|
||||
#define CTYP_AUDIO_ENCODER (CID_CLASS_AUDIO | CID_TYPE_ENCODER)
|
||||
#define CTYP_AUDIO_DECODER (CID_CLASS_AUDIO | CID_TYPE_DECODER)
|
||||
#define CTYP_AUDIO_DIGITIZER (CID_CLASS_AUDIO | CID_TYPE_DIGITIZER)
|
||||
#define CTYP_AUDIO_RENDERER (CID_CLASS_AUDIO | CID_TYPE_RENDERER)
|
||||
#define CTYP_AUDIO_FILTER (CID_CLASS_AUDIO | CID_TYPE_FILTER)
|
||||
#define CTYP_AUDIO_SUBSYS (CID_CLASS_AUDIO | CID_TYPE_SUBSYSTEM)
|
||||
|
||||
#define CID_COMP_AI (TAG(0x01) | CTYP_AUDIO_NONE)
|
||||
#define CID_COMP_AO (TAG(0x03) | CTYP_AUDIO_NONE)
|
||||
#define CID_COMP_ADAI (TAG(0x04) | CTYP_AUDIO_NONE)
|
||||
|
||||
#define CID_COMP_SDAC (TAG(0x01) | CTYP_AUDIO_SINK)
|
||||
|
||||
#define CID_COMP_ADIGAI (TAG(0x01) | CTYP_AUDIO_DIGITIZER)
|
||||
#define CID_COMP_ADIGSPDIF (TAG(0x02) | CTYP_AUDIO_DIGITIZER)
|
||||
|
||||
#define CID_COMP_ARENDAO (TAG(0x01) | CTYP_AUDIO_RENDERER)
|
||||
#define CID_COMP_ARENDSPDIF (TAG(0x02) | CTYP_AUDIO_RENDERER)
|
||||
|
||||
#define CID_COMP_NOISESEQ (TAG(0x03) | CTYP_AUDIO_SOURCE)
|
||||
|
||||
#define CID_COMP_AENCAC3 (TAG(0x01) | CTYP_AUDIO_ENCODER)
|
||||
#define CID_COMP_AENCMPEG1 (TAG(0x02) | CTYP_AUDIO_ENCODER)
|
||||
#define CID_COMP_AENCAAC (TAG(0x03) | CTYP_AUDIO_ENCODER)
|
||||
#define CID_COMP_AENCG723 (TAG(0x04) | CTYP_AUDIO_ENCODER)
|
||||
#define CID_COMP_AENCG728 (TAG(0x05) | CTYP_AUDIO_ENCODER)
|
||||
#define CID_COMP_AENCWMA (TAG(0x06) | CTYP_AUDIO_ENCODER)
|
||||
|
||||
#define CID_COMP_ADECPROLOGIC (TAG(0x01) | CTYP_AUDIO_DECODER)
|
||||
#define CID_COMP_ADECAC3 (TAG(0x02) | CTYP_AUDIO_DECODER)
|
||||
#define CID_COMP_ADECMPEG1 (TAG(0x03) | CTYP_AUDIO_DECODER)
|
||||
#define CID_COMP_ADECMP3 (TAG(0x04) | CTYP_AUDIO_DECODER)
|
||||
#define CID_COMP_ADECAAC (TAG(0x05) | CTYP_AUDIO_DECODER)
|
||||
#define CID_COMP_ADECG723 (TAG(0x06) | CTYP_AUDIO_DECODER)
|
||||
#define CID_COMP_ADECG728 (TAG(0x07) | CTYP_AUDIO_DECODER)
|
||||
#define CID_COMP_ADECWMA (TAG(0x08) | CTYP_AUDIO_DECODER)
|
||||
#define CID_COMP_ADECTHRU (TAG(0x09) | CTYP_AUDIO_DECODER)
|
||||
#define CID_COMP_ADEC (TAG(0x0A) | CTYP_AUDIO_DECODER)
|
||||
|
||||
#define CID_COMP_ASPLIB (TAG(0x01) | CTYP_AUDIO_FILTER)
|
||||
#define CID_COMP_IIR (TAG(0x02) | CTYP_AUDIO_FILTER)
|
||||
#define CID_COMP_ASPEQ2 (TAG(0x03) | CTYP_AUDIO_FILTER)
|
||||
#define CID_COMP_ASPEQ5 (TAG(0x04) | CTYP_AUDIO_FILTER)
|
||||
#define CID_COMP_ASPBASSREDIR (TAG(0x05) | CTYP_AUDIO_FILTER)
|
||||
#define CID_COMP_ASPLAT2 (TAG(0x06) | CTYP_AUDIO_FILTER)
|
||||
#define CID_COMP_ASPPLUGIN (TAG(0x07) | CTYP_AUDIO_FILTER)
|
||||
#define CID_COMP_AMIXDTV (TAG(0x08) | CTYP_AUDIO_FILTER)
|
||||
#define CID_COMP_AMIXSIMPLE (TAG(0x09) | CTYP_AUDIO_FILTER)
|
||||
#define CID_COMP_AMIXSTB (TAG(0x0A) | CTYP_AUDIO_FILTER)
|
||||
#define CID_COMP_ASPEQ (TAG(0x0B) | CTYP_AUDIO_FILTER)
|
||||
#define CID_COMP_ATESTSIG (TAG(0x0C) | CTYP_AUDIO_FILTER)
|
||||
|
||||
#define CID_COMP_AUDSUBSYS (TAG(0x01) | CTYP_AUDIO_SUBSYS)
|
||||
#define CID_COMP_AUDSYSSTB (TAG(0x02) | CTYP_AUDIO_SUBSYS)
|
||||
#define CID_COMP_AUDSYSDVD (TAG(0x03) | CTYP_AUDIO_SUBSYS)
|
||||
|
||||
/*
|
||||
// Graphics Class Types/Components
|
||||
*/
|
||||
#define CTYP_GRAPHICS_RENDERER (CID_CLASS_GRAPHICS | CID_TYPE_SINK)
|
||||
|
||||
#define CID_COMP_WM (TAG(0x01) | CTYP_GRAPHICS_RENDERER)
|
||||
#define CID_COMP_WIDGET (TAG(0x02) | CTYP_GRAPHICS_RENDERER)
|
||||
#define CID_COMP_OM (TAG(0x03) | CTYP_GRAPHICS_RENDERER)
|
||||
#define CID_COMP_HTMLRENDER (TAG(0x04) | CTYP_GRAPHICS_RENDERER)
|
||||
#define CID_COMP_VRENDEIA708 (TAG(0x05) | CTYP_GRAPHICS_RENDERER)
|
||||
#define CID_COMP_VRENDEIA608 (TAG(0x06) | CTYP_GRAPHICS_RENDERER)
|
||||
|
||||
#define CTYP_GRAPHICS_DRAW (CID_CLASS_GRAPHICS | CID_TYPE_NONE)
|
||||
|
||||
#define CID_COMP_DRAW (TAG(0x10) | CTYP_GRAPHICS_DRAW)
|
||||
#define CID_COMP_DRAW_UT (TAG(0x11) | CTYP_GRAPHICS_DRAW)
|
||||
#define CID_COMP_DRAW_DE (TAG(0x12) | CTYP_GRAPHICS_DRAW)
|
||||
#define CID_COMP_DRAW_REF (TAG(0x13) | CTYP_GRAPHICS_DRAW)
|
||||
#define CID_COMP_DRAW_TMH (TAG(0x14) | CTYP_GRAPHICS_DRAW)
|
||||
#define CID_COMP_DRAW_TMT (TAG(0x15) | CTYP_GRAPHICS_DRAW)
|
||||
#define CID_COMP_DRAW_TMTH (TAG(0x16) | CTYP_GRAPHICS_DRAW)
|
||||
|
||||
#define CID_COMP_3D (TAG(0x30) | CTYP_GRAPHICS_DRAW)
|
||||
#define CID_COMP_JAWT (TAG(0x31) | CTYP_GRAPHICS_DRAW)
|
||||
#define CID_COMP_JINPUT (TAG(0x32) | CTYP_GRAPHICS_DRAW)
|
||||
#define CID_COMP_LWM (TAG(0x33) | CTYP_GRAPHICS_DRAW)
|
||||
#define CID_COMP_2D (TAG(0x34) | CTYP_GRAPHICS_DRAW)
|
||||
|
||||
|
||||
/*
|
||||
// Bus Class Types/Components (busses connect hardware components together)
|
||||
*/
|
||||
#define CTYP_BUS_NOTYPE (CID_CLASS_BUS | CID_TYPE_NONE)
|
||||
|
||||
#define CID_COMP_XIO (TAG(0x01) | CTYP_BUS_NOTYPE)
|
||||
#define CID_COMP_IIC (TAG(0x02) | CTYP_BUS_NOTYPE)
|
||||
#define CID_COMP_PCI (TAG(0x03) | CTYP_BUS_NOTYPE)
|
||||
#define CID_COMP_P1394 (TAG(0x04) | CTYP_BUS_NOTYPE)
|
||||
#define CID_COMP_ENET (TAG(0x05) | CTYP_BUS_NOTYPE)
|
||||
#define CID_COMP_ATA (TAG(0x06) | CTYP_BUS_NOTYPE)
|
||||
#define CID_COMP_CAN (TAG(0x07) | CTYP_BUS_NOTYPE)
|
||||
#define CID_COMP_UCGDMA (TAG(0x08) | CTYP_BUS_NOTYPE)
|
||||
#define CID_COMP_I2S (TAG(0x09) | CTYP_BUS_NOTYPE)
|
||||
#define CID_COMP_SPI (TAG(0x0A) | CTYP_BUS_NOTYPE)
|
||||
#define CID_COMP_PCM (TAG(0x0B) | CTYP_BUS_NOTYPE)
|
||||
#define CID_COMP_L3 (TAG(0x0C) | CTYP_BUS_NOTYPE)
|
||||
|
||||
/*
|
||||
// Infrastructure Class Types/Components
|
||||
*/
|
||||
#define CTYP_INFRASTR_NOTYPE (CID_CLASS_INFRASTR | CID_TYPE_NONE)
|
||||
|
||||
#define CID_COMP_OSAL (TAG(0x01) | CTYP_INFRASTR_NOTYPE)
|
||||
#define CID_COMP_MML (TAG(0x02) | CTYP_INFRASTR_NOTYPE)
|
||||
#define CID_COMP_TSSA_DEFAULTS (TAG(0x03) | CTYP_INFRASTR_NOTYPE)
|
||||
#define CID_COMP_RPC (TAG(0x04) | CTYP_INFRASTR_NOTYPE)
|
||||
#define CID_COMP_THI (TAG(0x05) | CTYP_INFRASTR_NOTYPE)
|
||||
#define CID_COMP_REGISTRY (TAG(0x06) | CTYP_INFRASTR_NOTYPE)
|
||||
#define CID_COMP_TMMAN (TAG(0x07) | CTYP_INFRASTR_NOTYPE)
|
||||
#define CID_COMP_LDT (TAG(0x08) | CTYP_INFRASTR_NOTYPE)
|
||||
#define CID_COMP_CPUCONN (TAG(0x09) | CTYP_INFRASTR_NOTYPE)
|
||||
#define CID_COMP_COMMQUE (TAG(0x0A) | CTYP_INFRASTR_NOTYPE)
|
||||
#define CID_COMP_BSLMGR (TAG(0x0B) | CTYP_INFRASTR_NOTYPE)
|
||||
#define CID_COMP_CR (TAG(0x0C) | CTYP_INFRASTR_NOTYPE)
|
||||
#define CID_COMP_NODE (TAG(0x0D) | CTYP_INFRASTR_NOTYPE)
|
||||
#define CID_COMP_COM (TAG(0x0E) | CTYP_INFRASTR_NOTYPE)
|
||||
#define CID_COMP_UTIL (TAG(0x0F) | CTYP_INFRASTR_NOTYPE)
|
||||
#define CID_COMP_SGLIST (TAG(0x10) | CTYP_INFRASTR_NOTYPE)
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
// Component Standard Error/Progress Status definitions (bits 11:0, 12 bits)
|
||||
// NOTE: These status codes are OR'd with the component identifier to create
|
||||
// component unique 32 bit status values. The component status values
|
||||
// should be defined in the header files where the APIs are defined.
|
||||
*/
|
||||
#define CID_ERR_BITMASK 0xFFF /* Component error AND bitmask */
|
||||
#define CID_ERR_BITSHIFT 0 /* Component error bit shift */
|
||||
#define CID_GET_ERROR(compId) ((compId & CID_ERR_BITMASK) >> CID_ERR_BITSHIFT)
|
||||
|
||||
#define TM_ERR_COMPATIBILITY 0x001 /* SW Interface compatibility */
|
||||
#define TM_ERR_MAJOR_VERSION 0x002 /* SW Major Version error */
|
||||
#define TM_ERR_COMP_VERSION 0x003 /* SW component version error */
|
||||
#define TM_ERR_BAD_MODULE_ID 0x004 /* SW - HW module ID error */
|
||||
#define TM_ERR_BAD_UNIT_NUMBER 0x005 /* Invalid device unit number */
|
||||
#define TM_ERR_BAD_INSTANCE 0x006 /* Bad input instance value */
|
||||
#define TM_ERR_BAD_HANDLE 0x007 /* Bad input handle */
|
||||
#define TM_ERR_BAD_INDEX 0x008 /* Bad input index */
|
||||
#define TM_ERR_BAD_PARAMETER 0x009 /* Invalid input parameter */
|
||||
#define TM_ERR_NO_INSTANCES 0x00A /* No instances available */
|
||||
#define TM_ERR_NO_COMPONENT 0x00B /* Component is not present */
|
||||
#define TM_ERR_NO_RESOURCES 0x00C /* Resource is not available */
|
||||
#define TM_ERR_INSTANCE_IN_USE 0x00D /* Instance is already in use */
|
||||
#define TM_ERR_RESOURCE_OWNED 0x00E /* Resource is already in use */
|
||||
#define TM_ERR_RESOURCE_NOT_OWNED 0x00F /* Caller does not own resource */
|
||||
#define TM_ERR_INCONSISTENT_PARAMS 0x010 /* Inconsistent input params */
|
||||
#define TM_ERR_NOT_INITIALIZED 0x011 /* Component is not initialized */
|
||||
#define TM_ERR_NOT_ENABLED 0x012 /* Component is not enabled */
|
||||
#define TM_ERR_NOT_SUPPORTED 0x013 /* Function is not supported */
|
||||
#define TM_ERR_INIT_FAILED 0x014 /* Initialization failed */
|
||||
#define TM_ERR_BUSY 0x015 /* Component is busy */
|
||||
#define TM_ERR_NOT_BUSY 0x016 /* Component is not busy */
|
||||
#define TM_ERR_READ 0x017 /* Read error */
|
||||
#define TM_ERR_WRITE 0x018 /* Write error */
|
||||
#define TM_ERR_ERASE 0x019 /* Erase error */
|
||||
#define TM_ERR_LOCK 0x01A /* Lock error */
|
||||
#define TM_ERR_UNLOCK 0x01B /* Unlock error */
|
||||
#define TM_ERR_OUT_OF_MEMORY 0x01C /* Memory allocation failed */
|
||||
#define TM_ERR_BAD_VIRT_ADDRESS 0x01D /* Bad virtual address */
|
||||
#define TM_ERR_BAD_PHYS_ADDRESS 0x01E /* Bad physical address */
|
||||
#define TM_ERR_TIMEOUT 0x01F /* Timeout error */
|
||||
#define TM_ERR_OVERFLOW 0x020 /* Data overflow/overrun error */
|
||||
#define TM_ERR_FULL 0x021 /* Queue (etc.) is full */
|
||||
#define TM_ERR_EMPTY 0x022 /* Queue (etc.) is empty */
|
||||
#define TM_ERR_NOT_STARTED 0x023 /* Component stream not started */
|
||||
#define TM_ERR_ALREADY_STARTED 0x024 /* Comp. stream already started */
|
||||
#define TM_ERR_NOT_STOPPED 0x025 /* Component stream not stopped */
|
||||
#define TM_ERR_ALREADY_STOPPED 0x026 /* Comp. stream already stopped */
|
||||
#define TM_ERR_ALREADY_SETUP 0x027 /* Component already setup */
|
||||
#define TM_ERR_NULL_PARAMETER 0x028 /* Null input parameter */
|
||||
#define TM_ERR_NULL_DATAINFUNC 0x029 /* Null data input function */
|
||||
#define TM_ERR_NULL_DATAOUTFUNC 0x02A /* Null data output function */
|
||||
#define TM_ERR_NULL_CONTROLFUNC 0x02B /* Null control function */
|
||||
#define TM_ERR_NULL_COMPLETIONFUNC 0x02C /* Null completion function */
|
||||
#define TM_ERR_NULL_PROGRESSFUNC 0x02D /* Null progress function */
|
||||
#define TM_ERR_NULL_ERRORFUNC 0x02E /* Null error handler function */
|
||||
#define TM_ERR_NULL_MEMALLOCFUNC 0x02F /* Null memory alloc function */
|
||||
#define TM_ERR_NULL_MEMFREEFUNC 0x030 /* Null memory free function */
|
||||
#define TM_ERR_NULL_CONFIGFUNC 0x031 /* Null configuration function */
|
||||
#define TM_ERR_NULL_PARENT 0x032 /* Null parent data */
|
||||
#define TM_ERR_NULL_IODESC 0x033 /* Null in/out descriptor */
|
||||
#define TM_ERR_NULL_CTRLDESC 0x034 /* Null control descriptor */
|
||||
#define TM_ERR_UNSUPPORTED_DATACLASS 0x035 /* Unsupported data class */
|
||||
#define TM_ERR_UNSUPPORTED_DATATYPE 0x036 /* Unsupported data type */
|
||||
#define TM_ERR_UNSUPPORTED_DATASUBTYPE 0x037 /* Unsupported data subtype */
|
||||
#define TM_ERR_FORMAT 0x038 /* Invalid/unsupported format */
|
||||
#define TM_ERR_INPUT_DESC_FLAGS 0x039 /* Bad input descriptor flags */
|
||||
#define TM_ERR_OUTPUT_DESC_FLAGS 0x03A /* Bad output descriptor flags */
|
||||
#define TM_ERR_CAP_REQUIRED 0x03B /* Capabilities required ??? */
|
||||
#define TM_ERR_BAD_TMALFUNC_TABLE 0x03C /* Bad TMAL function table */
|
||||
#define TM_ERR_INVALID_CHANNEL_ID 0x03D /* Invalid channel identifier */
|
||||
#define TM_ERR_INVALID_COMMAND 0x03E /* Invalid command/request */
|
||||
#define TM_ERR_STREAM_MODE_CONFUSION 0x03F /* Stream mode config conflict */
|
||||
#define TM_ERR_UNDERRUN 0x040 /* Data underflow/underrun */
|
||||
#define TM_ERR_EMPTY_PACKET_RECVD 0x041 /* Empty data packet received */
|
||||
#define TM_ERR_OTHER_DATAINOUT_ERR 0x042 /* Other data input/output err */
|
||||
#define TM_ERR_STOP_REQUESTED 0x043 /* Stop in progress */
|
||||
#define TM_ERR_PIN_NOT_STARTED 0x044 /* Pin not started */
|
||||
#define TM_ERR_PIN_ALREADY_STARTED 0x045 /* Pin already started */
|
||||
#define TM_ERR_PIN_NOT_STOPPED 0x046 /* Pin not stopped */
|
||||
#define TM_ERR_PIN_ALREADY_STOPPED 0x047 /* Pin already stopped */
|
||||
#define TM_ERR_STOP_PIN_REQUESTED 0x048 /* Stop of a single pin is in progress (obsolescent) */
|
||||
#define TM_ERR_PAUSE_PIN_REQUESTED 0x048 /* Stop of a single pin is in progress */
|
||||
#define TM_ERR_ASSERTION 0x049 /* Assertion failure */
|
||||
#define TM_ERR_HIGHWAY_BANDWIDTH 0x04A /* Highway bandwidth bus error */
|
||||
#define TM_ERR_HW_RESET_FAILED 0x04B /* Hardware reset failed */
|
||||
#define TM_ERR_PIN_PAUSED 0x04C /* Pin Paused */
|
||||
|
||||
/* Add new standard error/progress status codes here */
|
||||
|
||||
#define TM_ERR_COMP_UNIQUE_START 0x800 /* 0x800-0xDFF: Component unique */
|
||||
|
||||
#define TM_ERR_CUSTOMER_START 0xC00
|
||||
|
||||
/* DVP Standard assert error code start offset
|
||||
// NOTE: This define should be added to the component's base error value and
|
||||
// standard error code(s) to define assert error codes. For example:
|
||||
// #define TMBSL_ERR_MGR_ASSERT_BAD_PARAM
|
||||
// (TMBSL_ERR_MGR_BASE + TM_ERR_ASSERT_START + TM_ERR_BAD_PARAMETER)
|
||||
*/
|
||||
#define TM_ERR_ASSERT_START 0xE00 /* 0xE00-0xEFF: Assert failures */
|
||||
#define TM_ERR_ASSERT_LAST 0xEFF /* Last assert error range value */
|
||||
#define CID_IS_ASSERT_ERROR(compId) \
|
||||
((CID_GET_ERROR(compId) >= TM_ERR_ASSERT_START) && \
|
||||
(CID_GET_ERROR(compId) <= TM_ERR_ASSERT_LAST))
|
||||
|
||||
/* DVP Standard fatal error code start offset
|
||||
// NOTE: This define should be added to the component's base error value and
|
||||
// standard error code(s) to define fatal error codes. For example:
|
||||
// #define TMML_ERR_FATAL_OUT_OF_MEMORY
|
||||
// (TMML_ERR_BASE + TM_ERR_FATAL_START + TM_ERR_OUT_OF_MEMORY)
|
||||
*/
|
||||
#define TM_ERR_FATAL_START 0xF00 /* 0xF00-0xFFF: Fatal failures */
|
||||
#define TM_ERR_FATAL_LAST 0xFFF /* Last fatal error range value */
|
||||
#define CID_IS_FATAL_ERROR(compId) \
|
||||
((CID_GET_ERROR(compId) >= TM_ERR_FATAL_START) && \
|
||||
(CID_GET_ERROR(compId) <= TM_ERR_FATAL_LAST))
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
// DVP hardware module IDs
|
||||
*/
|
||||
#define VMPG_100_MOD_ID 0x00000100
|
||||
#define C1394_101_MOD_ID 0x00000101
|
||||
#define FPBC_102_MOD_ID 0x00000102
|
||||
#define JTAG_103_MOD_ID 0x00000103
|
||||
#define EJTAG_104_MOD_ID 0x00000104
|
||||
#define IIC_105_MOD_ID 0x00000105
|
||||
#define SMCARD_106_MOD_ID 0x00000106
|
||||
#define UART_107_MOD_ID 0x00000107
|
||||
/* #define CLOCKS_108_MOD_ID 0x00000108 */
|
||||
#define USB_109_MOD_ID 0x00000109
|
||||
#define BOOT_10A_MOD_ID 0x0000010A
|
||||
#define MPBC_10B_MOD_ID 0x0000010B
|
||||
#define SSI_10C_MOD_ID 0x0000010C
|
||||
#define AI_10D_MOD_ID 0x0000010D
|
||||
#define VMSP_10E_MOD_ID 0x0000010E
|
||||
#define GPIO_10F_MOD_ID 0x0000010F
|
||||
#define SPDI_110_MOD_ID 0x00000110
|
||||
#define AICP_111_MOD_ID 0x00000111
|
||||
#define TPBC_112_MOD_ID 0x00000112
|
||||
#define PCI_113_MOD_ID 0x00000113
|
||||
#define MMI_114_MOD_ID 0x00000114
|
||||
#define ORCA3_115_MOD_ID 0x00000115
|
||||
#define DBG_116_MOD_ID 0x00000116
|
||||
#define DE_117_MOD_ID 0x00000117
|
||||
#define AICP_118_MOD_ID 0x00000118
|
||||
#define MBS_119_MOD_ID 0x00000119
|
||||
#define VIP_11A_MOD_ID 0x0000011A
|
||||
#define PIMI_11B_MOD_ID 0x0000011B
|
||||
#define PIB_11C_MOD_ID 0x0000011C
|
||||
#define PIC_11D_MOD_ID 0x0000011D
|
||||
#define TMDBG_11F_MOD_ID 0x0000011F
|
||||
#define AO_120_MOD_ID 0x00000120
|
||||
#define SPDO_121_MOD_ID 0x00000121
|
||||
#define FPIMI_122_MOD_ID 0x00000122
|
||||
#define RESET_123_MOD_ID 0x00000123
|
||||
#define NULL_124_MOD_ID 0x00000124
|
||||
#define TSDMA_125_MOD_ID 0x00000125
|
||||
#define GLBREG_126_MOD_ID 0x00000126
|
||||
#define TMDBG_127_MOD_ID 0x00000127
|
||||
#define GLBREG_128_MOD_ID 0x00000128
|
||||
#define DMA_130_MOD_ID 0x00000130
|
||||
#define IR_131_MOD_ID 0x00000131
|
||||
#define GFX2D_131_MOD_ID 0x00000132 /* TODO: Remove after code corrected */
|
||||
#define GFX2D_132_MOD_ID 0x00000132
|
||||
#define P1284_133_MOD_ID 0x00000133
|
||||
#define QNM_134_MOD_ID 0x00000134
|
||||
#define OSD_136_MOD_ID 0x00000136
|
||||
#define MIX_137_MOD_ID 0x00000137
|
||||
#define DENC_138_MOD_ID 0x00000138
|
||||
#define SYN_13A_MOD_ID 0x0000013A
|
||||
#define CLOCKS_13E_MOD_ID 0x0000013E
|
||||
#define CONFIG_13F_MOD_ID 0x0000013F
|
||||
#define MIU_A04C_MOD_ID 0x0000A04C
|
||||
#define DISP_A04D_MOD_ID 0x0000A04D
|
||||
#define VCTRL_A04E_MOD_ID 0x0000A04E
|
||||
|
||||
|
||||
#define PR3930_2B10_MOD_ID 0x00002B10
|
||||
#define PR3940_2B11_MOD_ID 0x00002B11
|
||||
|
||||
#define TM3218_2B80_MOD_ID 0x00002B80
|
||||
#define TM64_2b81_MOD_ID 0x00002B81
|
||||
|
||||
#define QNM_A017_MOD_ID 0x0000A017
|
||||
|
||||
/* There is no HW module ID for TS IO ROUTER. We assign
|
||||
// a SW module ID to this module, because it is needed by Clock
|
||||
// device and HWAPI libraries. Use 010Eh for lower word
|
||||
// (for lack of better reason ! because IO Router is closely
|
||||
// associated with VMSP module)
|
||||
*/
|
||||
|
||||
#define IORT_1010E_MOD_ID 0x0001010E
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* TM_COMP_ID_H */
|
||||
|
||||
@@ -0,0 +1,120 @@
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* (C) Copyright 2000 Koninklijke Philips Electronics N.V., All Rights Reserved */
|
||||
/* */
|
||||
/* This source code and any compilation or derivative thereof is the sole */
|
||||
/* property of Philips Corporation and is provided pursuant to a Software */
|
||||
/* License Agreement. This code is the proprietary information of */
|
||||
/* Philips Corporation and is confidential in nature. Its use and */
|
||||
/* dissemination by any party other than Philips Corporation is strictly */
|
||||
/* limited by the confidential information provisions of the Agreement */
|
||||
/* referenced above. */
|
||||
/*------------------------------------------------------------------------------*/
|
||||
|
||||
/* DOCUMENT REF: DVP Build Process Specification */
|
||||
/* */
|
||||
/* NOTES: This file defines the TMFL_xxx build flags. */
|
||||
/* */
|
||||
#if !defined(_TMFLAGS_H_SEEN_)
|
||||
#define _TMFLAGS_H_SEEN_
|
||||
/* Configuration */
|
||||
/* */
|
||||
/* FILENAME: tmFlags.h */
|
||||
/* */
|
||||
/* DESCRIPTION: Generated by */
|
||||
#define TMFL_BUILD_VERSION 00.00.00
|
||||
#define TMFL_CPU 0x00020011
|
||||
#define TMFL_ENDIAN 0
|
||||
#define TMFL_OS 0x03020500
|
||||
#define TMFL_CPU_IS_X86 1
|
||||
#define TMFL_CPU_IS_MIPS 0
|
||||
#define TMFL_CPU_IS_HP 0
|
||||
#define TMFL_CPU_IS_TM 0
|
||||
#define TMFL_CPU_IS_ARM 0
|
||||
#define TMFL_CPU_IS_REAL 0
|
||||
#define TMFL_OS_IS_BTM 0
|
||||
#define TMFL_OS_IS_CE 0
|
||||
#define TMFL_OS_IS_NT 1
|
||||
#define TMFL_OS_IS_PSOS 0
|
||||
#define TMFL_OS_IS_NULLOS 0
|
||||
#define TMFL_OS_IS_ECOS 0
|
||||
#define TMFL_OS_IS_VXWORKS 0
|
||||
#define TMFL_OS_IS_MTOS 0
|
||||
#define TMFL_OS_IS_CEXEC 0
|
||||
/* DO NOT CHANGE THIS FILE INDEPENDENTLY !!! */
|
||||
/* IT MUST BE SYNCHONISED WITH THE TMFLAGS TEMPLATE FILE ON THE */
|
||||
/* MOREUSE WEB SITE http://pww.rtg.sc.philips.com/cmd/html/global_files.html */
|
||||
/* CONTACT MOREUSE BEFORE ADDING NEW VALUES */
|
||||
/* constants */
|
||||
#define TMFL_CPU_TYPE_MASK 0xffff0000
|
||||
#define TMFL_CPU_TYPE_X86 0x00010000
|
||||
#define TMFL_CPU_TYPE_MIPS 0x00020000
|
||||
#define TMFL_CPU_TYPE_TM 0x00030000
|
||||
#define TMFL_CPU_TYPE_HP 0x00040000
|
||||
#define TMFL_CPU_TYPE_ARM 0x00050000
|
||||
#define TMFL_CPU_TYPE_REAL 0x00060000
|
||||
#define TMFL_CPU_MODEL_MASK 0x0000ffff
|
||||
#define TMFL_CPU_MODEL_I486 0x00000001
|
||||
#define TMFL_CPU_MODEL_R3940 0x00000002
|
||||
#define TMFL_CPU_MODEL_R4300 0x00000003
|
||||
#define TMFL_CPU_MODEL_TM1100 0x00000004
|
||||
#define TMFL_CPU_MODEL_TM1300 0x00000005
|
||||
#define TMFL_CPU_MODEL_TM32 0x00000006
|
||||
#define TMFL_CPU_MODEL_HP 0x00000007
|
||||
#define TMFL_CPU_MODEL_R4640 0x00000008
|
||||
#define TMFL_CPU_MODEL_ARM7 0x00000009
|
||||
#define TMFL_CPU_MODEL_ARM920T 0x0000000a
|
||||
#define TMFL_CPU_MODEL_ARM940T 0x0000000b
|
||||
#define TMFL_CPU_MODEL_ARM10 0x0000000c
|
||||
#define TMFL_CPU_MODEL_STRONGARM 0x0000000d
|
||||
#define TMFL_CPU_MODEL_RD24120 0x0000000e
|
||||
#define TMFL_CPU_MODEL_ARM926EJS 0x0000000f
|
||||
#define TMFL_CPU_MODEL_ARM946 0x00000010
|
||||
#define TMFL_CPU_MODEL_R1910 0x00000011
|
||||
#define TMFL_CPU_MODEL_R4450 0x00000012
|
||||
#define TMFL_CPU_MODEL_TM3260 0x00000013
|
||||
#define TMFL_ENDIAN_BIG 1
|
||||
#define TMFL_ENDIAN_LITTLE 0
|
||||
#define TMFL_OS_MASK 0xff000000
|
||||
#define TMFL_OS_VERSION_MASK 0x00ffffff
|
||||
#define TMFL_OS_BTM 0x00000000
|
||||
#define TMFL_OS_CE 0x01000000
|
||||
#define TMFL_OS_CE212 0x01020102
|
||||
#define TMFL_OS_CE300 0x01030000
|
||||
#define TMFL_OS_NT 0x02000000
|
||||
#define TMFL_OS_NT4 0x02040000
|
||||
#define TMFL_OS_PSOS 0x03000000
|
||||
#define TMFL_OS_PSOS250 0x03020500
|
||||
#define TMFL_OS_PSOS200 0x03020000
|
||||
#define TMFL_OS_NULLOS 0x04000000
|
||||
#define TMFL_OS_ECOS 0x05000000
|
||||
#define TMFL_OS_VXWORKS 0x06000000
|
||||
#define TMFL_OS_MTOS 0x07000000
|
||||
#define TMFL_OS_CEXEC 0x08000000
|
||||
#define TMFL_SCOPE_SP 0
|
||||
#define TMFL_SCOPE_MP 1
|
||||
#define TMFL_REL_ASSERT 0x00000002
|
||||
#define TMFL_REL_DEBUG 0x00000001
|
||||
#define TMFL_REL_RETAIL 0x00000000
|
||||
#define TMFL_CPU_I486 0x00010001
|
||||
#define TMFL_CPU_R3940 0x00020002
|
||||
#define TMFL_CPU_R4300 0x00020003
|
||||
#define TMFL_CPU_TM1100 0x00030004
|
||||
#define TMFL_CPU_TM1300 0x00030005
|
||||
#define TMFL_CPU_TM32 0x00030006
|
||||
#define TMFL_CPU_HP 0x00040007
|
||||
#define TMFL_CPU_R4640 0x00020008
|
||||
#define TMFL_CPU_ARM7 0x00050009
|
||||
#define TMFL_CPU_ARM920T 0x0005000a
|
||||
#define TMFL_CPU_ARM940T 0x0005000b
|
||||
#define TMFL_CPU_ARM10 0x0005000c
|
||||
#define TMFL_CPU_STRONGARM 0x0005000d
|
||||
#define TMFL_CPU_RD24120 0x0006000e
|
||||
#define TMFL_CPU_ARM926EJS 0x0005000f
|
||||
#define TMFL_CPU_ARM946 0x00050010
|
||||
#define TMFL_CPU_R1910 0x00020011
|
||||
#define TMFL_CPU_R4450 0x00020012
|
||||
#define TMFL_CPU_TM3260 0x00030013
|
||||
#define TMFL_MODE_KERNEL 1
|
||||
#define TMFL_MODE_USER 0
|
||||
|
||||
#endif /* !defined(_TMFLAGS_H_SEEN_) */
|
||||
@@ -0,0 +1,297 @@
|
||||
/**
|
||||
Copyright (C) 2007 NXP B.V., All Rights Reserved.
|
||||
This source code and any compilation or derivative thereof is the proprietary
|
||||
information of NXP B.V. and is confidential in nature. Under no circumstances
|
||||
is this software to be exposed to or placed under an Open Source License of
|
||||
any type without the expressed written permission of NXP B.V.
|
||||
*
|
||||
* \file tmFrontEnd.h
|
||||
* %version: CFR_FEAP#1 %
|
||||
*
|
||||
* \date %date_modified%
|
||||
*
|
||||
* \brief Describe briefly the purpose of this file.
|
||||
*
|
||||
* REFERENCE DOCUMENTS :
|
||||
*
|
||||
* Detailed description may be added here.
|
||||
*
|
||||
* \section info Change Information
|
||||
*
|
||||
* \verbatim
|
||||
Date Modified by CRPRNr TASKNr Maintenance description
|
||||
-------------|-----------|-------|-------|-----------------------------------
|
||||
26-Mar-2008 | B.GUILLOT | 13122 | 23456 | Creation
|
||||
-------------|-----------|-------|-------|-----------------------------------
|
||||
\endverbatim
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#ifndef TMFRONTEND_H
|
||||
#define TMFRONTEND_H
|
||||
|
||||
/*============================================================================*/
|
||||
/* INCLUDE FILES */
|
||||
/*============================================================================*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "tmNxTypes.h"
|
||||
|
||||
|
||||
/*============================================================================*/
|
||||
/* ENUM OR TYPE DEFINITION */
|
||||
/*============================================================================*/
|
||||
#define TMFRONTEND_DVBT2MAXPLPNB 250
|
||||
|
||||
/* standard*/
|
||||
typedef enum _tmFrontEndStandard_t {
|
||||
tmFrontEndStandardDVBT = 0,
|
||||
tmFrontEndStandardDVBS,
|
||||
tmFrontEndStandardDVBC,
|
||||
tmFrontEndStandardDSS,
|
||||
tmFrontEndStandardBSD,
|
||||
tmFrontEndStandardDVBH,
|
||||
tmFrontEndStandardAnalogDVBT,
|
||||
tmFrontEndStandardDVBS2,
|
||||
tmFrontEndStandardDVBT2,
|
||||
tmFrontEndStandardMax
|
||||
} tmFrontEndStandard_t, *ptmFrontEndStandard_t;
|
||||
|
||||
/* spectral inversion*/
|
||||
typedef enum _tmFrontEndSpecInv_t {
|
||||
tmFrontEndSpecInvAuto = 0,
|
||||
tmFrontEndSpecInvOff,
|
||||
tmFrontEndSpecInvOn,
|
||||
tmFrontEndSpecInvMax
|
||||
} tmFrontEndSpecInv_t, *ptmFrontEndSpecInv_t;
|
||||
|
||||
/* modulation*/
|
||||
typedef enum _tmFrontEndModulation_t {
|
||||
tmFrontEndModulationAuto = 0,
|
||||
tmFrontEndModulationBpsk,
|
||||
tmFrontEndModulationQpsk,
|
||||
tmFrontEndModulationQam4,
|
||||
tmFrontEndModulationPsk8,
|
||||
tmFrontEndModulationQam16,
|
||||
tmFrontEndModulationQam32,
|
||||
tmFrontEndModulationQam64,
|
||||
tmFrontEndModulationQam128,
|
||||
tmFrontEndModulationQam256,
|
||||
tmFrontEndModulationQam512,
|
||||
tmFrontEndModulationQam1024,
|
||||
tmFrontEndModulation8VSB,
|
||||
tmFrontEndModulation16VSB,
|
||||
tmFrontEndModulationQam,
|
||||
tmFrontEndModulationMax
|
||||
} tmFrontEndModulation_t, *ptmFrontEndModulation_t;
|
||||
|
||||
/* viterbi rate*/
|
||||
typedef enum _tmFrontEndCodeRate_t {
|
||||
tmFrontEndCodeRateAuto = 0,
|
||||
tmFrontEndCodeRate_1_4,
|
||||
tmFrontEndCodeRate_1_3,
|
||||
tmFrontEndCodeRate_2_5,
|
||||
tmFrontEndCodeRate_1_2,
|
||||
tmFrontEndCodeRate_3_5,
|
||||
tmFrontEndCodeRate_2_3,
|
||||
tmFrontEndCodeRate_3_4,
|
||||
tmFrontEndCodeRate_4_5,
|
||||
tmFrontEndCodeRate_5_6,
|
||||
tmFrontEndCodeRate_6_7,
|
||||
tmFrontEndCodeRate_7_8,
|
||||
tmFrontEndCodeRate_8_9,
|
||||
tmFrontEndCodeRate_9_10,
|
||||
tmFrontEndCodeRate_NotRelevant,
|
||||
tmFrontEndCodeRateMax
|
||||
} tmFrontEndCodeRate_t, *ptmFrontEndCodeRate_t;
|
||||
|
||||
/* frequency offset*/
|
||||
typedef enum _tmFrontEndRfOffset_t {
|
||||
tmFrontEndRfOffsetAuto = 0,
|
||||
tmFrontEndRfOffsetNull,
|
||||
tmFrontEndRfOffsetPlus125,
|
||||
tmFrontEndRfOffsetMinus125,
|
||||
tmFrontEndRfOffsetPlus166,
|
||||
tmFrontEndRfOffsetMinus166,
|
||||
tmFrontEndRfOffsetPlus333,
|
||||
tmFrontEndRfOffsetMinus333,
|
||||
tmFrontEndRfOffsetPlus500,
|
||||
tmFrontEndRfOffsetMinus500,
|
||||
tmFrontEndRfOffsetMax
|
||||
} tmFrontEndRfOffset_t, *ptmFrontEndRfOffset_t;
|
||||
|
||||
/* frequency offset*/
|
||||
typedef enum _tmFrontEndRfOffsetMode_t {
|
||||
tmFrontEndRfOffsetModeAuto,
|
||||
tmFrontEndRfOffsetModeManual,
|
||||
tmFrontEndRfOffsetModeMax
|
||||
} tmFrontEndRfOffsetMode_t, *ptmFrontEndRfOffsetMode_t;
|
||||
|
||||
/* guard interval*/
|
||||
typedef enum _tmFrontEndGI_t {
|
||||
tmFrontEndGIAuto = 0,
|
||||
tmFrontEndGI_1_32,
|
||||
tmFrontEndGI_1_16,
|
||||
tmFrontEndGI_1_8,
|
||||
tmFrontEndGI_1_4,
|
||||
tmFrontEndGI_1_128,
|
||||
tmFrontEndGI_19_128,
|
||||
tmFrontEndGI_19_256,
|
||||
tmFrontEndGIMax
|
||||
} tmFrontEndGI_t, *ptmFrontEndGI_t;
|
||||
|
||||
/* fast Fourrier transform size*/
|
||||
typedef enum _tmFrontEndFft_t {
|
||||
tmFrontEndFftAuto = 0,
|
||||
tmFrontEndFft2K,
|
||||
tmFrontEndFft8K,
|
||||
tmFrontEndFft4K,
|
||||
tmFrontEndFft16K,
|
||||
tmFrontEndFft32K,
|
||||
tmFrontEndFftMax
|
||||
} tmFrontEndFft_t, *ptmFrontEndFft_t;
|
||||
|
||||
/* hierarchy*/
|
||||
typedef enum _tmFrontEndHier_t {
|
||||
tmFrontEndHierAuto = 0,
|
||||
tmFrontEndHierNo,
|
||||
tmFrontEndHierAlpha1,
|
||||
tmFrontEndHierAlpha2,
|
||||
tmFrontEndHierAlpha4,
|
||||
tmFrontEndHierMax
|
||||
} tmFrontEndHier_t, *ptmFrontEndHier_t;
|
||||
|
||||
/* priority*/
|
||||
typedef enum _tmFrontEndPrior_t {
|
||||
tmFrontEndPriorAuto = 0,
|
||||
tmFrontEndPriorHigh,
|
||||
tmFrontEndPriorLow,
|
||||
tmFrontEndPriorMax
|
||||
} tmFrontEndPrior_t, *ptmFrontEndPrior_t;
|
||||
|
||||
/* roll off */
|
||||
typedef enum _tmFrontEndRollOff_t {
|
||||
tmFrontEndRollOffAuto = 0,
|
||||
tmFrontEndRollOff_0_15,
|
||||
tmFrontEndRollOff_0_20,
|
||||
tmFrontEndRollOff_0_25,
|
||||
tmFrontEndRollOff_0_35,
|
||||
tmFrontEndRollOffMax
|
||||
} tmFrontEndRollOff_t, *ptmFrontEndRollOff_t;
|
||||
|
||||
/* LNB polarity */
|
||||
typedef enum _tmFrontEndLNBPolarity_t {
|
||||
tmFrontEndLNBPolarityAuto = 0,
|
||||
tmFrontEndLNBPolarityHigh,
|
||||
tmFrontEndLNBPolarityLow,
|
||||
tmFrontEndLNBPolarityMax
|
||||
} tmFrontEndLNBPolarity_t, *ptmFrontEndLNBPolarity_t;
|
||||
|
||||
/* continuous tone */
|
||||
typedef enum _tmFrontEndContinuousTone_t {
|
||||
tmFrontEndContinuousToneAuto = 0,
|
||||
tmFrontEndContinuousToneOff,
|
||||
tmFrontEndContinuousTone22KHz,
|
||||
tmFrontEndContinuousToneMax
|
||||
} tmFrontEndContinuousTone_t, *ptmFrontEndContinuousTone_t;
|
||||
|
||||
typedef enum _tmFrontEndChannelType_t
|
||||
{
|
||||
tmFrontEndChannelTypeNone = 0x00, /* No detection */
|
||||
tmFrontEndChannelTypeDigital = 0x01, /* Digital channel */
|
||||
tmFrontEndChannelTypeAnalog = 0x02, /* Analog channel */
|
||||
tmFrontEndChannelTypeUnknown = 0x20 /* unknown channel type */
|
||||
} tmFrontEndChannelType_t;
|
||||
|
||||
typedef enum _tmFrontEndChannelConfidence_t
|
||||
{
|
||||
tmFrontEndConfidenceNotAvailable,
|
||||
tmFrontEndConfidenceNull,
|
||||
tmFrontEndConfidenceLow,
|
||||
tmFrontEndConfidenceMedium,
|
||||
tmFrontEndConfidenceHigh
|
||||
} tmFrontEndConfidence_t;
|
||||
|
||||
typedef enum _tmFrontEndDVBT2PLPType_t
|
||||
{
|
||||
tmFrontEndDVBT2PLPTypeAuto,
|
||||
tmFrontEndDVBT2PLPTypeCommon,
|
||||
tmFrontEndDVBT2PLPType1,
|
||||
tmFrontEndDVBT2PLPType2,
|
||||
tmFrontEndDVBT2PLPTypeMax
|
||||
} tmFrontEndDVBT2PLPType_t;
|
||||
|
||||
typedef enum _tmFrontEndDVBT2PLPPayloadType_t
|
||||
{
|
||||
tmFrontEndDVBT2PLPPayloadTypeAuto,
|
||||
tmFrontEndDVBT2PLPPayloadTypeGFPS,
|
||||
tmFrontEndDVBT2PLPPayloadTypeGCS,
|
||||
tmFrontEndDVBT2PLPPayloadTypeGSE,
|
||||
tmFrontEndDVBT2PLPPayloadTypeTS,
|
||||
tmFrontEndDVBT2PLPPayloadTypeMax
|
||||
} tmFrontEndDVBT2PLPPayloadType_t;
|
||||
|
||||
typedef enum _tmFrontEndRotationState_t
|
||||
{
|
||||
tmFrontEndRotationStateAuto,
|
||||
tmFrontEndRotationStateOn,
|
||||
tmFrontEndRotationStateOff,
|
||||
tmFrontEndRotationStateMax
|
||||
} tmFrontEndRotationState;
|
||||
|
||||
typedef enum _tmFrontEndDVBT2FECType_t
|
||||
{
|
||||
tmFrontEndDVBT2FECTypeAuto,
|
||||
tmFrontEndDVBT2FECType16K,
|
||||
tmFrontEndDVBT2FECType64K,
|
||||
tmFrontEndDVBT2FECTypeMax
|
||||
} tmFrontEndDVBT2FECType_t;
|
||||
|
||||
typedef enum _tmFrontEndDVBT2InputType_t
|
||||
{
|
||||
tmFrontEndDVBT2InputTypeAuto,
|
||||
tmFrontEndDVBT2InputTypeSISO,
|
||||
tmFrontEndDVBT2InputTypeMISO,
|
||||
tmFrontEndDVBT2InputTypeMax
|
||||
} tmFrontEndDVBT2InputType_t;
|
||||
|
||||
typedef enum _tmFrontEndFECMode_t
|
||||
{
|
||||
tmFrontEndFECModeUnknown = 0,
|
||||
tmFrontEndFECModeAnnexA,
|
||||
tmFrontEndFECModeAnnexB,
|
||||
tmFrontEndFECModeAnnexC,
|
||||
tmFrontEndFECModeMax
|
||||
} tmFrontEndFECMode_t;
|
||||
|
||||
typedef struct _tmFrontEndFracNb8_t
|
||||
{
|
||||
Int8 lInteger;
|
||||
UInt8 uDivider;
|
||||
}tmFrontEndFracNb8_t;
|
||||
|
||||
typedef struct _tmFrontEndFracNb16_t
|
||||
{
|
||||
Int16 lInteger;
|
||||
UInt16 uDivider;
|
||||
}tmFrontEndFracNb16_t;
|
||||
|
||||
typedef struct _tmFrontEndFracNb32_t
|
||||
{
|
||||
Int32 lInteger;
|
||||
UInt32 uDivider;
|
||||
}tmFrontEndFracNb32_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* TMFRONTEND_H */
|
||||
/*============================================================================*/
|
||||
/* END OF FILE */
|
||||
/*============================================================================*/
|
||||
@@ -0,0 +1,50 @@
|
||||
|
||||
/* Copyright (C) 2006 Koninklijke Philips Electronics N.V.
|
||||
All Rights Reserved.
|
||||
This source code and any compilation or derivative thereof is the
|
||||
proprietary information of Koninklijke Philips Electronics N.V. and is
|
||||
confidential in nature.
|
||||
Under no circumstances is this software to be exposed to or placed under an
|
||||
Open Source License of any type without the expressed written permission of
|
||||
Koninklijke Philips Electronics N.V.
|
||||
*//**
|
||||
@file tmNxCompId.h
|
||||
@brief Brief description of this h file.
|
||||
|
||||
@b Component: n/a
|
||||
|
||||
This is a temporary workaround to assist integration of STB810 components
|
||||
into the STB225 project. STB810 uses the newer 'tmNxCompId.h' naming
|
||||
convention, while existing STB225 include 'tmCompId.h'.
|
||||
|
||||
Set your editor for 4 space indentation.
|
||||
*//*
|
||||
|
||||
Rev Date Author Comments
|
||||
--------------------------------------------------------------------------------
|
||||
001 20060605 G.Lawrance Original
|
||||
--------------------------------------------------------------------------------
|
||||
For consistency and standardisation retain the Section Separators.
|
||||
*/
|
||||
#ifndef TM_NX_COMP_ID_H
|
||||
#define TM_NX_COMP_ID_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* -------------------------------------------------------------------------- */
|
||||
/* Project include files: */
|
||||
/* -------------------------------------------------------------------------- */
|
||||
#include "tmCompId.h"
|
||||
|
||||
/* Map tmNxCompId.h onto tmCompId.h */
|
||||
#define CID_STBSTREAMINGSYSTEM CID_COMP_STBSTREAMINGSYSTEM
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* TM_NX_COMP_ID_H */
|
||||
Executable
+372
@@ -0,0 +1,372 @@
|
||||
/*==========================================================================*/
|
||||
/* (Copyright (C) 2003 Koninklijke Philips Electronics N.V. */
|
||||
/* All rights reserved. */
|
||||
/* This source code and any compilation or derivative thereof is the */
|
||||
/* proprietary information of Koninklijke Philips Electronics N.V. */
|
||||
/* and is confidential in nature. */
|
||||
/* Under no circumstances is this software to be exposed to or placed */
|
||||
/* under an Open Source License of any type without the expressed */
|
||||
/* written permission of Koninklijke Philips Electronics N.V. */
|
||||
/*==========================================================================*/
|
||||
/*
|
||||
* Copyright (C) 2000,2001
|
||||
* Koninklijke Philips Electronics N.V.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Copyright (C) 2000,2001 TriMedia Technologies, Inc.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
*############################################################
|
||||
*
|
||||
* Module name : tmNxTypes.h %version: CFR_FEAP#22 %
|
||||
*
|
||||
* Last Update : %date_modified: Tue Jul 8 18:08:00 2003 %
|
||||
*
|
||||
* Description: TriMedia/MIPS global type definitions.
|
||||
*
|
||||
* Document Ref: DVP Software Coding Guidelines Specification
|
||||
* DVP/MoReUse Naming Conventions specification
|
||||
* DVP Software Versioning Specification
|
||||
* DVP Device Library Architecture Specification
|
||||
* DVP Board Support Library Architecture Specification
|
||||
* DVP Hardware API Architecture Specification
|
||||
*
|
||||
*
|
||||
*############################################################
|
||||
*/
|
||||
|
||||
#ifndef TM_NX_TYPES_H
|
||||
#define TM_NX_TYPES_H
|
||||
|
||||
#include "tmFlags.h" /* DVP common build control flags */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
typedef signed char int8;
|
||||
typedef unsigned char uint8;
|
||||
typedef signed short int16;
|
||||
typedef unsigned short uint16;
|
||||
typedef signed int int32;
|
||||
typedef unsigned int uint32;
|
||||
|
||||
/*============================================================================*/
|
||||
/* Environment macros: */
|
||||
/*============================================================================*/
|
||||
|
||||
#ifdef TMFL_NATIVE_C_FORCED
|
||||
#undef TMFL_DOT_NET_2_0_TYPES
|
||||
#undef NXPFE
|
||||
#endif
|
||||
|
||||
/*============================================================================*/
|
||||
/* Standard Types */
|
||||
/*============================================================================*/
|
||||
|
||||
#define False 0
|
||||
#define True 1
|
||||
|
||||
typedef void CVoid; /* Void (typeless) */
|
||||
typedef int CInt; /* machine-natural integer */
|
||||
typedef unsigned int CUInt; /* machine-natural unsigned integer */
|
||||
typedef signed char CInt8; /* 8 bit signed integer */
|
||||
typedef signed short CInt16; /* 16 bit signed integer */
|
||||
typedef signed int CInt32; /* 32 bit signed integer */
|
||||
typedef unsigned char CUInt8; /* 8 bit unsigned integer */
|
||||
typedef unsigned short CUInt16; /* 16 bit unsigned integer */
|
||||
typedef unsigned int CUInt32; /* 32 bit unsigned integer */
|
||||
typedef float CFloat; /* 32 bit floating point */
|
||||
typedef double CDouble; /* 32/64 bit floating point */
|
||||
typedef unsigned int CBool; /* Boolean (True/False) */
|
||||
typedef char CChar; /* character, character array ptr */
|
||||
typedef CUInt32 tmErrorCode_t;
|
||||
typedef CUInt32 tmProgressCode_t;
|
||||
|
||||
/* Endianness */
|
||||
typedef CInt Endian;
|
||||
#define BigEndian 0
|
||||
#define LittleEndian 1
|
||||
|
||||
|
||||
#ifdef TMFL_DOT_NET_2_0_TYPES
|
||||
using namespace System;
|
||||
typedef int Int;
|
||||
typedef SByte Int8;
|
||||
typedef Byte UInt8;
|
||||
typedef float Float32;
|
||||
typedef unsigned int Bool;
|
||||
typedef Void *pVoid;
|
||||
#define Null nullptr
|
||||
|
||||
#else
|
||||
typedef CVoid Void; /* Void (typeless) */
|
||||
typedef CInt Int; /* machine-natural integer */
|
||||
typedef CUInt UInt; /* machine-natural unsigned integer */
|
||||
typedef CInt8 Int8; /* 8 bit signed integer */
|
||||
typedef CInt16 Int16; /* 16 bit signed integer */
|
||||
typedef CInt32 Int32; /* 32 bit signed integer */
|
||||
typedef CUInt8 UInt8; /* 8 bit unsigned integer */
|
||||
typedef CUInt16 UInt16; /* 16 bit unsigned integer */
|
||||
typedef CUInt32 UInt32; /* 32 bit unsigned integer */
|
||||
typedef CFloat Float; /* 32 bit floating point */
|
||||
typedef CDouble Double; /* 32/64 bit floating point */
|
||||
typedef CBool Bool; /* Boolean (True/False) */
|
||||
typedef CChar Char; /* character, character array ptr */
|
||||
typedef char *String; /* Null terminated 8 bit char str */
|
||||
|
||||
typedef CVoid *pVoid; /* Void (typeless) */
|
||||
typedef Int *pInt; /* machine-natural integer */
|
||||
typedef UInt *pUInt; /* machine-natural unsigned integer */
|
||||
typedef Int8 *pInt8; /* 8 bit signed integer */
|
||||
typedef Int16 *pInt16; /* 16 bit signed integer */
|
||||
typedef Int32 *pInt32; /* 32 bit signed integer */
|
||||
typedef UInt8 *pUInt8; /* 8 bit unsigned integer */
|
||||
typedef UInt16 *pUInt16; /* 16 bit unsigned integer */
|
||||
typedef UInt32 *pUInt32; /* 32 bit unsigned integer */
|
||||
typedef Float *pFloat; /* 32 bit floating point */
|
||||
typedef Double *pDouble; /* 32/64 bit floating point */
|
||||
typedef Bool *pBool; /* Boolean (True/False) */
|
||||
typedef Char *pChar; /* character, character array ptr */
|
||||
typedef String *pString; /* Null terminated 8 bit char str */
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define Null 0
|
||||
#else
|
||||
#define Null ((Void *) 0)
|
||||
#endif
|
||||
|
||||
/* Legacy Types/Structures */
|
||||
typedef char *Address; /* Ready for address-arithmetic */
|
||||
typedef char const *ConstAddress;
|
||||
typedef unsigned char Byte; /* Raw byte */
|
||||
typedef float Float32; /* Single-precision float */
|
||||
typedef double Float64; /* Double-precision float */
|
||||
typedef void *Pointer; /* Pointer to anonymous object */
|
||||
typedef void const *ConstPointer;
|
||||
typedef char const *ConstString;
|
||||
|
||||
#endif
|
||||
|
||||
/*Assume that 64-bit integers are supported natively by C99 compilers and Visual
|
||||
C version 6.00 and higher. More discrimination in this area may be added
|
||||
here as necessary.*/
|
||||
#ifndef TMFL_DOT_NET_2_0_TYPES
|
||||
#if defined __STDC_VERSION__ && __STDC_VERSION__ > 199409L
|
||||
/*This can be enabled only when all explicit references to the hi and lo
|
||||
structure members are eliminated from client code.*/
|
||||
#define TMFL_NATIVE_INT64 1
|
||||
typedef signed long long int Int64, *pInt64; /* 64-bit integer */
|
||||
typedef unsigned long long int UInt64, *pUInt64; /* 64-bit bitmask */
|
||||
/* #elif defined _MSC_VER && _MSC_VER >= 1200 */
|
||||
/* This can be enabled only when all explicit references to the hi and lo
|
||||
structure members are eliminated from client code. */
|
||||
/* #define TMFL_NATIVE_INT64 1 */
|
||||
/* 64-bit integer */
|
||||
/* typedef signed __int64 Int64, *pInt64; */
|
||||
/* 64-bit bitmask */
|
||||
/* typedef unsigned __int64 UInt64, *pUInt64; */
|
||||
#else /*!(defined __STDC_VERSION__ && __STDC_VERSION__ > 199409L)*/
|
||||
#define TMFL_NATIVE_INT64 0
|
||||
typedef
|
||||
struct
|
||||
{
|
||||
/*Get the correct endianness (this has no impact on any other part of
|
||||
the system, but may make memory dumps easier to understand).*/
|
||||
#if TMFL_ENDIAN == TMFL_ENDIAN_BIG
|
||||
Int32 hi; UInt32 lo;
|
||||
#else
|
||||
UInt32 lo; Int32 hi;
|
||||
#endif
|
||||
}
|
||||
Int64, *pInt64; /* 64-bit integer */
|
||||
|
||||
typedef
|
||||
struct
|
||||
{
|
||||
#if TMFL_ENDIAN == TMFL_ENDIAN_BIG
|
||||
UInt32 hi; UInt32 lo;
|
||||
#else
|
||||
UInt32 lo; UInt32 hi;
|
||||
#endif
|
||||
}
|
||||
UInt64, *pUInt64; /* 64-bit bitmask */
|
||||
#endif /*defined __STDC_VERSION__ && __STDC_VERSION__ > 199409L*/
|
||||
#endif /*TMFL_DOT_NET_2_0_TYPES*/
|
||||
|
||||
|
||||
/* Maximum length of device name in all BSP and capability structures */
|
||||
#define HAL_DEVICE_NAME_LENGTH 16
|
||||
|
||||
|
||||
|
||||
/* timestamp definition */
|
||||
#ifndef TMFL_DOT_NET_2_0_TYPES
|
||||
typedef UInt64 tmTimeStamp_t, *ptmTimeStamp_t;
|
||||
#endif
|
||||
/* for backwards compatibility with the older tmTimeStamp_t definition */
|
||||
#define ticks lo
|
||||
#define hiTicks hi
|
||||
|
||||
|
||||
/*============================================================================*/
|
||||
/* Hardware device power states */
|
||||
/*============================================================================*/
|
||||
typedef enum tmPowerState
|
||||
{
|
||||
tmPowerOn = 0, /* Device powered on (D0 state) */
|
||||
tmPowerStandby, /* Device power standby (D1 state) */
|
||||
tmPowerSuspend, /* Device power suspended (D2 state) */
|
||||
tmPowerOff, /* Device powered off (D3 state) */
|
||||
tmPowerMax /* Device power max */
|
||||
} tmPowerState_t, *ptmPowerState_t;
|
||||
|
||||
/*============================================================================*/
|
||||
/* Software Version Structure */
|
||||
/*============================================================================*/
|
||||
|
||||
typedef struct tmSWVersion
|
||||
{
|
||||
UInt32 compatibilityNr; /* Interface compatibility number */
|
||||
UInt32 majorVersionNr; /* Interface major version number */
|
||||
UInt32 minorVersionNr; /* Interface minor version number */
|
||||
UInt32 buildVersionNr; /* Interface build version number */
|
||||
} tmSWVersion_t, *ptmSWVersion_t;
|
||||
|
||||
|
||||
/*============================================================================*/
|
||||
/* HW Unit Selection */
|
||||
/*============================================================================*/
|
||||
typedef CInt tmUnitSelect_t, *ptmUnitSelect_t;
|
||||
|
||||
#define tmUnitNone ((tmUnitSelect_t)(-1))
|
||||
#define tmUnit0 0
|
||||
#define tmUnit1 1
|
||||
#define tmUnit2 2
|
||||
#define tmUnit3 3
|
||||
#define tmUnit4 4
|
||||
#define tmUnit5 5
|
||||
|
||||
|
||||
/*============================================================================*/
|
||||
/* Instance handle */
|
||||
/*============================================================================*/
|
||||
typedef Int tmInstance_t, *ptmInstance_t;
|
||||
|
||||
#ifndef TMFL_DOT_NET_2_0_TYPES
|
||||
/* Callback function declaration */
|
||||
typedef Void (*ptmCallback_t) (UInt32 events, Void *pData, UInt32 userData);
|
||||
#define tmCallback_t ptmCallback_t /*compatibility*/
|
||||
#endif
|
||||
|
||||
|
||||
/*============================================================================*/
|
||||
/* INLINE keyword for inline functions in all environments */
|
||||
/*============================================================================*/
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define inline __inline
|
||||
#elif defined(__GNUC__)
|
||||
#define inline __inline__
|
||||
#elif TMFL_OS_IS_PSOS && TMFL_CPU_IS_MIPS
|
||||
|
||||
/* NOTE regarding the keyword INLINE:
|
||||
|
||||
Inline is not an ANSI-C keyword, hence every compiler can implement inlining
|
||||
the way it wants to. When using the dcc compiler this might possibly lead to
|
||||
redeclaration warnings when linking. For example:
|
||||
|
||||
dld: warning: Redeclaration of tmmlGetMemHandle
|
||||
dld: Defined in root.o
|
||||
dld: and tmmlApi.o(../../lib/pSOS-MIPS/libtmml.a)
|
||||
|
||||
For the dcc compiler inlining is not on by default. When building a retail
|
||||
version ( _TMTGTREL=ret), inlining is turned on explicitly in the dvp1 pSOS
|
||||
makefiles by specifying -XO, which enables all standard optimizations plus
|
||||
some others, including inlining (see the Language User's Manual, D-CC and
|
||||
D-C++ Compiler Suites p46). When building a debug version ( _TMTGTREL=dbg),
|
||||
the optimizations are not turned on (and even if they were they would have
|
||||
been overruled by -g anyway).
|
||||
|
||||
When a .h file with inline function declarations gets included in multiple
|
||||
source files, redeclaration warnings are issued.
|
||||
|
||||
When building a retail version those functions are inlined, but in addition
|
||||
the function is also declared within the .o file, resulting in redeclaration
|
||||
warnings as the same function is also defined by including that same header
|
||||
file in other source files. Defining the functions as static inline rather
|
||||
than inline solves the problem, as now the additional function declaration
|
||||
is omitted (as now the compiler realizes that there is no point in keeping
|
||||
that declaration as it can only be called from within this specific file,
|
||||
but it isn't, because all calls are already inline).
|
||||
|
||||
When building a debug version no inlining is done, but the functions are
|
||||
still defined within the .o file, again resulting in redeclaration warnings.
|
||||
Again, defining the functions to be static inline rather than inline solves
|
||||
the problem.
|
||||
|
||||
Now if we would change the definition of the inline keyword for pSOS from
|
||||
__inline__ to static __inline__, all inline function definitions throughout
|
||||
the code would not issue redeclaration warnings anymore, but all static
|
||||
inline definitions would.
|
||||
If we don't change the definition of the inline keyword, all inline func-
|
||||
tion definitions would return redeclaration warnings.
|
||||
|
||||
As this is a pSOS linker bug, it was decided not to change the code but
|
||||
rather to ignore the issued warnings.
|
||||
*/
|
||||
|
||||
#define inline __inline__
|
||||
|
||||
#elif TMFL_OS_IS_PSOS && TMFL_CPU_IS_TM
|
||||
/* TriMedia keyword is already inline */
|
||||
|
||||
#elif TMFL_OS_IS_ECOS && TMFL_CPU_IS_MIPS
|
||||
|
||||
#define inline __inline__
|
||||
|
||||
#elif (TMFL_OS_IS_HPUNIX || TMFL_OS_IS_NULLOS)
|
||||
/*
|
||||
TMFL_OS_IS_HPUNIX is the HP Unix workstation target OS environment for the
|
||||
DVP SDE2 using the GNU gcc toolset. It is the same as TMFL_OS_IS_NULLOS
|
||||
(which is inaccurately named because it is the HP Unix CPU/OS target
|
||||
environment).
|
||||
*/
|
||||
/* LM; 02/07/2202; to be able to use Insure, I modify the definition of inline */
|
||||
/* #define inline __inline__ */
|
||||
#define inline
|
||||
|
||||
#elif TMFL_OS_IS_ECOS && TMFL_CPU_IS_MIPS
|
||||
|
||||
#define inline
|
||||
|
||||
#else /* TMFL_OS_IS_??? */
|
||||
|
||||
#define inline
|
||||
|
||||
#endif /* TMFL_OS_IS_XXX */
|
||||
|
||||
|
||||
/*============================================================================*/
|
||||
/* Macros for deprecating */
|
||||
/*============================================================================*/
|
||||
/*
|
||||
#ifdef __GNUC__
|
||||
#define DEPRECATED(_LEGACYFUNC, _FUNC) _LEGACYFUNC __attribute__ ((deprecated("was declared deprecated. Use " ## #_FUNC ## " instead.")))
|
||||
#define DEPRECATED_MSG(_LEGACY, _NEW)
|
||||
#elif defined(_MSC_VER)
|
||||
#define DEPRECATED(_LEGACYFUNC, _FUNC) __declspec(deprecated("was declared deprecated. Use " ## #_FUNC ## " instead.")) _LEGACYFUNC
|
||||
#define DEPRECATED_MSG(_LEGACY, _NEW) __pragma(message(__FILE__ "(0) : warning C4996: " _LEGACY " was declared deprecated. Use " _NEW " instead." ))
|
||||
#else
|
||||
#pragma message("WARNING: You need to implement DEPRECATED for this compiler")
|
||||
#define DEPRECATED(_LEGACYFUNC, _FUNC) _LEGACYFUNC
|
||||
#endif
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ndef TM_NX_TYPES_H */
|
||||
|
||||
@@ -0,0 +1,111 @@
|
||||
/*
|
||||
Copyright (C) 2006-2010 NXP B.V., All Rights Reserved.
|
||||
This source code and any compilation or derivative thereof is the proprietary
|
||||
information of NXP B.V. and is confidential in nature. Under no circumstances
|
||||
is this software to be exposed to or placed under an Open Source License of
|
||||
any type without the expressed written permission of NXP B.V.
|
||||
*
|
||||
* \file tmUnitParams.h
|
||||
*
|
||||
* %version: CFR_FEAP#4 %
|
||||
*
|
||||
* \date %modify_time%
|
||||
*
|
||||
* \author Christophe CAZETTES
|
||||
*
|
||||
* \brief Describe briefly the purpose of this file.
|
||||
*
|
||||
* REFERENCE DOCUMENTS :
|
||||
*
|
||||
*
|
||||
* TVFE SW Arch V4 Template: Author Christophe CAZETTES
|
||||
*
|
||||
* \section info Change Information
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _TM_UNIT_PARAMS_H
|
||||
#define _TM_UNIT_PARAMS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*============================================================================*/
|
||||
/* Types and defines: */
|
||||
/*============================================================================*/
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/** \brief "These macros map to tmUnitSelect_t variables parts"
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#define UNIT_VALID(_tUnIt) (((_tUnIt)&0x80000000)==0)
|
||||
|
||||
#define UNIT_PATH_INDEX_MASK (0x0000001F)
|
||||
#define UNIT_PATH_INDEX_POS (0)
|
||||
|
||||
#define UNIT_PATH_TYPE_MASK (0x000003E0)
|
||||
#define UNIT_PATH_TYPE_POS (5)
|
||||
|
||||
#define UNIT_PATH_CONFIG_MASK (0x0003FC00)
|
||||
#define UNIT_PATH_CONFIG_POS (10)
|
||||
|
||||
#define UNIT_SYSTEM_INDEX_MASK (0x007C0000)
|
||||
#define UNIT_SYSTEM_INDEX_POS (18)
|
||||
|
||||
#define UNIT_SYSTEM_CONFIG_MASK (0x7F800000)
|
||||
#define UNIT_SYSTEM_CONFIG_POS (23)
|
||||
|
||||
|
||||
|
||||
|
||||
#define UNIT_PATH_INDEX_GET(_tUnIt) ((_tUnIt)&UNIT_PATH_INDEX_MASK)
|
||||
#define UNIT_PATH_INDEX_VAL(_val) (((_val)<<UNIT_PATH_INDEX_POS)&UNIT_PATH_INDEX_MASK)
|
||||
#define UNIT_PATH_INDEX_SET(_tUnIt, _val) ( ((_tUnIt)&~UNIT_PATH_INDEX_MASK) | UNIT_PATH_INDEX_VAL(_val) )
|
||||
#define UNIT_PATH_INDEX_VAL_GET(_val) (UNIT_PATH_INDEX_VAL(UNIT_PATH_INDEX_GET(_val)))
|
||||
|
||||
#define UNIT_PATH_TYPE_GET(_tUnIt) (((_tUnIt)&UNIT_PATH_TYPE_MASK) >> UNIT_PATH_TYPE_POS)
|
||||
#define UNIT_PATH_TYPE_VAL(_val) (((_val)<<UNIT_PATH_TYPE_POS)&UNIT_PATH_TYPE_MASK)
|
||||
#define UNIT_PATH_TYPE_SET(_tUnIt, _val) ( ((_tUnIt)&~UNIT_PATH_TYPE_MASK) | UNIT_PATH_TYPE_VAL(_val) )
|
||||
#define UNIT_PATH_TYPE_VAL_GET(_val) (UNIT_PATH_TYPE_VAL(UNIT_PATH_TYPE_GET(_val)))
|
||||
|
||||
|
||||
#define UNIT_PATH_CONFIG_GET(_tUnIt) (((_tUnIt)&UNIT_PATH_CONFIG_MASK) >> UNIT_PATH_CONFIG_POS)
|
||||
#define UNIT_PATH_CONFIG_VAL(_val) (((_val)<<UNIT_PATH_CONFIG_POS)&UNIT_PATH_CONFIG_MASK)
|
||||
#define UNIT_PATH_CONFIG_SET(_tUnIt, _val) ( ((_tUnIt)&~UNIT_PATH_CONFIG_MASK) | UNIT_PATH_CONFIG_VAL(_val) )
|
||||
#define UNIT_PATH_CONFIG_VAL_GET(_val) (UNIT_PATH_CONFIG_VAL(UNIT_PATH_CONFIG_GET(_val)))
|
||||
|
||||
#define UNIT_SYSTEM_INDEX_GET(_tUnIt) (((_tUnIt)&UNIT_SYSTEM_INDEX_MASK) >> UNIT_SYSTEM_INDEX_POS)
|
||||
#define UNIT_SYSTEM_INDEX_VAL(_val) (((_val)<<UNIT_SYSTEM_INDEX_POS)&UNIT_SYSTEM_INDEX_MASK)
|
||||
#define UNIT_SYSTEM_INDEX_SET(_tUnIt, _val) ( ((_tUnIt)&~UNIT_SYSTEM_INDEX_MASK) | UNIT_SYSTEM_INDEX_VAL(_val) )
|
||||
#define UNIT_SYSTEM_INDEX_VAL_GET(_val) (UNIT_SYSTEM_INDEX_VAL(UNIT_SYSTEM_INDEX_GET(_val)))
|
||||
|
||||
#define UNIT_SYSTEM_CONFIG_GET(_tUnIt) (((_tUnIt)&UNIT_SYSTEM_CONFIG_MASK) >> UNIT_SYSTEM_CONFIG_POS)
|
||||
#define UNIT_SYSTEM_CONFIG_VAL(_val) (((_val)<<UNIT_SYSTEM_CONFIG_POS)&UNIT_SYSTEM_CONFIG_MASK)
|
||||
#define UNIT_SYSTEM_CONFIG_SET(_tUnIt, _val) ( ((_tUnIt)&~UNIT_SYSTEM_CONFIG_MASK) | UNIT_SYSTEM_CONFIG_POS(_val) )
|
||||
#define UNIT_SYSTEM_CONFIG_VAL_GET(_val) (UNIT_SYSTEM_CONFIG_VAL(UNIT_SYSTEM_CONFIG_GET(_val)))
|
||||
|
||||
|
||||
#define GET_WHOLE_SYSTEM_TUNIT(_tUnIt) (UNIT_SYSTEM_CONFIG_VAL_GET(_tUnIt)|UNIT_SYSTEM_INDEX_VAL_GET(_tUnIt))
|
||||
|
||||
#define GET_SYSTEM_TUNIT(_tUnIt) (UNIT_SYSTEM_CONFIG_VAL_GET(_tUnIt)|UNIT_SYSTEM_INDEX_VAL_GET(_tUnIt)|UNIT_PATH_INDEX_VAL_GET(_tUnIt))
|
||||
|
||||
#define GET_INDEX_TUNIT(_tUnIt) (UNIT_SYSTEM_INDEX_VAL_GET(_tUnIt)|UNIT_PATH_INDEX_VAL_GET(_tUnIt))
|
||||
|
||||
#define GET_INDEX_TYPE_TUNIT(_tUnIt) (UNIT_SYSTEM_INDEX_VAL_GET(_tUnIt)|UNIT_PATH_INDEX_VAL_GET(_tUnIt)|UNIT_PATH_TYPE_VAL_GET(_tUnIt))
|
||||
|
||||
#define XFER_DISABLED_FLAG (UNIT_PATH_CONFIG_VAL(0x80))
|
||||
#define GET_XFER_DISABLED_FLAG_TUNIT(_tUnIt) (((_tUnIt)&XFER_DISABLED_FLAG)!=0)
|
||||
|
||||
|
||||
/*============================================================================*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TM_UNIT_PARAMS_H */
|
||||
|
||||
@@ -0,0 +1,350 @@
|
||||
/**
|
||||
Copyright (C) 2007 NXP B.V.), All Rights Reserved.
|
||||
This source code and any compilation or derivative thereof is the proprietary
|
||||
information of NXP B.V. and is confidential in nature. Under no circumstances
|
||||
is this software to be exposed to or placed under an Open Source License of
|
||||
any type without the expressed written permission of NXP B.V.
|
||||
*
|
||||
* \file tmbslFrontEndCfgItem.h
|
||||
* %version: CFR_STB#0.12 %
|
||||
*
|
||||
* \date %date_modified%
|
||||
*
|
||||
* \brief Describe briefly the purpose of this file.
|
||||
*
|
||||
* REFERENCE DOCUMENTS :
|
||||
*
|
||||
* Detailled description may be added here.
|
||||
*
|
||||
* \section info Change Information
|
||||
*
|
||||
* \verbatim
|
||||
Date Modified by CRPRNr TASKNr Maintenance description
|
||||
-------------|-----------|-------|-------|-----------------------------------
|
||||
<28-Jan-2005>
|
||||
\endverbatim
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
#ifndef TMBSLFRONTENDCFGITEM_H
|
||||
#define TMBSLFRONTENDCFGITEM_H
|
||||
*/
|
||||
/*============================================================================*/
|
||||
/* INCLUDE FILES */
|
||||
/*============================================================================*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/*============================================================================*/
|
||||
/* MACRO DEFINITION */
|
||||
/*============================================================================*/
|
||||
#if !defined(TMBSLFRONTEND_CFG_ITEM_MAKE)
|
||||
#define TMBSLFRONTEND_CFG_ITEM_MAKE(item) tmbslFrontEnd##item
|
||||
#endif
|
||||
|
||||
/*============================================================================*/
|
||||
/* ENUM OR TYPE DEFINITION */
|
||||
/*============================================================================*/
|
||||
|
||||
/******************************************************************************/
|
||||
/** \brief "This enum are used to choose a configuration item in set/get config bsl"
|
||||
*
|
||||
* \sa "bsl 'cfg' functions"
|
||||
*
|
||||
******************************************************************************/
|
||||
typedef enum {
|
||||
/** Board Id */
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Board) = 0,
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Standard),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(LPSel) = 6,
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Init) = 100,
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(I2cSwitch),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(CheckIdentity),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadSync),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadIQ),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadAgc),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadTVBER), /* = 106 - BSD*/
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadTCPTU),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadTMCC),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadCBER), /* = 109 - DVB-T*/
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadConfidence),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadRepImpul),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadRepFreq),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadCellId),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadDspVersion),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(CarrierHigh),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(CarrierLow),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(CarrierStep),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(CarrierCurrent),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(StartIQ),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(StopIQ),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(StartRepImpul),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(StopRepImpul),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadACI),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadCCI),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadLEE),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadCRC),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadMSE), /* = 127 - DVB-C*/
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadCOEF),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(StartEqual),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(StopEqual),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(DspCrcVersionOK), /* return true if OK */
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadRSSI) = 138, /*138*/
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(RFTone),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(RFToneIndex),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ToneSearchState),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(NbOfUnit) = 200,
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(OutOfGIEcho), /*DVB_T*/
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(DSPDownload),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(DSPloadFromHost),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(DSPloadFromEEPROM),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Enable4k),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ModePer),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(GiveConfigToTuner),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ConfigAttenuator),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(AGCBusEnable),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(AGCExt),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(AGCGainIndex),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(AGCGainValue),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(LOFreqIndex),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(LOFreqValue),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(XtalMode),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(EnableLNA),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(CutOffIndex),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(TunerBandwidth) = 300,
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(TunerLevel),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Band),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(RF),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ID),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(POR),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadFEL),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(FCC),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Temp),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(RFAGC),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(IFAGC),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(AGCandTemp),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(PowerState),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Sensibility),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadCarrier),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(BandAuto) = 330,
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ManualBandWidth),
|
||||
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(RFCALOK) = 355,
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(IRCALOK),
|
||||
|
||||
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(IFLevel) = 362,
|
||||
|
||||
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadInit) = 372,
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(StatusByte) = 380,
|
||||
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(StandardMode) = 400,
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Sound),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(DemodStatus),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadAFC),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadHlock),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadVlock),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadDIFAGC),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadTIFAGC),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(SetFI),
|
||||
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(DemodAdd) = 500,
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(DemodFct),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(MapNb), /* for 8275AHN), 8274AHN */
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(MapIndex),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(MapFreq),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(MapParam),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ATC), /* used by TD1316 */
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(TOP), /* used by TD1316 */
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadID),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Xtall),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(PLLMFactor),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(PLLNFactor),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(PLLPFactor),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(BERDepth),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(IQSwapped),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ExtOffset),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Offset125K),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(IF),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ProtocolStep),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Watchdog),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(NbRetry),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(PulseKiller),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Xtall100PPM),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(UseAGCTun),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(AGCPolaTun),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(AGCPolaIF),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(AGCTunMax),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(AGCTunMin),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(AGCIFMax),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(AGCIFMin),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Out1POClk),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Out1ParaSer),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Out1SLSB), /* MSBLSB), configure in serial mode if MSB or LSB first */
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Out1TSMode), /* Transport stream mode A), B), C... */
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Out1ParaDiv),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Out2POClk),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Out2ParaSer),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Out2SLSB),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Out2TSMODE),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Out2ParaDiv),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(SRMax), /* Sat SR config */
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(SRMin),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(SRMaxMargin),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(SRMinMargin),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(SearchRange),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(PolaAGC),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(DeltaThreshold),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ZIFTuner),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(FC), /* tmbsl8262 */
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(BBGain),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(RFATT),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(PDPLL),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(PDZIF),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(PDLoopT),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(PDRSSI),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(PDLNA),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(RefDivider),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(CalManual),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(CPCurSel),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(CPHigh),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Port1),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(FSampling),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(DVBMCNS), /* TDA10023 */
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(AGCThreshold),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(EqualType),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(PolaPWM1),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(PolaPWM2),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(BERWindow),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ClkOffsetRange),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(SWDyn),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(SWStep),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(SWLength),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(SWPos),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(JQAMMode),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(JQAMReQTS),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(JQAMReQON),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(JQAMGetReg5),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(JQAMGetTSStatus),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(JQAMGetRCVStatus),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(JQAMGetTSON),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(CPump), /* Cdm1316 */
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(PioInOut0),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(PioInOut1),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(PioValue1),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(PioInOut2),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(PioValue2),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(PioInOut3),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(PioValue3),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(SetAntennaPower) = 600, /* Control GPIO1 in open-drain for Vestel application */
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ZapMode) = 601,
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ChannelInfo),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(TimeErr),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(FreqErr),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(EnableI2cSwitch),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadFreqFilter),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadChannelType),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadCCIDetection),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadDopplerDetection),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadCumulatedHS),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadACIDetection),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadPKUse),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadIIRTimeInter),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadEchoType),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadChangeDetect),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadNBPath),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadChannelLength),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(EnableIQDetect),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(IFTuner) = 619,
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(IFDemod),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(DemodReadFct),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(AutoOffsetLock),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(PLLStep),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ManualBandwidth),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(IsMK3),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(DiversitySetMaster),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(DiversitySetBridge),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(DiversitySetSlave),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ICMode) = 631,
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Enable8295Equal) = 633,
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(CustomGDCoeff),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(CustomCVBSCoeff),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(CustomCVBSLevel),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(GDEqSect1),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(GDEqSect2),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(GDEqSect3),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(GDEqSect4),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(CVBSEqCoeff0),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(CVBSEqCoeff1),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(CVBSEqCoeff2),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(CVBSEqCoeff3),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(CVBSEqCoeff4),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(CVBSEqCoeff5),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(CVBSEqLevel),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(StandardCoeff),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(LNA1Gain),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(LNA2Gain),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(MixerGain),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(IFGain),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(SAClkOutputMode),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(BAND),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(SpectralInversion),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(CBERDepth),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(VBERReset),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(CBERReset),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(PioValue0),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Gpio0Cfg),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Gpio2Cfg),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Gpio0Select),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ITSel),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(DeltaSigma0Value),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(GpioPolarity),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(SetGPI0Analog),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(AgcTreshold),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(SendI2cStop),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ResetPK),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Spectrum),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(DspStop),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(WriteFwCode),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(WriteFwData),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(GiveCfgToTuner),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(EEPROMReadFct),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(EEPROMWriteFct),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(NbSample2Lock),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(CarrierSearching),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(CARCONF),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(Scanning),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(SYNCREG),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadCurrentFreq),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadCurrentBW),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadCurrentFFT),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadCurrentGI),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadCurrentSI),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadCurrentHPLP),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadCurrentHRCH),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadCurrentMOD),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadCurrentVRHP),
|
||||
TMBSLFRONTEND_CFG_ITEM_MAKE(ReadCurrentVRLP)
|
||||
} TMBSLFRONTEND_CFG_ITEM_MAKE(Config_t);
|
||||
|
||||
#define tmhalRFCALOK TMBSLFRONTEND_CFG_ITEM_MAKE(RFCALOK)
|
||||
#define tmhalIRCALOK TMBSLFRONTEND_CFG_ITEM_MAKE(IRCALOK)
|
||||
#define tmhalFELOCK TMBSLFRONTEND_CFG_ITEM_MAKE(ReadFEL)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
//#endif /* TMBSLFRONTENDCFGITEM_H */
|
||||
|
||||
/*============================================================================*/
|
||||
/* END OF FILE */
|
||||
/*============================================================================*/
|
||||
|
||||
@@ -0,0 +1,419 @@
|
||||
/*
|
||||
Copyright (C) 2006-2010 NXP B.V., All Rights Reserved.
|
||||
This source code and any compilation or derivative thereof is the proprietary
|
||||
information of NXP B.V. and is confidential in nature. Under no circumstances
|
||||
is this software to be exposed to or placed under an Open Source License of
|
||||
any type without the expressed written permission of NXP B.V.
|
||||
*
|
||||
* \file tmbslFrontEndTypes.h
|
||||
*
|
||||
* %version: CFR_FEAP#4 %
|
||||
*
|
||||
* \date %modify_time%
|
||||
*
|
||||
* \author Baptiste GUILLOT, Christophe CAZETTES
|
||||
*
|
||||
* \brief Describe briefly the purpose of this file.
|
||||
*
|
||||
* REFERENCE DOCUMENTS :
|
||||
*
|
||||
*
|
||||
* TVFE SW Arch V4 Template: Author Christophe CAZETTES
|
||||
*
|
||||
* \section info Change Information
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _FRONTEND_TYPES_H
|
||||
#define _FRONTEND_TYPES_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*============================================================================*/
|
||||
/* Types and defines: */
|
||||
/*============================================================================*/
|
||||
|
||||
/* Status of the carrier phase lock loop */
|
||||
typedef enum _tmbslFrontEndState_t
|
||||
{
|
||||
/** status Unknown */
|
||||
tmbslFrontEndStateUnknown = 0,
|
||||
/** Channel locked*/
|
||||
tmbslFrontEndStateLocked,
|
||||
/** Channel not locked */
|
||||
tmbslFrontEndStateNotLocked,
|
||||
/** Channel lock in process */
|
||||
tmbslFrontEndStateSearching,
|
||||
tmbslFrontEndStateMax
|
||||
} tmbslFrontEndState_t, *ptmbslFrontEndState_t;
|
||||
|
||||
|
||||
/* GPIO Config */
|
||||
typedef enum _tmbslFrontEndGpioConfig_t
|
||||
{
|
||||
tmbslFrontEndGpioConfUnknown = 0,
|
||||
tmbslFrontEndGpioConfInput,
|
||||
tmbslFrontEndGpioConfOutputPushPull,
|
||||
tmbslFrontEndGpioConfOutputOpenDrain,
|
||||
tmbslFrontEndGpioConfTriState,
|
||||
tmbslFrontEndGpioConfMax
|
||||
} tmbslFrontEndGpioConfig_t, *ptmbslFrontEndGpioConfig_t;
|
||||
|
||||
/* GPIO Polarity */
|
||||
typedef enum _tmbslFrontEndGpioPolarity_t
|
||||
{
|
||||
tmbslFrontEndGpioPolUnknown = 0,
|
||||
tmbslFrontEndGpioPolNotInverted,
|
||||
tmbslFrontEndGpioPolInverted,
|
||||
tmbslFrontEndGpioPolMax
|
||||
} tmbslFrontEndGpioPolarity_t, *ptmbslFrontEndGpioPolarity_t;
|
||||
|
||||
/* IT Selection */
|
||||
typedef enum _tmbslFrontEndITSel_t
|
||||
{
|
||||
tmbslFrontEndITSelUnknown = 0,
|
||||
tmbslFrontEndITSelFELGoesUp,
|
||||
tmbslFrontEndITSelFELGoesDown,
|
||||
tmbslFrontEndITSelDVBSynchroFlag,
|
||||
tmbslFrontEndITSelVBERRefreshed,
|
||||
tmbslFrontEndITSelBERRefreshed,
|
||||
tmbslFrontEndITSelUncor,
|
||||
tmbslFrontEndGpioITSelMax
|
||||
} tmbslFrontEndITSel_t, *ptmbslFrontEndITSel_t;
|
||||
|
||||
/* I2C switch */
|
||||
typedef enum _tmbslFrontEndI2CSwitchState_t
|
||||
{
|
||||
tmbslFrontEndI2CSwitchStateUnknown = 0,
|
||||
tmbslFrontEndI2CSwitchStateOpen,
|
||||
tmbslFrontEndI2CSwitchStateClosed,
|
||||
tmbslFrontEndI2CSwitchStateReset,
|
||||
tmbslFrontEndI2CSwitchStateMax
|
||||
} tmbslFrontEndI2CSwitchState_t, *ptmbslFrontEndI2CSwitchState_t;
|
||||
|
||||
/* DVBT2 PLP */
|
||||
typedef struct _tmbslFrontEndDVBT2PLP_t
|
||||
{
|
||||
UInt32 uId;
|
||||
UInt32 uGroupId;
|
||||
tmFrontEndDVBT2PLPType_t eType;
|
||||
tmFrontEndDVBT2PLPPayloadType_t ePayloadType;
|
||||
tmFrontEndCodeRate_t eCodeRate;
|
||||
tmFrontEndModulation_t eModulation;
|
||||
tmFrontEndRotationState eRotation;
|
||||
tmFrontEndDVBT2FECType_t eFECType;
|
||||
} tmbslFrontEndDVBT2PLP_t;
|
||||
|
||||
typedef enum _tmbslFrontEndTVStandard_t
|
||||
{
|
||||
tmbslFrontEndTVStandardNone,
|
||||
tmbslFrontEndTVStandardMN,
|
||||
tmbslFrontEndTVStandardBG,
|
||||
tmbslFrontEndTVStandardI,
|
||||
tmbslFrontEndTVStandardDKL,
|
||||
tmbslFrontEndTVStandardLp,
|
||||
tmbslFrontEndTVStandardMax
|
||||
} tmbslFrontEndTVStandard_t;
|
||||
|
||||
typedef enum _tmbslFrontEndStandardMode_t {
|
||||
tmbslFrontEndStandardModeUnknown = 0, /* Unknown standard */
|
||||
tmbslFrontEndStandardQAM6MHz, /* Digital TV QAM 6MHz */
|
||||
tmbslFrontEndStandardQAM8MHz, /* Digital TV QAM 8MHz */
|
||||
tmbslFrontEndStandardATSC6MHz, /* Digital TV ATSC 6MHz */
|
||||
tmbslFrontEndStandardISDBT6MHz, /* Digital TV ISDBT 6MHz */
|
||||
tmbslFrontEndStandardDVBT1_7MHz, /* Digital TV DVB-T/T2 6MHz */
|
||||
tmbslFrontEndStandardDVBT6MHz, /* Digital TV DVB-T/T2 6MHz */
|
||||
tmbslFrontEndStandardDVBT7MHz, /* Digital TV DVB-T/T2 7MHz */
|
||||
tmbslFrontEndStandardDVBT8MHz, /* Digital TV DVB-T/T2 8MHz */
|
||||
tmbslFrontEndStandardDVBT10MHz, /* Digital TV DVB-T/T2 10MHz */
|
||||
tmbslFrontEndStandardDMBT8MHz, /* Digital TV DMB-T 8MHz */
|
||||
tmbslFrontEndStandardFMRadio, /* Analog FM Radio */
|
||||
tmbslFrontEndStandardANLGMN, /* Analog TV M/N */
|
||||
tmbslFrontEndStandardANLGB, /* Analog TV B */
|
||||
tmbslFrontEndStandardANLGGH, /* Analog TV G/H */
|
||||
tmbslFrontEndStandardANLGI, /* Analog TV I */
|
||||
tmbslFrontEndStandardANLGDK, /* Analog TV D/K */
|
||||
tmbslFrontEndStandardANLGL, /* Analog TV L */
|
||||
tmbslFrontEndStandardANLGLL, /* Analog TV L' */
|
||||
tmbslFrontEndStandardScanning, /* Analog Preset Blind Scanning */
|
||||
tmbslFrontEndStandardScanXpress, /* ScanXpress */
|
||||
tmbslFrontEndStandardStandardMode_Max
|
||||
} tmbslFrontEndStandardMode_t, *ptmbslFrontEndStandardMode_t;
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/** \brief "Function pointers to hardware access services"
|
||||
*
|
||||
******************************************************************************/
|
||||
typedef struct _tmbslFrontEndIoFunc_t
|
||||
{
|
||||
#if USE_TUNER_88436
|
||||
uint32 (*Read)(int tUnit,uint32 AddrSize, uint8* pAddr,uint32 ReadLen, uint8* pData);
|
||||
|
||||
uint32 (*Write)(int tUnit,uint32 AddrSize, uint8* pAddr,uint32 WriteLen, uint8* pData);
|
||||
#else
|
||||
/** Read hardware function */
|
||||
tmErrorCode_t (*Read)(tmUnitSelect_t tUnit, UInt32 AddrSize, UInt8* pAddr, UInt32 ReadLen, UInt8* pData);
|
||||
/** Write hardware register, 8bit aligned function */
|
||||
tmErrorCode_t (*Write)(tmUnitSelect_t tUnit, UInt32 AddrSize, UInt8* pAddr, UInt32 WriteLen, UInt8* pData);
|
||||
#endif
|
||||
} tmbslFrontEndIoFunc_t, *ptmbslFrontEndIoFunc_t;
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/** \brief "Function pointers to Time services"
|
||||
*
|
||||
******************************************************************************/
|
||||
typedef struct _tmbslFrontEndTimeFunc_t
|
||||
{
|
||||
/** Return current time value in ms */
|
||||
tmErrorCode_t (*Get)(UInt32 *ptms);
|
||||
/** Wait t ms without blocking scheduler; warning this function
|
||||
don't schedule others frontend instance */
|
||||
tmErrorCode_t (*Wait)(tmUnitSelect_t tUnit, UInt32 tms);
|
||||
} tmbslFrontEndTimeFunc_t, *ptmbslFrontEndTimeFunc_t;
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/** \brief "Function pointers to Debug services "
|
||||
*
|
||||
******************************************************************************/
|
||||
typedef struct _tmbslFrontEndDebugFunc_t
|
||||
{
|
||||
/** Print a debug message */
|
||||
tmErrorCode_t (*Print)(UInt32 level, const char* format, ...);
|
||||
} tmbslFrontEndDebugFunc_t, *ptmbslFrontEndDebugFunc_t;
|
||||
|
||||
/* Mutex types */
|
||||
typedef void *ptmbslFrontEndMutexHandle;
|
||||
#define TMBSL_FRONTEND_MUTEX_TIMEOUT_INFINITE (0xFFFFFFFF)
|
||||
|
||||
/******************************************************************************/
|
||||
/** \brief "Function pointers to Mutex services "
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifdef _TVFE_SW_ARCH_V4
|
||||
|
||||
typedef struct _tmbslFrontEndMutexFunc_t
|
||||
{
|
||||
/* Open a mutex object */
|
||||
tmErrorCode_t (*Open)(ptmbslFrontEndMutexHandle *ppMutexHandle);
|
||||
/* Close a mutex object */
|
||||
tmErrorCode_t (*Close)(ptmbslFrontEndMutexHandle pMutexHandle);
|
||||
/* Acquire a mutex object */
|
||||
tmErrorCode_t (*Acquire)(ptmbslFrontEndMutexHandle pMutexHandle, UInt32 timeOut);
|
||||
/* Release a mutex object */
|
||||
tmErrorCode_t (*Release)(ptmbslFrontEndMutexHandle pMutexHandle);
|
||||
} tmbslFrontEndMutexFunc_t, *ptmbslFrontEndMutexFunc_t;
|
||||
|
||||
#else
|
||||
|
||||
/* Deprecated Mutex function pointer structure: */
|
||||
typedef struct _tmbslFrontEndMutexFunc_t
|
||||
{
|
||||
/* Open a mutex object */
|
||||
tmErrorCode_t (*Init)(ptmbslFrontEndMutexHandle *ppMutexHandle);
|
||||
/* Close a mutex object */
|
||||
tmErrorCode_t (*DeInit)(ptmbslFrontEndMutexHandle pMutexHandle);
|
||||
/* Acquire a mutex object */
|
||||
tmErrorCode_t (*Acquire)(ptmbslFrontEndMutexHandle pMutexHandle, UInt32 timeOut);
|
||||
/* Release a mutex object */
|
||||
tmErrorCode_t (*Release)(ptmbslFrontEndMutexHandle pMutexHandle);
|
||||
} tmbslFrontEndMutexFunc_t, *ptmbslFrontEndMutexFunc_t;
|
||||
|
||||
#endif
|
||||
|
||||
/******************************************************************************/
|
||||
/** \brief "This structure contain all the bsl driver external dependencies"
|
||||
*
|
||||
* \sa "all bsl 'init' functions"
|
||||
*
|
||||
******************************************************************************/
|
||||
typedef struct _tmbslFrontEndDependency_t
|
||||
{
|
||||
/** Hardware access to FrontEnd */
|
||||
tmbslFrontEndIoFunc_t sIo;
|
||||
/** Time services (wait, getTime, ...) */
|
||||
tmbslFrontEndTimeFunc_t sTime;
|
||||
/** Debug services (Print, Store, ...) */
|
||||
tmbslFrontEndDebugFunc_t sDebug;
|
||||
/** Mutex services */
|
||||
tmbslFrontEndMutexFunc_t sMutex;
|
||||
/** Device Parameters data size */
|
||||
UInt32 dwAdditionalDataSize;
|
||||
/** Device Parameters data pointer */
|
||||
void* pAdditionalData;
|
||||
} tmbslFrontEndDependency_t, *ptmbslFrontEndDependency_t;
|
||||
|
||||
/* Hardware access Functions macros */
|
||||
#define FUNC_SIO(_FUNC) _FUNC.sIo
|
||||
#define P_FUNC_SIO(_PFUNC) _PFUNC->sIo
|
||||
#define FUNC_SIO_READ(_FUNC) FUNC_SIO(_FUNC).Read
|
||||
#define P_FUNC_SIO_READ(_PFUNC) P_FUNC_SIO(_PFUNC).Read
|
||||
#define FUNC_SIO_WRITE(_FUNC) FUNC_SIO(_FUNC).Write
|
||||
#define P_FUNC_SIO_WRITE(_PFUNC) P_FUNC_SIO(_PFUNC).Write
|
||||
#define FUNC_SIO_READ_VALID(_FUNC) (FUNC_SIO_READ(_FUNC) != Null)
|
||||
#define P_FUNC_SIO_READ_VALID(_PFUNC) (P_FUNC_SIO_READ(_PFUNC) != Null)
|
||||
#define FUNC_SIO_WRITE_VALID(_FUNC) (FUNC_SIO_WRITE(_FUNC) != Null)
|
||||
#define P_FUNC_SIO_WRITE_VALID(_PFUNC) (P_FUNC_SIO_WRITE(_PFUNC) != Null)
|
||||
|
||||
/* Time Functions macros */
|
||||
#define FUNC_STIME(_FUNC) _FUNC.sTime
|
||||
#define P_FUNC_STIME(_PFUNC) _PFUNC->sTime
|
||||
#define FUNC_STIME_GET(_FUNC) FUNC_STIME(_FUNC).Get
|
||||
#define P_FUNC_STIME_GET(_PFUNC) P_FUNC_STIME(_PFUNC).Get
|
||||
#define FUNC_STIME_WAIT(_FUNC) FUNC_STIME(_FUNC).Wait
|
||||
#define P_FUNC_STIME_WAIT(_PFUNC) P_FUNC_STIME(_PFUNC).Wait
|
||||
#define FUNC_STIME_GET_VALID(_FUNC) (FUNC_STIME_GET(_FUNC) != Null)
|
||||
#define P_FUNC_STIME_GET_VALID(_PFUNC) (P_FUNC_STIME_GET(_PFUNC) != Null)
|
||||
#define FUNC_STIME_WAIT_VALID(_FUNC) (FUNC_STIME_WAIT(_FUNC) != Null)
|
||||
#define P_FUNC_STIME_WAIT_VALID(_PFUNC) (P_FUNC_STIME_WAIT(_PFUNC) != Null)
|
||||
|
||||
/* Debug Functions macros */
|
||||
#define FUNC_SDEBUG(_FUNC) _FUNC.sDebug
|
||||
#define P_FUNC_SDEBUG(_PFUNC) _PFUNC->sDebug
|
||||
#define FUNC_SDEBUG_PRINT(_FUNC) FUNC_SDEBUG(_FUNC).Print
|
||||
#define P_FUNC_SDEBUG_PRINT(_PFUNC) P_FUNC_SDEBUG(_PFUNC).Print
|
||||
#define FUNC_SDEBUG_PRINT_VALID(_FUNC) (FUNC_SDEBUG_PRINT(_FUNC) != Null)
|
||||
#define P_FUNC_SDEBUG_PRINT_VALID(_PFUNC) (P_FUNC_SDEBUG_PRINT(_PFUNC) != Null)
|
||||
|
||||
/* Mutex Functions macros */
|
||||
#define FUNC_SMUTEX(_FUNC) _FUNC.sMutex
|
||||
#define P_FUNC_SMUTEX(_PFUNC) _PFUNC->sMutex
|
||||
|
||||
#ifdef _TVFE_SW_ARCH_V4
|
||||
#define FUNC_SMUTEX_OPEN(_FUNC) FUNC_SMUTEX(_FUNC).Open
|
||||
#define P_FUNC_SMUTEX_OPEN(_PFUNC) P_FUNC_SMUTEX(_PFUNC).Open
|
||||
#define FUNC_SMUTEX_CLOSE(_FUNC) FUNC_SMUTEX(_FUNC).Close
|
||||
#define P_FUNC_SMUTEX_CLOSE(_PFUNC) P_FUNC_SMUTEX(_PFUNC).Close
|
||||
#else
|
||||
#define FUNC_SMUTEX_OPEN(_FUNC) FUNC_SMUTEX(_FUNC).Init
|
||||
#define P_FUNC_SMUTEX_OPEN(_PFUNC) P_FUNC_SMUTEX(_PFUNC).Init
|
||||
#define FUNC_SMUTEX_CLOSE(_FUNC) FUNC_SMUTEX(_FUNC).DeInit
|
||||
#define P_FUNC_SMUTEX_CLOSE(_PFUNC) P_FUNC_SMUTEX(_PFUNC).DeInit
|
||||
#endif
|
||||
|
||||
#define FUNC_SMUTEX_ACQUIRE(_FUNC) FUNC_SMUTEX(_FUNC).Acquire
|
||||
#define P_FUNC_SMUTEX_ACQUIRE(_PFUNC) P_FUNC_SMUTEX(_PFUNC).Acquire
|
||||
#define FUNC_SMUTEX_RELEASE(_FUNC) FUNC_SMUTEX(_FUNC).Release
|
||||
#define P_FUNC_SMUTEX_RELEASE(_PFUNC) P_FUNC_SMUTEX(_PFUNC).Release
|
||||
#define FUNC_SMUTEX_OPEN_VALID(_FUNC) (FUNC_SMUTEX_OPEN(_FUNC) != Null)
|
||||
#define P_FUNC_SMUTEX_OPEN_VALID(_PFUNC) (P_FUNC_SMUTEX_OPEN(_PFUNC) != Null)
|
||||
#define FUNC_SMUTEX_CLOSE_VALID(_FUNC) (FUNC_SMUTEX_CLOSE(_FUNC) != Null)
|
||||
#define P_FUNC_SMUTEX_CLOSE_VALID(_PFUNC) (P_FUNC_SMUTEX_CLOSE(_PFUNC) != Null)
|
||||
#define FUNC_SMUTEX_ACQUIRE_VALID(_FUNC) (FUNC_SMUTEX_ACQUIRE(_FUNC) != Null)
|
||||
#define P_FUNC_SMUTEX_ACQUIRE_VALID(_PFUNC) (P_FUNC_SMUTEX_ACQUIRE(_PFUNC) != Null)
|
||||
#define FUNC_SMUTEX_RELEASE_VALID(_FUNC) (FUNC_SMUTEX_RELEASE(_FUNC) != Null)
|
||||
#define P_FUNC_SMUTEX_RELEASE_VALID(_PFUNC) (P_FUNC_SMUTEX_RELEASE(_PFUNC) != Null)
|
||||
|
||||
/*============================================================================*/
|
||||
|
||||
typedef struct tmSWSettingsVersion
|
||||
{
|
||||
UInt32 customerNr; /* SW Settings customer number */
|
||||
UInt32 projectNr; /* SW Settings project number */
|
||||
UInt32 majorVersionNr; /* SW Settings major version number */
|
||||
UInt32 minorVersionNr; /* SW Settings minor version number */
|
||||
|
||||
} tmSWSettingsVersion_t, *ptmSWSettingsVersion_t;
|
||||
|
||||
/******************************************************************************/
|
||||
/** \brief "These macros map to trace functions "
|
||||
* P_DBGPRINTEx macro should be defined in each component
|
||||
******************************************************************************/
|
||||
|
||||
#define DEBUGLVL_DISABLED (0)
|
||||
#define DEBUGLVL_ERROR (DEBUGLVL_DISABLED+1)
|
||||
#define DEBUGLVL_TERSE (DEBUGLVL_ERROR+1)
|
||||
#define DEBUGLVL_VERBOSE (DEBUGLVL_TERSE+1)
|
||||
#define DEBUGLVL_BLAB (DEBUGLVL_VERBOSE+1)
|
||||
#define DEBUGLVL_INOUT (DEBUGLVL_BLAB+1)
|
||||
#define DEBUGLVL_MAX (DEBUGLVL_INOUT+1)
|
||||
|
||||
|
||||
#if defined(_TVFE_DEBUG_TRACE) || defined(TMBSLFRONTEND_DEBUG_TRACE)
|
||||
|
||||
#define tmDBGPRINTEx(_level, _format, ...) \
|
||||
{ \
|
||||
if(P_DBGPRINTVALID) \
|
||||
{ \
|
||||
P_DBGPRINTEx(_level, _format, ##__VA_ARGS__); \
|
||||
if(_level == DEBUGLVL_ERROR) \
|
||||
{ \
|
||||
P_DBGPRINTEx(_level, "==> Error in %s, Line %d\n", __FUNCTION__, __LINE__ ); \
|
||||
} \
|
||||
} \
|
||||
}
|
||||
|
||||
#define tmDBGPRINTErrEx(_errorCode, _level, _format, ...) \
|
||||
{ \
|
||||
if(P_DBGPRINTVALID) \
|
||||
{ \
|
||||
P_DBGPRINTEx(_level, _format, ##__VA_ARGS__); \
|
||||
if(_level == DEBUGLVL_ERROR) \
|
||||
{ \
|
||||
P_DBGPRINTEx(_level, "=> Error 0x%08X in %s (%d)\n", _errorCode, __FUNCTION__, __LINE__ ); \
|
||||
} \
|
||||
} \
|
||||
}
|
||||
|
||||
#define tmDBGPRINTErrAssertEx(_level, _format, ...) \
|
||||
{ \
|
||||
if(P_DBGPRINTVALID) \
|
||||
{ \
|
||||
P_DBGPRINTEx(_level, _format, ##__VA_ARGS__); \
|
||||
if(_level == DEBUGLVL_ERROR) \
|
||||
{ \
|
||||
P_DBGPRINTEx(_level, "=> Error 0x%08X in %s (%d)\n", _tmASSERTExErrorCode, __FUNCTION__, __LINE__ ); \
|
||||
} \
|
||||
} \
|
||||
}
|
||||
|
||||
#define tmASSERTExTR(_retVar, _expr, _strings) \
|
||||
{ \
|
||||
if((_retVar) != (_expr)) \
|
||||
{ \
|
||||
tmErrorCode_t _tmASSERTExErrorCode = _retVar; \
|
||||
tmDBGPRINTErrAssertEx _strings ; \
|
||||
return _retVar; \
|
||||
} \
|
||||
}
|
||||
|
||||
#define tmASSERTExT(_retVar, _expr, _strings) \
|
||||
{ \
|
||||
if((_retVar) != (_expr)) \
|
||||
{ \
|
||||
tmErrorCode_t _tmASSERTExErrorCode = _retVar; \
|
||||
tmDBGPRINTErrAssertEx _strings ; \
|
||||
} \
|
||||
}
|
||||
|
||||
#else
|
||||
#define tmDBGPRINTEx(_level, _format, ...)
|
||||
|
||||
#define tmDBGPRINTErrEx(_errorCode, _level, _format, ...)
|
||||
|
||||
#define tmDBGPRINTErrAssertEx(_level, _format, ...)
|
||||
|
||||
#define tmASSERTExTR(_retVar, _expr, _strings) \
|
||||
{ \
|
||||
if((_retVar) != (_expr)) \
|
||||
{ \
|
||||
return _retVar; \
|
||||
} \
|
||||
}
|
||||
|
||||
#define tmASSERTExT(_retVar, _expr, _strings)
|
||||
|
||||
#endif
|
||||
|
||||
/*============================================================================*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _FRONTEND_TYPES_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,504 @@
|
||||
/*
|
||||
Copyright (C) 2010 NXP B.V., All Rights Reserved.
|
||||
This source code and any compilation or derivative thereof is the proprietary
|
||||
information of NXP B.V. and is confidential in nature. Under no circumstances
|
||||
is this software to be exposed to or placed under an Open Source License of
|
||||
any type without the expressed written permission of NXP B.V.
|
||||
*
|
||||
* \file tmbslTDA18273.h
|
||||
*
|
||||
* %version: CFR_FEAP#21 %
|
||||
*
|
||||
* \date %modify_time%
|
||||
*
|
||||
* \author David LEGENDRE
|
||||
* Michael VANNIER
|
||||
* Christophe CAZETTES
|
||||
*
|
||||
* \brief Describe briefly the purpose of this file.
|
||||
*
|
||||
* REFERENCE DOCUMENTS :
|
||||
* TDA18273_Driver_User_Guide.pdf
|
||||
*
|
||||
* TVFE SW Arch V4 Template: Author Christophe CAZETTES
|
||||
*
|
||||
* \section info Change Information
|
||||
*
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
#ifndef _TMBSL_TDA18273_H
|
||||
#define _TMBSL_TDA18273_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*============================================================================*/
|
||||
/* TDA18273 Error Codes */
|
||||
/*============================================================================*/
|
||||
|
||||
#define TDA18273_ERR_BASE (CID_COMP_TUNER | CID_LAYER_BSL)
|
||||
#define TDA18273_ERR_COMP (CID_COMP_TUNER | CID_LAYER_BSL | TM_ERR_COMP_UNIQUE_START)
|
||||
|
||||
#define TDA18273_ERR_BAD_UNIT_NUMBER (TDA18273_ERR_BASE + TM_ERR_BAD_UNIT_NUMBER)
|
||||
#define TDA18273_ERR_ERR_NO_INSTANCES (TDA18273_ERR_BASE + TM_ERR_NO_INSTANCES)
|
||||
#define TDA18273_ERR_NOT_INITIALIZED (TDA18273_ERR_BASE + TM_ERR_NOT_INITIALIZED)
|
||||
#define TDA18273_ERR_ALREADY_SETUP (TDA18273_ERR_BASE + TM_ERR_ALREADY_SETUP)
|
||||
#define TDA18273_ERR_INIT_FAILED (TDA18273_ERR_BASE + TM_ERR_INIT_FAILED)
|
||||
#define TDA18273_ERR_BAD_PARAMETER (TDA18273_ERR_BASE + TM_ERR_BAD_PARAMETER)
|
||||
#define TDA18273_ERR_NOT_SUPPORTED (TDA18273_ERR_BASE + TM_ERR_NOT_SUPPORTED)
|
||||
#define TDA18273_ERR_NULL_CONTROLFUNC (TDA18273_ERR_BASE + TM_ERR_NULL_CONTROLFUNC)
|
||||
#define TDA18273_ERR_HW_FAILED (TDA18273_ERR_COMP + 0x0001)
|
||||
#define TDA18273_ERR_NOT_READY (TDA18273_ERR_COMP + 0x0002)
|
||||
#define TDA18273_ERR_BAD_VERSION (TDA18273_ERR_COMP + 0x0003)
|
||||
#define TDA18273_ERR_STD_NOT_SET (TDA18273_ERR_COMP + 0x0004)
|
||||
#define TDA18273_ERR_RF_NOT_SET (TDA18273_ERR_COMP + 0x0005)
|
||||
|
||||
/*============================================================================*/
|
||||
/* Types and defines: */
|
||||
/*============================================================================*/
|
||||
|
||||
typedef enum _TDA18273PowerState_t {
|
||||
TDA18273_PowerNormalMode = 0, /* Device normal mode */
|
||||
TDA18273_PowerStandbyWithXtalOn, /* Device standby mode with Xtal Output */
|
||||
TDA18273_PowerStandby, /* Device standby mode */
|
||||
TDA18273_PowerMax
|
||||
} TDA18273PowerState_t, *pTDA18273PowerState_t;
|
||||
|
||||
typedef enum _TDA18273StandardMode_t {
|
||||
TDA18273_StandardMode_Unknown = 0, /* Unknown standard */
|
||||
TDA18273_QAM_6MHz, /* Digital TV QAM 6MHz */
|
||||
TDA18273_QAM_8MHz, /* Digital TV QAM 8MHz */
|
||||
TDA18273_ATSC_6MHz, /* Digital TV ATSC 6MHz */
|
||||
TDA18273_ISDBT_6MHz, /* Digital TV ISDBT 6MHz */
|
||||
TDA18273_DVBT_1_7MHz, /* Digital TV DVB-T/T2 6MHz */
|
||||
TDA18273_DVBT_6MHz, /* Digital TV DVB-T/T2 6MHz */
|
||||
TDA18273_DVBT_7MHz, /* Digital TV DVB-T/T2 7MHz */
|
||||
TDA18273_DVBT_8MHz, /* Digital TV DVB-T/T2 8MHz */
|
||||
TDA18273_DVBT_10MHz, /* Digital TV DVB-T/T2 10MHz */
|
||||
TDA18273_DMBT_8MHz, /* Digital TV DMB-T 8MHz */
|
||||
TDA18273_FM_Radio, /* Analog FM Radio */
|
||||
TDA18273_ANLG_MN, /* Analog TV M/N */
|
||||
TDA18273_ANLG_B, /* Analog TV B */
|
||||
TDA18273_ANLG_GH, /* Analog TV G/H */
|
||||
TDA18273_ANLG_I, /* Analog TV I */
|
||||
TDA18273_ANLG_DK, /* Analog TV D/K */
|
||||
TDA18273_ANLG_L, /* Analog TV L */
|
||||
TDA18273_ANLG_LL, /* Analog TV L' */
|
||||
TDA18273_Scanning, /* Analog Preset Blind Scanning */
|
||||
TDA18273_ScanXpress, /* ScanXpress */
|
||||
TDA18273_StandardMode_Max
|
||||
} TDA18273StandardMode_t, *pTDA18273StandardMode_t;
|
||||
|
||||
#define isTDA18273_DGTL_STD(_CURSTD) ( (((_CURSTD)>=TDA18273_QAM_6MHz) && ((_CURSTD)<=TDA18273_DMBT_8MHz)) || ((_CURSTD)==TDA18273_ScanXpress) )
|
||||
#define isTDA18273_ANLG_STD(_CURSTD) ( ((_CURSTD)>=TDA18273_FM_Radio) && ((_CURSTD)<=TDA18273_Scanning) )
|
||||
|
||||
/* TDA18273 specific IRQ clear: */
|
||||
typedef enum _TDA18273IRQ_t {
|
||||
TDA18273_IRQ_MSM_RCCal = 0x01, /* MSM_RCCal bit */
|
||||
TDA18273_IRQ_MSM_IRCAL = 0x02, /* MSM_IRCAL bit */
|
||||
TDA18273_IRQ_MSM_RFCal = 0x04, /* MSM_RFCal bit */
|
||||
TDA18273_IRQ_MSM_LOCalc = 0x08, /* MSM_LOCalc bit */
|
||||
TDA18273_IRQ_MSM_RSSI = 0x10, /* MSM_RSSI bit */
|
||||
TDA18273_IRQ_XtalCal = 0x20, /* XtalCal bit */
|
||||
TDA18273_IRQ_Global = 0x80, /* IRQ_status bit */
|
||||
TDA18273_IRQ_HwInit = TDA18273_IRQ_MSM_RCCal\
|
||||
|TDA18273_IRQ_MSM_RFCal\
|
||||
|TDA18273_IRQ_MSM_LOCalc\
|
||||
|TDA18273_IRQ_MSM_RSSI,
|
||||
TDA18273_IRQ_IrCal = TDA18273_IRQ_MSM_IRCAL\
|
||||
|TDA18273_IRQ_MSM_LOCalc\
|
||||
|TDA18273_IRQ_MSM_RSSI,
|
||||
TDA18273_IRQ_SetRF = TDA18273_IRQ_MSM_RFCal\
|
||||
|TDA18273_IRQ_MSM_LOCalc,
|
||||
TDA18273_IRQ_GetPowerLevel = TDA18273_IRQ_MSM_RSSI
|
||||
} TDA18273IRQ_t, *pTDA18273IRQ_t;
|
||||
|
||||
/* Register Bit-Field Definition */
|
||||
typedef struct _TDA18273_BitField_t
|
||||
{
|
||||
UInt8 Address;
|
||||
UInt8 PositionInBits;
|
||||
UInt8 WidthInBits;
|
||||
UInt8 Attributes;
|
||||
}
|
||||
TDA18273_BitField_t, *pTDA18273_BitField_t;
|
||||
|
||||
/* Bus Access */
|
||||
typedef enum _eBusAccess_t
|
||||
{
|
||||
/* RW Bus access */
|
||||
Bus_RW = 0x00,
|
||||
/* No Read Bus access */
|
||||
Bus_NoRead = 0x01,
|
||||
/* No Write Bus access */
|
||||
Bus_NoWrite = 0x02,
|
||||
/* No Bus access. Update RegMap only */
|
||||
Bus_None = Bus_NoRead|Bus_NoWrite,
|
||||
Bus_Max
|
||||
} eBusAccess_t;
|
||||
|
||||
/*============================================================================*/
|
||||
/* Exported functions: */
|
||||
/*============================================================================*/
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_Open(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
tmbslFrontEndDependency_t* psSrvFunc /* I: setup parameters */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_Close(
|
||||
tmUnitSelect_t tUnit /* I: Unit number */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_GetSWVersion(
|
||||
ptmSWVersion_t pSWVersion /* I: Receives SW Version */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_GetSWSettingsVersion(
|
||||
ptmSWSettingsVersion_t pSWSettingsVersion /* O: Receives SW Settings Version */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_CheckHWVersion(
|
||||
tmUnitSelect_t tUnit /* I: Unit number */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_SetPowerState(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
tmPowerState_t powerState /* I: Power state */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_GetPowerState(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
tmPowerState_t* pPowerState /* O: Power state */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_SetLLPowerState(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
TDA18273PowerState_t powerState /* I: Power state of TDA18273 */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_GetLLPowerState(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
TDA18273PowerState_t* pPowerState /* O: Power state of TDA18273 */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_SetStandardMode(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
TDA18273StandardMode_t StandardMode /* I: Standard mode of this device */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_GetStandardMode(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
TDA18273StandardMode_t *pStandardMode /* O: Standard mode of this device */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_SetRF(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
UInt32 uRF /* I: RF frequency in hertz */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_GetRF(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
UInt32* pRF /* O: RF frequency in hertz */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_HwInit(
|
||||
tmUnitSelect_t tUnit /* I: Unit number */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_GetIF(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
UInt32* puIF /* O: IF Frequency in hertz */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_SetIF(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
UInt32 uIF /* I: IF Frequency in hertz */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_GetCF_Offset(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
UInt32* puOffset /* O: Center frequency offset in hertz */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_GetLockStatus(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
tmbslFrontEndState_t* pLockStatus /* O: PLL Lock status */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_GetPowerLevel(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
UInt8* pPowerLevel /* O: Power Level in 1/2 steps dBµV */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_SetInternalVsync(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
Bool bEnabled /* I: Enable of disable the internal VSYNC */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_GetInternalVsync(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
Bool* pbEnabled /* O: current status of the internal VSYNC */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_SetIRQWait(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
Bool bWait /* I: Determine if we need to wait IRQ in driver functions */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_GetIRQWait(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
Bool* pbWait /* O: Determine if we need to wait IRQ in driver functions */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_SetPllManual(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
Bool bOverridePLL /* I: Determine if we need to put PLL in manual mode in SetRF */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_GetPllManual(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
Bool* pbOverridePLL /* O: Determine if we need to put PLL in manual mode in SetRF */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_SetIRQWaitHwInit(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
Bool bWait /* I: Determine if we need to wait IRQ in driver functions */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_GetIRQWaitHwInit(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
Bool* pbWait /* O: Determine if we need to wait IRQ in driver functions */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_GetIRQ(
|
||||
tmUnitSelect_t tUnit /* I: Unit number */,
|
||||
Bool* pbIRQ /* O: IRQ triggered */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_WaitIRQ(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
UInt32 timeOut, /* I: timeOut for IRQ wait */
|
||||
UInt32 waitStep, /* I: wait step */
|
||||
UInt8 irqStatus /* I: IRQs to wait */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_GetXtalCal_End(
|
||||
tmUnitSelect_t tUnit /* I: Unit number */,
|
||||
Bool* pbXtalCal_End /* O: XtalCal_End triggered */
|
||||
);
|
||||
|
||||
/* You can only add one step (-1 or +1) at a time along -125 KHz <-> -62.5 KHz <-> 0 <-> 62.5 KHz <-> 125 KHz */
|
||||
/* After calling tmbslTDA18273_SetRF, step is reset at 0 */
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_SetFineRF(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
Int8 step /* I: step (-1, +1) */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_Write(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
const TDA18273_BitField_t* pBitField, /* I: Bitfield structure */
|
||||
UInt8 uData, /* I: Data to write */
|
||||
eBusAccess_t eBusAccess /* I: Access to bus */
|
||||
);
|
||||
|
||||
tmErrorCode_t
|
||||
tmbslTDA18273_Read(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
const TDA18273_BitField_t* pBitField, /* I: Bitfield structure */
|
||||
UInt8* puData, /* I: Data to read */
|
||||
eBusAccess_t eBusAccess /* I: Access to bus */
|
||||
);
|
||||
|
||||
/*============================================================================*/
|
||||
/* Legacy compatibility: */
|
||||
/*============================================================================*/
|
||||
|
||||
#ifndef tmbslTDA18273Init
|
||||
#define tmbslTDA18273Init tmbslTDA18273_Open
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273DeInit
|
||||
#define tmbslTDA18273DeInit tmbslTDA18273_Close
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273GetSWVersion
|
||||
#define tmbslTDA18273GetSWVersion tmbslTDA18273_GetSWVersion
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273GetSWSettingsVersion
|
||||
#define tmbslTDA18273GetSWSettingsVersion tmbslTDA18273_GetSWSettingsVersion
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273CheckHWVersion
|
||||
#define tmbslTDA18273CheckHWVersion tmbslTDA18273_CheckHWVersion
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273SetPowerState
|
||||
#define tmbslTDA18273SetPowerState tmbslTDA18273_SetLLPowerState
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273GetPowerState
|
||||
#define tmbslTDA18273GetPowerState tmbslTDA18273_GetLLPowerState
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273SetLLPowerState
|
||||
#define tmbslTDA18273SetLLPowerState tmbslTDA18273_SetLLPowerState
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273GetLLPowerState
|
||||
#define tmbslTDA18273GetLLPowerState tmbslTDA18273_GetLLPowerState
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273SetStandardMode
|
||||
#define tmbslTDA18273SetStandardMode tmbslTDA18273_SetStandardMode
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273GetStandardMode
|
||||
#define tmbslTDA18273GetStandardMode tmbslTDA18273_GetStandardMode
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273SetRf
|
||||
#define tmbslTDA18273SetRf tmbslTDA18273_SetRF
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273GetRf
|
||||
#define tmbslTDA18273GetRf tmbslTDA18273_GetRF
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273Reset
|
||||
#define tmbslTDA18273Reset tmbslTDA18273_HwInit
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273GetIF
|
||||
#define tmbslTDA18273GetIF tmbslTDA18273_GetIF
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273GetCF_Offset
|
||||
#define tmbslTDA18273GetCF_Offset tmbslTDA18273_GetCF_Offset
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273GetLockStatus
|
||||
#define tmbslTDA18273GetLockStatus tmbslTDA18273_GetLockStatus
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273GetPowerLevel
|
||||
#define tmbslTDA18273GetPowerLevel tmbslTDA18273_GetPowerLevel
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273GetRSSI
|
||||
#define tmbslTDA18273GetRSSI tmbslTDA18273_GetRSSI
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273SetIRQWait
|
||||
#define tmbslTDA18273SetIRQWait tmbslTDA18273_SetIRQWait
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273GetIRQWait
|
||||
#define tmbslTDA18273GetIRQWait tmbslTDA18273_GetIRQWait
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273SetIRQWaitHwInit
|
||||
#define tmbslTDA18273SetIRQWaitHwInit tmbslTDA18273_SetIRQWaitHwInit
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273GetIRQWaitHwInit
|
||||
#define tmbslTDA18273GetIRQWaitHwInit tmbslTDA18273_GetIRQWaitHwInit
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273GetIRQ
|
||||
#define tmbslTDA18273GetIRQ tmbslTDA18273_GetIRQ
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273WaitIRQ
|
||||
#define tmbslTDA18273WaitIRQ tmbslTDA18273_WaitIRQ
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273GetXtalCal_End
|
||||
#define tmbslTDA18273GetXtalCal_End tmbslTDA18273_GetXtalCal_End
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273RFFineTuning
|
||||
#define tmbslTDA18273RFFineTuning tmbslTDA18273_SetFineRF
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273Write
|
||||
#define tmbslTDA18273Write tmbslTDA18273_Write
|
||||
#endif
|
||||
|
||||
#ifndef tmbslTDA18273Read
|
||||
#define tmbslTDA18273Read tmbslTDA18273_Read
|
||||
#endif
|
||||
|
||||
#define tmTDA18273PowerState_t TDA18273PowerState_t
|
||||
#define tmTDA18273_PowerNormalMode TDA18273_PowerNormalMode
|
||||
#define tmTDA18273_PowerStandbyWithXtalOn TDA18273_PowerStandbyWithXtalOn
|
||||
#define tmTDA18273_PowerStandby TDA18273_PowerStandby
|
||||
#define tmTDA18273_PowerMax TDA18273_PowerMax
|
||||
|
||||
#define tmTDA18273StandardMode_t TDA18273StandardMode_t
|
||||
#define tmTDA18273_QAM_6MHz TDA18273_QAM_6MHz
|
||||
#define tmTDA18273_QAM_8MHz TDA18273_QAM_8MHz
|
||||
#define tmTDA18273_ATSC_6MHz TDA18273_ATSC_6MHz
|
||||
#define tmTDA18273_ISDBT_6MHz TDA18273_ISDBT_6MHz
|
||||
#define tmTDA18273_DVBT_1_7MHz TDA18273_DVBT_1_7MHz
|
||||
#define tmTDA18273_DVBT_6MHz TDA18273_DVBT_6MHz
|
||||
#define tmTDA18273_DVBT_7MHz TDA18273_DVBT_7MHz
|
||||
#define tmTDA18273_DVBT_8MHz TDA18273_DVBT_8MHz
|
||||
#define tmTDA18273_DVBT_10MHz TDA18273_DVBT_10MHz
|
||||
#define tmTDA18273_DMBT_8MHz TDA18273_DMBT_8MHz
|
||||
#define tmTDA18273_FM_Radio TDA18273_FM_Radio
|
||||
#define tmTDA18273_ANLG_MN TDA18273_ANLG_MN
|
||||
#define tmTDA18273_ANLG_B TDA18273_ANLG_B
|
||||
#define tmTDA18273_ANLG_GH TDA18273_ANLG_GH
|
||||
#define tmTDA18273_ANLG_I TDA18273_ANLG_I
|
||||
#define tmTDA18273_ANLG_DK TDA18273_ANLG_DK
|
||||
#define tmTDA18273_ANLG_L TDA18273_ANLG_L
|
||||
#define tmTDA18273_ANLG_LL TDA18273_ANLG_LL
|
||||
#define tmTDA18273_Scanning TDA18273_Scanning
|
||||
#define tmTDA18273_ScanXpress TDA18273_ScanXpress
|
||||
#define tmTDA18273_StandardMode_Max TDA18273_StandardMode_Max
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TMBSL_TDA18273_H */
|
||||
|
||||
Binary file not shown.
@@ -0,0 +1,242 @@
|
||||
/*
|
||||
Copyright (C) 2010 NXP B.V., All Rights Reserved.
|
||||
This source code and any compilation or derivative thereof is the proprietary
|
||||
information of NXP B.V. and is confidential in nature. Under no circumstances
|
||||
is this software to be exposed to or placed under an Open Source License of
|
||||
any type without the expressed written permission of NXP B.V.
|
||||
*
|
||||
* \file tmbslTDA18273_Instance.c
|
||||
*
|
||||
* %version: 3 %
|
||||
*
|
||||
* \date %modify_time%
|
||||
*
|
||||
* \author David LEGENDRE
|
||||
* Michael VANNIER
|
||||
* Christophe CAZETTES
|
||||
*
|
||||
* \brief Describe briefly the purpose of this file.
|
||||
*
|
||||
* REFERENCE DOCUMENTS :
|
||||
* TDA18273_Driver_User_Guide.pdf
|
||||
*
|
||||
* TVFE SW Arch V4 Template: Author Christophe CAZETTES
|
||||
*
|
||||
* \section info Change Information
|
||||
*
|
||||
*/
|
||||
#include "../inc/config.h"
|
||||
|
||||
#if USE_TUNER
|
||||
/*============================================================================*/
|
||||
/* Standard include files: */
|
||||
/*============================================================================*/
|
||||
#include "tmNxTypes.h"
|
||||
#include "tmNxCompId.h"
|
||||
#include "tmFrontEnd.h"
|
||||
#include "tmbslFrontEndTypes.h"
|
||||
#include "tmUnitParams.h"
|
||||
|
||||
/*============================================================================*/
|
||||
/* Project include files: */
|
||||
/*============================================================================*/
|
||||
#include "tmbslTDA18273.h"
|
||||
|
||||
#include "tmbslTDA18273_RegDef.h"
|
||||
#include "tmbslTDA18273_Local.h"
|
||||
#include "tmbslTDA18273_Instance.h"
|
||||
#include "tmbslTDA18273_InstanceCustom.h"
|
||||
|
||||
|
||||
/*============================================================================*/
|
||||
/* Global data: */
|
||||
/*============================================================================*/
|
||||
|
||||
/* Driver instance */
|
||||
TDA18273Object_t gTDA18273Instance[TDA18273_MAX_UNITS] =
|
||||
{
|
||||
{
|
||||
(tmUnitSelect_t)(-1), /* Unit not set */
|
||||
(tmUnitSelect_t)(-1), /* UnitW not set */
|
||||
Null, /* pMutex */
|
||||
False, /* init (instance initialization default) */
|
||||
{ /* sIo */
|
||||
Null,
|
||||
Null
|
||||
},
|
||||
{ /* sTime */
|
||||
Null,
|
||||
Null
|
||||
},
|
||||
{ /* sDebug */
|
||||
Null
|
||||
},
|
||||
{ /* sMutex */
|
||||
Null,
|
||||
Null,
|
||||
Null,
|
||||
Null
|
||||
},
|
||||
TDA18273_INSTANCE_CUSTOM_0 /* Instance Customizable Settings */
|
||||
},
|
||||
{
|
||||
(tmUnitSelect_t)(-1), /* Unit not set */
|
||||
(tmUnitSelect_t)(-1), /* UnitW not set */
|
||||
Null, /* pMutex */
|
||||
False, /* init (instance initialization default) */
|
||||
{ /* sIo */
|
||||
Null,
|
||||
Null
|
||||
},
|
||||
{ /* sTime */
|
||||
Null,
|
||||
Null
|
||||
},
|
||||
{ /* sDebug */
|
||||
Null
|
||||
},
|
||||
{ /* sMutex */
|
||||
Null,
|
||||
Null,
|
||||
Null,
|
||||
Null
|
||||
},
|
||||
TDA18273_INSTANCE_CUSTOM_1 /* Instance Customizable Settings */
|
||||
}
|
||||
};
|
||||
|
||||
/*============================================================================*/
|
||||
/* Internal functions: */
|
||||
/*============================================================================*/
|
||||
|
||||
/*============================================================================*/
|
||||
/* FUNCTION: iTDA18273_AllocInstance: */
|
||||
/* */
|
||||
/* DESCRIPTION: Allocates an instance. */
|
||||
/* */
|
||||
/* RETURN: TM_OK if no error */
|
||||
/* */
|
||||
/* NOTES: */
|
||||
/*============================================================================*/
|
||||
tmErrorCode_t
|
||||
iTDA18273_AllocInstance(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
ppTDA18273Object_t ppDrvObject /* I: Driver Object */
|
||||
)
|
||||
{
|
||||
tmErrorCode_t err = TDA18273_ERR_ERR_NO_INSTANCES;
|
||||
pTDA18273Object_t pObj = Null;
|
||||
UInt32 uLoopCounter = 0;
|
||||
|
||||
/* Find a free instance */
|
||||
for (uLoopCounter = 0; uLoopCounter<TDA18273_MAX_UNITS; uLoopCounter++)
|
||||
{
|
||||
pObj = &gTDA18273Instance[uLoopCounter];
|
||||
if (pObj->init == False)
|
||||
{
|
||||
err = TM_OK;
|
||||
|
||||
pObj->tUnit = tUnit;
|
||||
pObj->tUnitW = tUnit;
|
||||
|
||||
err = iTDA18273_ResetInstance(pObj);
|
||||
|
||||
if(err == TM_OK)
|
||||
{
|
||||
*ppDrvObject = pObj;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/*============================================================================*/
|
||||
/* FUNCTION: iTDA18273_DeAllocInstance: */
|
||||
/* */
|
||||
/* DESCRIPTION: Deallocates an instance. */
|
||||
/* */
|
||||
/* RETURN: TM_OK if no error */
|
||||
/* */
|
||||
/* NOTES: */
|
||||
/*============================================================================*/
|
||||
tmErrorCode_t
|
||||
iTDA18273_DeAllocInstance(
|
||||
pTDA18273Object_t pDrvObject /* I: Driver Object */
|
||||
)
|
||||
{
|
||||
tmErrorCode_t err = TM_OK;
|
||||
|
||||
if(pDrvObject != Null)
|
||||
{
|
||||
pDrvObject->init = False;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/*============================================================================*/
|
||||
/* FUNCTION: iTDA18273_GetInstance: */
|
||||
/* */
|
||||
/* DESCRIPTION: Gets an instance. */
|
||||
/* */
|
||||
/* RETURN: TM_OK if no error */
|
||||
/* */
|
||||
/* NOTES: */
|
||||
/*============================================================================*/
|
||||
tmErrorCode_t
|
||||
iTDA18273_GetInstance(
|
||||
tmUnitSelect_t tUnit, /* I: Unit number */
|
||||
ppTDA18273Object_t ppDrvObject /* I: Driver Object */
|
||||
)
|
||||
{
|
||||
tmErrorCode_t err = TDA18273_ERR_ERR_NO_INSTANCES;
|
||||
pTDA18273Object_t pObj = Null;
|
||||
UInt32 uLoopCounter = 0;
|
||||
|
||||
/* Get instance */
|
||||
for (uLoopCounter = 0; uLoopCounter<TDA18273_MAX_UNITS; uLoopCounter++)
|
||||
{
|
||||
pObj = &gTDA18273Instance[uLoopCounter];
|
||||
if (pObj->init == True && pObj->tUnit == GET_INDEX_TYPE_TUNIT(tUnit))
|
||||
{
|
||||
pObj->tUnitW = tUnit;
|
||||
|
||||
*ppDrvObject = pObj;
|
||||
err = TM_OK;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/*============================================================================*/
|
||||
/* FUNCTION: iTDA18273_ResetInstance: */
|
||||
/* */
|
||||
/* DESCRIPTION: Resets an instance. */
|
||||
/* */
|
||||
/* RETURN: TM_OK if no error */
|
||||
/* */
|
||||
/* NOTES: */
|
||||
/*============================================================================*/
|
||||
tmErrorCode_t
|
||||
iTDA18273_ResetInstance(
|
||||
pTDA18273Object_t pDrvObject /* I: Driver Object */
|
||||
)
|
||||
{
|
||||
tmErrorCode_t err = TM_OK ;
|
||||
|
||||
pDrvObject->curPowerState = TDA18273_INSTANCE_CUSTOM_CURPOWERSTATE_DEF;
|
||||
pDrvObject->curLLPowerState = TDA18273_INSTANCE_CUSTOM_CURLLPOWERSTATE_DEF;
|
||||
pDrvObject->uRF = TDA18273_INSTANCE_CUSTOM_RF_DEF;
|
||||
pDrvObject->uProgRF = TDA18273_INSTANCE_CUSTOM_PROG_RF_DEF;
|
||||
|
||||
pDrvObject->StandardMode = TDA18273_INSTANCE_CUSTOM_STANDARDMODE_DEF;
|
||||
|
||||
pDrvObject->eHwState = TDA18273_HwState_InitNotDone;
|
||||
|
||||
return err;
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,57 @@
|
||||
/*
|
||||
Copyright (C) 2010 NXP B.V., All Rights Reserved.
|
||||
This source code and any compilation or derivative thereof is the proprietary
|
||||
information of NXP B.V. and is confidential in nature. Under no circumstances
|
||||
is this software to be exposed to or placed under an Open Source License of
|
||||
any type without the expressed written permission of NXP B.V.
|
||||
*
|
||||
* \file tmbslTDA18273_Instance.h
|
||||
*
|
||||
* %version: 3 %
|
||||
*
|
||||
* \date %modify_time%
|
||||
*
|
||||
* \author David LEGENDRE
|
||||
* Michael VANNIER
|
||||
* Christophe CAZETTES
|
||||
*
|
||||
* \brief Describe briefly the purpose of this file.
|
||||
*
|
||||
* REFERENCE DOCUMENTS :
|
||||
* TDA18273_Driver_User_Guide.pdf
|
||||
*
|
||||
* TVFE SW Arch V4 Template: Author Christophe CAZETTES
|
||||
*
|
||||
* \section info Change Information
|
||||
*
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
#ifndef _TMBSL_TDA18273_INSTANCE_H
|
||||
#define _TMBSL_TDA18273_INSTANCE_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
tmErrorCode_t
|
||||
iTDA18273_AllocInstance(tmUnitSelect_t tUnit, ppTDA18273Object_t ppDrvObject);
|
||||
|
||||
tmErrorCode_t
|
||||
iTDA18273_DeAllocInstance(pTDA18273Object_t pDrvObject);
|
||||
|
||||
tmErrorCode_t
|
||||
iTDA18273_GetInstance(tmUnitSelect_t tUnit, ppTDA18273Object_t ppDrvObject);
|
||||
|
||||
tmErrorCode_t
|
||||
iTDA18273_ResetInstance(pTDA18273Object_t pDrvObject);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TMBSL_TDA18273_INSTANCE_H */
|
||||
|
||||
Binary file not shown.
@@ -0,0 +1,872 @@
|
||||
/*
|
||||
Copyright (C) 2010 NXP B.V., All Rights Reserved.
|
||||
This source code and any compilation or derivative thereof is the proprietary
|
||||
information of NXP B.V. and is confidential in nature. Under no circumstances
|
||||
is this software to be exposed to or placed under an Open Source License of
|
||||
any type without the expressed written permission of NXP B.V.
|
||||
*
|
||||
* \file tmbslTDA18273_InstanceCustom.h
|
||||
*
|
||||
* %version: 4 %
|
||||
*
|
||||
* \date %modify_time%
|
||||
*
|
||||
* \author David LEGENDRE
|
||||
* Michael VANNIER
|
||||
* Christophe CAZETTES
|
||||
*
|
||||
* \brief Describe briefly the purpose of this file.
|
||||
*
|
||||
* REFERENCE DOCUMENTS :
|
||||
* TDA18273_Driver_User_Guide.pdf
|
||||
*
|
||||
* TVFE SW Arch V4 Template: Author Christophe CAZETTES
|
||||
*
|
||||
* \section info Change Information
|
||||
*
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
#ifndef _TDA18273_INSTANCE_CUSTOM_H
|
||||
#define _TDA18273_INSTANCE_CUSTOM_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*============================================================================*/
|
||||
/* Types and defines: */
|
||||
/*============================================================================*/
|
||||
|
||||
/* Driver settings version definition */
|
||||
#define TDA18273_SETTINGS_CUSTOMER_NUM (0) /* SW Settings Customer Number */
|
||||
#define TDA18273_SETTINGS_PROJECT_NUM (0) /* SW Settings Project Number */
|
||||
#define TDA18273_SETTINGS_MAJOR_VER (2) /* SW Settings Major Version */
|
||||
#define TDA18273_SETTINGS_MINOR_VER (1) /* SW Settings Minor Version */
|
||||
//TDA18273_IF_Output_Level_1Vpp_min_6_24dB
|
||||
/* Standard Preset Definitions: */
|
||||
#define TDA18273_INSTANCE_CUSTOM_STD_QAM_6MHZ /* defined for Wintech system*/ \
|
||||
{ /* QAM 6MHz */ \
|
||||
5000000, /* IF = 4.75M */ \
|
||||
0, /* CF_Offset */ \
|
||||
TDA18273_LPF_8MHz, /* LPF */ \
|
||||
TDA18273_LPFOffset_0pc, /* LPF_Offset */ \
|
||||
TDA18273_DC_Notch_IF_PPF_Enabled, /* DC notch IF PPF */ \
|
||||
TDA18273_IF_HPF_1_5MHz, /* Hi Pass */ \
|
||||
TDA18273_IF_Notch_Disabled, /* IF notch */ \
|
||||
TDA18273_IFnotchToRSSI_Disabled, /* IF notch To RSSI */ \
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d102_u84dBuV, /* AGC1 TOP I2C DN/UP */ \
|
||||
TDA18273_AGC1_Adapt_TOP_DN_UP_0_Step, /* AGC1 Adapt TOP DN/UP */ \
|
||||
TDA18273_AGC1_Mode_LNA_ADAPT_WIDE, /* AGC1 mode */ \
|
||||
TDA18273_Range_LNA_Adapt_20dB_11dB, /* Range LNA Adapt */ \
|
||||
TDA18273_LNA_Adapt_RFAGC_Gv_Threshold_18_25dB, /* LNA Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC1_Top_Adapt_RFAGC_Gv_Threshold_16_75dB, /* AGC1 TOP Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC2_TOP_DN_UP_d90_u84dBuV, /* AGC2 TOP DN/UP */ \
|
||||
TDA18273_AGC3_TOP_I2C_107dBuV, /* AGC3 TOP I2C */ \
|
||||
TDA18273_AGC4_TOP_DN_UP_d110_u105dBuV, /* AGC4 TOP DN/UP */ \
|
||||
TDA18273_AGC5_TOP_DN_UP_d110_u105dBuV, /* AGC5 TOP DN/UP */ \
|
||||
TDA18273_Top_Adapt_TOP_ADAPT35, /* AGC3 TOP Adapt Algorithm */ \
|
||||
TDA18273_AGC3_Adapt_TOP_2_Step, /* AGC3 Adapt */ \
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_4_5_min_3_5, /* AGC Overload TOP */ \
|
||||
TDA18273_TH_AGC_Adapt34_5dB, /* Adapt TOP 34 Gain Threshold */ \
|
||||
TDA18273_RF_Atten_3dB_Enabled, /* RF Atten 3dB */ \
|
||||
TDA18273_IF_Output_Level_1Vpp_min_6_24dB, /* IF Output Level */ \
|
||||
TDA18273_S2D_Gain_6dB, /* S2D Gain */ \
|
||||
TDA18273_Negative_Modulation_Disabled, /* Negative Modulation */ \
|
||||
TDA18273_AGCK_Steps_0_2dB, /* Step */ \
|
||||
TDA18273_AGCK_Time_Constant_32_768ms, /* AGCK Time Constant */ \
|
||||
TDA18273_AGC5_HPF_Disabled, /* AGC5 HPF */ \
|
||||
TDA18273_Pulse_Shaper_Disable_Enabled, /* Pulse Shaper Disable */ \
|
||||
TDA18273_VHF_III_Mode_Enabled, /* VHF III Mode */ \
|
||||
TDA18273_LO_CP_Current_Enabled /* LO CP Current */ \
|
||||
}
|
||||
|
||||
#define TDA18273_INSTANCE_CUSTOM_STD_QAM_8MHZ \
|
||||
{ /* QAM 8MHz */ \
|
||||
5000000, /* IF */ \
|
||||
0, /* CF_Offset */ \
|
||||
TDA18273_LPF_9MHz, /* LPF */ \
|
||||
TDA18273_LPFOffset_min_8pc, /* LPF_Offset */ \
|
||||
TDA18273_DC_Notch_IF_PPF_Enabled, /* DC notch IF PPF */ \
|
||||
TDA18273_IF_HPF_0_85MHz, /* Hi Pass */ \
|
||||
TDA18273_IF_Notch_Disabled, /* IF notch */ \
|
||||
TDA18273_IFnotchToRSSI_Disabled, /* IF notch To RSSI */ \
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d95_u89wdBuV, /* AGC1 TOP I2C DN/UP */ \
|
||||
TDA18273_AGC1_Adapt_TOP_DN_UP_0_Step, /* AGC1 Adapt TOP DN/UP */ \
|
||||
TDA18273_AGC1_Mode_LNA_ADAPT, /* AGC1 mode */ \
|
||||
TDA18273_Range_LNA_Adapt_20dB_11dB, /* Range LNA Adapt */ \
|
||||
TDA18273_LNA_Adapt_RFAGC_Gv_Threshold_18_25dB, /* LNA Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC1_Top_Adapt_RFAGC_Gv_Threshold_16_75dB, /* AGC1 TOP Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC2_TOP_DN_UP_d90_u84dBuV, /* AGC2 TOP DN/UP */ \
|
||||
TDA18273_AGC3_TOP_I2C_100dBuV, /* AGC3 TOP I2C */ \
|
||||
TDA18273_AGC4_TOP_DN_UP_d110_u105dBuV, /* AGC4 TOP DN/UP */ \
|
||||
TDA18273_AGC5_TOP_DN_UP_d110_u105dBuV, /* AGC5 TOP DN/UP */ \
|
||||
TDA18273_Top_Adapt_NO_TOP_ADAPT, /* AGC3 TOP Adapt Algorithm */ \
|
||||
TDA18273_AGC3_Adapt_TOP_0_Step, /* AGC3 Adapt */ \
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_4_5_min_3_5, /* AGC Overload TOP */ \
|
||||
TDA18273_TH_AGC_Adapt34_5dB, /* Adapt TOP 34 Gain Threshold */ \
|
||||
TDA18273_RF_Atten_3dB_Disabled, /* RF Atten 3dB */ \
|
||||
TDA18273_IF_Output_Level_1Vpp_min_6_24dB, /* IF Output Level */ \
|
||||
TDA18273_S2D_Gain_6dB, /* S2D Gain */ \
|
||||
TDA18273_Negative_Modulation_Disabled, /* Negative Modulation */ \
|
||||
TDA18273_AGCK_Steps_0_2dB, /* Step */ \
|
||||
TDA18273_AGCK_Time_Constant_32_768ms, /* AGCK Time Constant */ \
|
||||
TDA18273_AGC5_HPF_Disabled, /* AGC5 HPF */ \
|
||||
TDA18273_Pulse_Shaper_Disable_Enabled, /* Pulse Shaper Disable */ \
|
||||
TDA18273_VHF_III_Mode_Disabled, /* VHF III Mode */ \
|
||||
TDA18273_LO_CP_Current_Enabled /* LO CP Current */ \
|
||||
}
|
||||
|
||||
#define TDA18273_INSTANCE_CUSTOM_STD_ATSC_6MHZ \
|
||||
{ /* ATSC */ \
|
||||
5000000, /* IF */ \
|
||||
0, /* CF_Offset */ \
|
||||
TDA18273_LPF_9MHz, /* LPF */ \
|
||||
TDA18273_LPFOffset_0pc, /* LPF_Offset */ \
|
||||
TDA18273_DC_Notch_IF_PPF_Enabled, /* DC notch IF PPF */ \
|
||||
TDA18273_IF_HPF_0_4MHz, /* Hi Pass */ \
|
||||
TDA18273_IF_Notch_Disabled, /* IF notch */ \
|
||||
TDA18273_IFnotchToRSSI_Disabled, /* IF notch To RSSI */ \
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d100_u94dBuV, /* AGC1 TOP I2C DN/UP */ \
|
||||
TDA18273_AGC1_Adapt_TOP_DN_UP_0_Step, /* AGC1 Adapt TOP DN/UP */ \
|
||||
TDA18273_AGC1_Mode_LNA_ADAPT, /* AGC1 mode */ \
|
||||
TDA18273_Range_LNA_Adapt_20dB_11dB, /* Range LNA Adapt */ \
|
||||
TDA18273_LNA_Adapt_RFAGC_Gv_Threshold_18_25dB, /* LNA Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC1_Top_Adapt_RFAGC_Gv_Threshold_16_75dB, /* AGC1 TOP Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC2_TOP_DN_UP_d90_u84dBuV, /* AGC2 TOP DN/UP */ \
|
||||
TDA18273_AGC3_TOP_I2C_104dBuV, /* AGC3 TOP I2C */ \
|
||||
TDA18273_AGC4_TOP_DN_UP_d112_u107dBuV, /* AGC4 TOP DN/UP */ \
|
||||
TDA18273_AGC5_TOP_DN_UP_d112_u107dBuV, /* AGC5 TOP DN/UP */ \
|
||||
TDA18273_Top_Adapt_TOP_ADAPT35, /* AGC3 TOP Adapt Algorithm */ \
|
||||
TDA18273_AGC3_Adapt_TOP_3_Step, /* AGC3 Adapt */ \
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_4_5_min_3_5, /* AGC Overload TOP */ \
|
||||
TDA18273_TH_AGC_Adapt34_5dB, /* Adapt TOP 34 Gain Threshold */ \
|
||||
TDA18273_RF_Atten_3dB_Enabled, /* RF Atten 3dB */ \
|
||||
TDA18273_IF_Output_Level_1Vpp_min_6_24dB, /* IF Output Level */ \
|
||||
TDA18273_S2D_Gain_3dB, /* S2D Gain */ \
|
||||
TDA18273_Negative_Modulation_Disabled, /* Negative Modulation */ \
|
||||
TDA18273_AGCK_Steps_0_2dB, /* Step */ \
|
||||
TDA18273_AGCK_Time_Constant_32_768ms, /* AGCK Time Constant */ \
|
||||
TDA18273_AGC5_HPF_Disabled, /* AGC5 HPF */ \
|
||||
TDA18273_Pulse_Shaper_Disable_Enabled, /* Pulse Shaper Disable */ \
|
||||
TDA18273_VHF_III_Mode_Enabled, /* VHF III Mode */ \
|
||||
TDA18273_LO_CP_Current_Enabled /* LO CP Current */ \
|
||||
}
|
||||
|
||||
#define TDA18273_INSTANCE_CUSTOM_STD_ISDBT_6MHZ \
|
||||
{ /* ISDBT */ \
|
||||
3250000, /* IF */ \
|
||||
0, /* CF_Offset */ \
|
||||
TDA18273_LPF_6MHz, /* LPF */ \
|
||||
TDA18273_LPFOffset_0pc, /* LPF_Offset */ \
|
||||
TDA18273_DC_Notch_IF_PPF_Enabled, /* DC notch IF PPF */ \
|
||||
TDA18273_IF_HPF_0_4MHz, /* Hi Pass */ \
|
||||
TDA18273_IF_Notch_Enabled, /* IF notch */ \
|
||||
TDA18273_IFnotchToRSSI_Disabled, /* IF notch To RSSI */ \
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d95_u89dBuV, /* AGC1 TOP I2C DN/UP */ \
|
||||
TDA18273_AGC1_Adapt_TOP_DN_UP_0_Step, /* AGC1 Adapt TOP DN/UP */ \
|
||||
TDA18273_AGC1_Mode_LNA_ADAPT, /* AGC1 mode */ \
|
||||
TDA18273_Range_LNA_Adapt_20dB_11dB, /* Range LNA Adapt */ \
|
||||
TDA18273_LNA_Adapt_RFAGC_Gv_Threshold_18_25dB, /* LNA Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC1_Top_Adapt_RFAGC_Gv_Threshold_16_75dB, /* AGC1 TOP Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC2_TOP_DN_UP_d90_u84dBuV, /* AGC2 TOP DN/UP */ \
|
||||
TDA18273_AGC3_TOP_I2C_100dBuV, /* AGC3 TOP I2C */ \
|
||||
TDA18273_AGC4_TOP_DN_UP_d110_u105dBuV, /* AGC4 TOP DN/UP */ \
|
||||
TDA18273_AGC5_TOP_DN_UP_d110_u105dBuV, /* AGC5 TOP DN/UP */ \
|
||||
TDA18273_Top_Adapt_TOP_ADAPT35, /* AGC3 TOP Adapt Algorithm */ \
|
||||
TDA18273_AGC3_Adapt_TOP_2_Step, /* AGC3 Adapt */ \
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_4_5_min_3_5, /* AGC Overload TOP */ \
|
||||
TDA18273_TH_AGC_Adapt34_5dB, /* Adapt TOP 34 Gain Threshold */ \
|
||||
TDA18273_RF_Atten_3dB_Enabled, /* RF Atten 3dB */ \
|
||||
TDA18273_IF_Output_Level_0_6Vpp_min_10_3_19_7dB, /* IF Output Level */ \
|
||||
TDA18273_S2D_Gain_6dB, /* S2D Gain */ \
|
||||
TDA18273_Negative_Modulation_Disabled, /* Negative Modulation */ \
|
||||
TDA18273_AGCK_Steps_0_2dB, /* Step */ \
|
||||
TDA18273_AGCK_Time_Constant_32_768ms, /* AGCK Time Constant */ \
|
||||
TDA18273_AGC5_HPF_Disabled, /* AGC5 HPF */ \
|
||||
TDA18273_Pulse_Shaper_Disable_Enabled, /* Pulse Shaper Disable */ \
|
||||
TDA18273_VHF_III_Mode_Enabled, /* VHF III Mode */ \
|
||||
TDA18273_LO_CP_Current_Enabled /* LO CP Current */ \
|
||||
}
|
||||
|
||||
#define TDA18273_INSTANCE_CUSTOM_STD_DVBT_1_7MHZ \
|
||||
{ /* DVB-T/T2 1.7MHz */ \
|
||||
850000, /* IF */ \
|
||||
0, /* CF_Offset */ \
|
||||
TDA18273_LPF_1_5MHz, /* LPF */ \
|
||||
TDA18273_LPFOffset_0pc, /* LPF_Offset */ \
|
||||
TDA18273_DC_Notch_IF_PPF_Disabled, /* DC notch IF PPF */ \
|
||||
TDA18273_IF_HPF_Disabled, /* Hi Pass */ \
|
||||
TDA18273_IF_Notch_Disabled, /* IF notch */ \
|
||||
TDA18273_IFnotchToRSSI_Enabled, /* IF notch To RSSI */ \
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d95_u89dBuV, /* AGC1 TOP I2C DN/UP */ \
|
||||
TDA18273_AGC1_Adapt_TOP_DN_UP_0_Step, /* AGC1 Adapt TOP DN/UP */ \
|
||||
TDA18273_AGC1_Mode_LNA_ADAPT, /* AGC1 mode */ \
|
||||
TDA18273_Range_LNA_Adapt_20dB_11dB, /* Range LNA Adapt */ \
|
||||
TDA18273_LNA_Adapt_RFAGC_Gv_Threshold_18_25dB, /* LNA Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC1_Top_Adapt_RFAGC_Gv_Threshold_16_75dB, /* AGC1 TOP Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC2_TOP_DN_UP_d90_u84dBuV, /* AGC2 TOP DN/UP */ \
|
||||
TDA18273_AGC3_TOP_I2C_100dBuV, /* AGC3 TOP I2C */ \
|
||||
TDA18273_AGC4_TOP_DN_UP_d110_u105dBuV, /* AGC4 TOP DN/UP */ \
|
||||
TDA18273_AGC5_TOP_DN_UP_d110_u105dBuV, /* AGC5 TOP DN/UP */ \
|
||||
TDA18273_Top_Adapt_TOP_ADAPT35, /* AGC3 TOP Adapt Algorithm */ \
|
||||
TDA18273_AGC3_Adapt_TOP_2_Step, /* AGC3 Adapt */ \
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_4_5_min_3_5, /* AGC Overload TOP */ \
|
||||
TDA18273_TH_AGC_Adapt34_5dB, /* Adapt TOP 34 Gain Threshold */ \
|
||||
TDA18273_RF_Atten_3dB_Enabled, /* RF Atten 3dB */ \
|
||||
TDA18273_IF_Output_Level_1Vpp_min_6_24dB, /* IF Output Level */ \
|
||||
TDA18273_S2D_Gain_6dB, /* S2D Gain */ \
|
||||
TDA18273_Negative_Modulation_Disabled, /* Negative Modulation */ \
|
||||
TDA18273_AGCK_Steps_0_2dB, /* Step */ \
|
||||
TDA18273_AGCK_Time_Constant_32_768ms, /* AGCK Time Constant */ \
|
||||
TDA18273_AGC5_HPF_Disabled, /* AGC5 HPF */ \
|
||||
TDA18273_Pulse_Shaper_Disable_Enabled, /* Pulse Shaper Disable */ \
|
||||
TDA18273_VHF_III_Mode_Enabled, /* VHF III Mode */ \
|
||||
TDA18273_LO_CP_Current_Enabled /* LO CP Current */ \
|
||||
}
|
||||
|
||||
#define TDA18273_INSTANCE_CUSTOM_STD_DVBT_6MHZ \
|
||||
{ /* DVB-T/T2 6MHz */ \
|
||||
3250000, /* IF */ \
|
||||
0, /* CF_Offset */ \
|
||||
TDA18273_LPF_6MHz, /* LPF */ \
|
||||
TDA18273_LPFOffset_0pc, /* LPF_Offset */ \
|
||||
TDA18273_DC_Notch_IF_PPF_Enabled, /* DC notch IF PPF */ \
|
||||
TDA18273_IF_HPF_0_4MHz, /* Hi Pass */ \
|
||||
TDA18273_IF_Notch_Enabled, /* IF notch */ \
|
||||
TDA18273_IFnotchToRSSI_Disabled, /* IF notch To RSSI */ \
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d95_u89dBuV, /* AGC1 TOP I2C DN/UP */ \
|
||||
TDA18273_AGC1_Adapt_TOP_DN_UP_0_Step, /* AGC1 Adapt TOP DN/UP */ \
|
||||
TDA18273_AGC1_Mode_LNA_ADAPT, /* AGC1 mode */ \
|
||||
TDA18273_Range_LNA_Adapt_20dB_11dB, /* Range LNA Adapt */ \
|
||||
TDA18273_LNA_Adapt_RFAGC_Gv_Threshold_18_25dB, /* LNA Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC1_Top_Adapt_RFAGC_Gv_Threshold_16_75dB, /* AGC1 TOP Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC2_TOP_DN_UP_d90_u84dBuV, /* AGC2 TOP DN/UP */ \
|
||||
TDA18273_AGC3_TOP_I2C_100dBuV, /* AGC3 TOP I2C */ \
|
||||
TDA18273_AGC4_TOP_DN_UP_d110_u105dBuV, /* AGC4 TOP DN/UP */ \
|
||||
TDA18273_AGC5_TOP_DN_UP_d110_u105dBuV, /* AGC5 TOP DN/UP */ \
|
||||
TDA18273_Top_Adapt_TOP_ADAPT35, /* AGC3 TOP Adapt Algorithm */ \
|
||||
TDA18273_AGC3_Adapt_TOP_2_Step, /* AGC3 Adapt */ \
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_4_5_min_3_5, /* AGC Overload TOP */ \
|
||||
TDA18273_TH_AGC_Adapt34_5dB, /* Adapt TOP 34 Gain Threshold */ \
|
||||
TDA18273_RF_Atten_3dB_Enabled, /* RF Atten 3dB */ \
|
||||
TDA18273_IF_Output_Level_1Vpp_min_6_24dB, /* IF Output Level */ \
|
||||
TDA18273_S2D_Gain_6dB, /* S2D Gain */ \
|
||||
TDA18273_Negative_Modulation_Disabled, /* Negative Modulation */ \
|
||||
TDA18273_AGCK_Steps_0_2dB, /* Step */ \
|
||||
TDA18273_AGCK_Time_Constant_32_768ms, /* AGCK Time Constant */ \
|
||||
TDA18273_AGC5_HPF_Disabled, /* AGC5 HPF */ \
|
||||
TDA18273_Pulse_Shaper_Disable_Enabled, /* Pulse Shaper Disable */ \
|
||||
TDA18273_VHF_III_Mode_Enabled, /* VHF III Mode */ \
|
||||
TDA18273_LO_CP_Current_Enabled /* LO CP Current */ \
|
||||
}
|
||||
|
||||
#define TDA18273_INSTANCE_CUSTOM_STD_DVBT_7MHZ \
|
||||
{ /* DVB-T/T2 7MHz */ \
|
||||
3500000, /* IF */ \
|
||||
0, /* CF_Offset */ \
|
||||
TDA18273_LPF_7MHz, /* LPF */ \
|
||||
TDA18273_LPFOffset_min_8pc, /* LPF_Offset */ \
|
||||
TDA18273_DC_Notch_IF_PPF_Enabled, /* DC notch IF PPF */ \
|
||||
TDA18273_IF_HPF_Disabled, /* Hi Pass */ \
|
||||
TDA18273_IF_Notch_Enabled, /* IF notch */ \
|
||||
TDA18273_IFnotchToRSSI_Disabled, /* IF notch To RSSI */ \
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d95_u89dBuV, /* AGC1 TOP I2C DN/UP */ \
|
||||
TDA18273_AGC1_Adapt_TOP_DN_UP_0_Step, /* AGC1 Adapt TOP DN/UP */ \
|
||||
TDA18273_AGC1_Mode_LNA_ADAPT, /* AGC1 mode */ \
|
||||
TDA18273_Range_LNA_Adapt_20dB_11dB, /* Range LNA Adapt */ \
|
||||
TDA18273_LNA_Adapt_RFAGC_Gv_Threshold_18_25dB, /* LNA Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC1_Top_Adapt_RFAGC_Gv_Threshold_16_75dB, /* AGC1 TOP Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC2_TOP_DN_UP_d90_u84dBuV, /* AGC2 TOP DN/UP */ \
|
||||
TDA18273_AGC3_TOP_I2C_100dBuV, /* AGC3 TOP I2C */ \
|
||||
TDA18273_AGC4_TOP_DN_UP_d110_u105dBuV, /* AGC4 TOP DN/UP */ \
|
||||
TDA18273_AGC5_TOP_DN_UP_d110_u105dBuV, /* AGC5 TOP DN/UP */ \
|
||||
TDA18273_Top_Adapt_TOP_ADAPT35, /* AGC3 TOP Adapt Algorithm */ \
|
||||
TDA18273_AGC3_Adapt_TOP_2_Step, /* AGC3 Adapt */ \
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_4_5_min_3_5, /* AGC Overload TOP */ \
|
||||
TDA18273_TH_AGC_Adapt34_5dB, /* Adapt TOP 34 Gain Threshold */ \
|
||||
TDA18273_RF_Atten_3dB_Enabled, /* RF Atten 3dB */ \
|
||||
TDA18273_IF_Output_Level_1Vpp_min_6_24dB, /* IF Output Level */ \
|
||||
TDA18273_S2D_Gain_6dB, /* S2D Gain */ \
|
||||
TDA18273_Negative_Modulation_Disabled, /* Negative Modulation */ \
|
||||
TDA18273_AGCK_Steps_0_2dB, /* Step */ \
|
||||
TDA18273_AGCK_Time_Constant_32_768ms, /* AGCK Time Constant */ \
|
||||
TDA18273_AGC5_HPF_Disabled, /* AGC5 HPF */ \
|
||||
TDA18273_Pulse_Shaper_Disable_Enabled, /* Pulse Shaper Disable */ \
|
||||
TDA18273_VHF_III_Mode_Enabled, /* VHF III Mode */ \
|
||||
TDA18273_LO_CP_Current_Enabled /* LO CP Current */ \
|
||||
}
|
||||
|
||||
#define TDA18273_INSTANCE_CUSTOM_STD_DVBT_8MHZ \
|
||||
{ /* DVB-T/T2 8MHz */ \
|
||||
4000000, /* IF */ \
|
||||
0, /* CF_Offset */ \
|
||||
TDA18273_LPF_8MHz, /* LPF */ \
|
||||
TDA18273_LPFOffset_0pc, /* LPF_Offset */ \
|
||||
TDA18273_DC_Notch_IF_PPF_Enabled, /* DC notch IF PPF */ \
|
||||
TDA18273_IF_HPF_Disabled, /* Hi Pass */ \
|
||||
TDA18273_IF_Notch_Enabled, /* IF notch */ \
|
||||
TDA18273_IFnotchToRSSI_Disabled, /* IF notch To RSSI */ \
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d95_u89dBuV, /* AGC1 TOP I2C DN/UP */ \
|
||||
TDA18273_AGC1_Adapt_TOP_DN_UP_0_Step, /* AGC1 Adapt TOP DN/UP */ \
|
||||
TDA18273_AGC1_Mode_LNA_ADAPT, /* AGC1 mode */ \
|
||||
TDA18273_Range_LNA_Adapt_20dB_11dB, /* Range LNA Adapt */ \
|
||||
TDA18273_LNA_Adapt_RFAGC_Gv_Threshold_18_25dB, /* LNA Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC1_Top_Adapt_RFAGC_Gv_Threshold_16_75dB, /* AGC1 TOP Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC2_TOP_DN_UP_d90_u84dBuV, /* AGC2 TOP DN/UP */ \
|
||||
TDA18273_AGC3_TOP_I2C_100dBuV, /* AGC3 TOP I2C */ \
|
||||
TDA18273_AGC4_TOP_DN_UP_d110_u105dBuV, /* AGC4 TOP DN/UP */ \
|
||||
TDA18273_AGC5_TOP_DN_UP_d110_u105dBuV, /* AGC5 TOP DN/UP */ \
|
||||
TDA18273_Top_Adapt_TOP_ADAPT35, /* AGC3 TOP Adapt Algorithm */ \
|
||||
TDA18273_AGC3_Adapt_TOP_2_Step, /* AGC3 Adapt */ \
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_4_5_min_3_5, /* AGC Overload TOP */ \
|
||||
TDA18273_TH_AGC_Adapt34_5dB, /* Adapt TOP 34 Gain Threshold */ \
|
||||
TDA18273_RF_Atten_3dB_Enabled, /* RF Atten 3dB */ \
|
||||
TDA18273_IF_Output_Level_1Vpp_min_6_24dB, /* IF Output Level */ \
|
||||
TDA18273_S2D_Gain_6dB, /* S2D Gain */ \
|
||||
TDA18273_Negative_Modulation_Disabled, /* Negative Modulation */ \
|
||||
TDA18273_AGCK_Steps_0_2dB, /* Step */ \
|
||||
TDA18273_AGCK_Time_Constant_32_768ms, /* AGCK Time Constant */ \
|
||||
TDA18273_AGC5_HPF_Disabled, /* AGC5 HPF */ \
|
||||
TDA18273_Pulse_Shaper_Disable_Enabled, /* Pulse Shaper Disable */ \
|
||||
TDA18273_VHF_III_Mode_Enabled, /* VHF III Mode */ \
|
||||
TDA18273_LO_CP_Current_Enabled /* LO CP Current */ \
|
||||
}
|
||||
|
||||
#define TDA18273_INSTANCE_CUSTOM_STD_DVBT_10MHZ \
|
||||
{ /* DVB-T/T2 10MHz */ \
|
||||
5000000, /* IF */ \
|
||||
0, /* CF_Offset */ \
|
||||
TDA18273_LPF_9MHz, /* LPF */ \
|
||||
TDA18273_LPFOffset_0pc, /* LPF_Offset */ \
|
||||
TDA18273_DC_Notch_IF_PPF_Enabled, /* DC notch IF PPF */ \
|
||||
TDA18273_IF_HPF_Disabled, /* Hi Pass */ \
|
||||
TDA18273_IF_Notch_Disabled, /* IF notch */ \
|
||||
TDA18273_IFnotchToRSSI_Enabled, /* IF notch To RSSI */ \
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d95_u89dBuV, /* AGC1 TOP I2C DN/UP */ \
|
||||
TDA18273_AGC1_Adapt_TOP_DN_UP_0_Step, /* AGC1 Adapt TOP DN/UP */ \
|
||||
TDA18273_AGC1_Mode_LNA_ADAPT, /* AGC1 mode */ \
|
||||
TDA18273_Range_LNA_Adapt_20dB_11dB, /* Range LNA Adapt */ \
|
||||
TDA18273_LNA_Adapt_RFAGC_Gv_Threshold_18_25dB, /* LNA Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC1_Top_Adapt_RFAGC_Gv_Threshold_16_75dB, /* AGC1 TOP Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC2_TOP_DN_UP_d90_u84dBuV, /* AGC2 TOP DN/UP */ \
|
||||
TDA18273_AGC3_TOP_I2C_100dBuV, /* AGC3 TOP I2C */ \
|
||||
TDA18273_AGC4_TOP_DN_UP_d110_u105dBuV, /* AGC4 TOP DN/UP */ \
|
||||
TDA18273_AGC5_TOP_DN_UP_d110_u105dBuV, /* AGC5 TOP DN/UP */ \
|
||||
TDA18273_Top_Adapt_TOP_ADAPT35, /* AGC3 TOP Adapt Algorithm */ \
|
||||
TDA18273_AGC3_Adapt_TOP_2_Step, /* AGC3 Adapt */ \
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_4_5_min_3_5, /* AGC Overload TOP */ \
|
||||
TDA18273_TH_AGC_Adapt34_5dB, /* Adapt TOP 34 Gain Threshold */ \
|
||||
TDA18273_RF_Atten_3dB_Enabled, /* RF Atten 3dB */ \
|
||||
TDA18273_IF_Output_Level_1Vpp_min_6_24dB, /* IF Output Level */ \
|
||||
TDA18273_S2D_Gain_6dB, /* S2D Gain */ \
|
||||
TDA18273_Negative_Modulation_Disabled, /* Negative Modulation */ \
|
||||
TDA18273_AGCK_Steps_0_2dB, /* Step */ \
|
||||
TDA18273_AGCK_Time_Constant_32_768ms, /* AGCK Time Constant */ \
|
||||
TDA18273_AGC5_HPF_Disabled, /* AGC5 HPF */ \
|
||||
TDA18273_Pulse_Shaper_Disable_Enabled, /* Pulse Shaper Disable */ \
|
||||
TDA18273_VHF_III_Mode_Enabled, /* VHF III Mode */ \
|
||||
TDA18273_LO_CP_Current_Enabled /* LO CP Current */ \
|
||||
}
|
||||
|
||||
#define TDA18273_INSTANCE_CUSTOM_STD_DMBT_8MHZ \
|
||||
{ /* DMB-T */ \
|
||||
4000000, /* IF */ \
|
||||
0, /* CF_Offset */ \
|
||||
TDA18273_LPF_8MHz, /* LPF */ \
|
||||
TDA18273_LPFOffset_0pc, /* LPF_Offset */ \
|
||||
TDA18273_DC_Notch_IF_PPF_Enabled, /* DC notch IF PPF */ \
|
||||
TDA18273_IF_HPF_Disabled, /* Hi Pass */ \
|
||||
TDA18273_IF_Notch_Enabled, /* IF notch */ \
|
||||
TDA18273_IFnotchToRSSI_Disabled, /* IF notch To RSSI */ \
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d95_u89dBuV, /* AGC1 TOP I2C DN/UP */ \
|
||||
TDA18273_AGC1_Adapt_TOP_DN_UP_0_Step, /* AGC1 Adapt TOP DN/UP */ \
|
||||
TDA18273_AGC1_Mode_LNA_ADAPT, /* AGC1 mode */ \
|
||||
TDA18273_Range_LNA_Adapt_20dB_11dB, /* Range LNA Adapt */ \
|
||||
TDA18273_LNA_Adapt_RFAGC_Gv_Threshold_18_25dB, /* LNA Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC1_Top_Adapt_RFAGC_Gv_Threshold_16_75dB, /* AGC1 TOP Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC2_TOP_DN_UP_d90_u84dBuV, /* AGC2 TOP DN/UP */ \
|
||||
TDA18273_AGC3_TOP_I2C_100dBuV, /* AGC3 TOP I2C */ \
|
||||
TDA18273_AGC4_TOP_DN_UP_d110_u105dBuV, /* AGC4 TOP DN/UP */ \
|
||||
TDA18273_AGC5_TOP_DN_UP_d110_u105dBuV, /* AGC5 TOP DN/UP */ \
|
||||
TDA18273_Top_Adapt_TOP_ADAPT35, /* AGC3 TOP Adapt Algorithm */ \
|
||||
TDA18273_AGC3_Adapt_TOP_2_Step, /* AGC3 Adapt */ \
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_4_5_min_3_5, /* AGC Overload TOP */ \
|
||||
TDA18273_TH_AGC_Adapt34_5dB, /* Adapt TOP 34 Gain Threshold */ \
|
||||
TDA18273_RF_Atten_3dB_Enabled, /* RF Atten 3dB */ \
|
||||
TDA18273_IF_Output_Level_1Vpp_min_6_24dB, /* IF Output Level */ \
|
||||
TDA18273_S2D_Gain_6dB, /* S2D Gain */ \
|
||||
TDA18273_Negative_Modulation_Disabled, /* Negative Modulation */ \
|
||||
TDA18273_AGCK_Steps_0_2dB, /* Step */ \
|
||||
TDA18273_AGCK_Time_Constant_32_768ms, /* AGCK Time Constant */ \
|
||||
TDA18273_AGC5_HPF_Disabled, /* AGC5 HPF */ \
|
||||
TDA18273_Pulse_Shaper_Disable_Enabled, /* Pulse Shaper Disable */ \
|
||||
TDA18273_VHF_III_Mode_Enabled, /* VHF III Mode */ \
|
||||
TDA18273_LO_CP_Current_Enabled /* LO CP Current */ \
|
||||
}
|
||||
|
||||
#define TDA18273_INSTANCE_CUSTOM_STD_ANALOG_FM_RADIO \
|
||||
{ /* FM */ \
|
||||
1250000, /* IF */ \
|
||||
0, /* CF_Offset */ \
|
||||
TDA18273_LPF_1_5MHz, /* LPF */ \
|
||||
TDA18273_LPFOffset_0pc, /* LPF_Offset */ \
|
||||
TDA18273_DC_Notch_IF_PPF_Enabled, /* DC notch IF PPF */ \
|
||||
TDA18273_IF_HPF_0_85MHz, /* Hi Pass */ \
|
||||
TDA18273_IF_Notch_Disabled, /* IF notch */ \
|
||||
TDA18273_IFnotchToRSSI_Disabled, /* IF notch To RSSI */ \
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d95_u89dBuV, /* AGC1 TOP I2C DN/UP */ \
|
||||
TDA18273_AGC1_Adapt_TOP_DN_UP_1_Step, /* AGC1 Adapt TOP DN/UP */ \
|
||||
TDA18273_AGC1_Mode_LNA_ADAPT_TOP_ADAPT, /* AGC1 mode */ \
|
||||
TDA18273_Range_LNA_Adapt_20dB_11dB, /* Range LNA Adapt */ \
|
||||
TDA18273_LNA_Adapt_RFAGC_Gv_Threshold_18_25dB, /* LNA Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC1_Top_Adapt_RFAGC_Gv_Threshold_15_25dB, /* AGC1 TOP Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC2_TOP_DN_UP_d90_u84dBuV, /* AGC2 TOP DN/UP */ \
|
||||
TDA18273_AGC3_TOP_I2C_96dBuV, /* AGC3 TOP I2C */ \
|
||||
TDA18273_AGC4_TOP_DN_UP_d105_u100dBuV, /* AGC4 TOP DN/UP */ \
|
||||
TDA18273_AGC5_TOP_DN_UP_d105_u100dBuV, /* AGC5 TOP DN/UP */ \
|
||||
TDA18273_Top_Adapt_TOP_ADAPT34, /* AGC3 TOP Adapt Algorithm */ \
|
||||
TDA18273_AGC3_Adapt_TOP_1_Step, /* AGC3 Adapt */ \
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_4_5_min_3_5, /* AGC Overload TOP */ \
|
||||
TDA18273_TH_AGC_Adapt34_5dB, /* Adapt TOP 34 Gain Threshold */ \
|
||||
TDA18273_RF_Atten_3dB_Disabled, /* RF Atten 3dB */ \
|
||||
TDA18273_IF_Output_Level_0_8Vpp_min_8_22dB, /* IF Output Level */ \
|
||||
TDA18273_S2D_Gain_6dB, /* S2D Gain */ \
|
||||
TDA18273_Negative_Modulation_Disabled, /* Negative Modulation */ \
|
||||
TDA18273_AGCK_Steps_0_2dB, /* Step */ \
|
||||
TDA18273_AGCK_Time_Constant_32_768ms, /* AGCK Time Constant */ \
|
||||
TDA18273_AGC5_HPF_Disabled, /* AGC5 HPF */ \
|
||||
TDA18273_Pulse_Shaper_Disable_Enabled, /* Pulse Shaper Disable */ \
|
||||
TDA18273_VHF_III_Mode_Disabled, /* VHF III Mode */ \
|
||||
TDA18273_LO_CP_Current_Enabled /* LO CP Current */ \
|
||||
}
|
||||
|
||||
#define TDA18273_INSTANCE_CUSTOM_STD_ANALOG_MN \
|
||||
{ /* NTSC M/N */ \
|
||||
5400000, /* IF */ \
|
||||
1750000, /* CF_Offset */ \
|
||||
TDA18273_LPF_6MHz, /* LPF */ \
|
||||
TDA18273_LPFOffset_0pc, /* LPF_Offset */ \
|
||||
TDA18273_DC_Notch_IF_PPF_Disabled, /* DC notch IF PPF */ \
|
||||
TDA18273_IF_HPF_Disabled, /* Hi Pass */ \
|
||||
TDA18273_IF_Notch_Disabled, /* IF notch */ \
|
||||
TDA18273_IFnotchToRSSI_Enabled, /* IF notch To RSSI */ \
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d95_u89dBuV, /* AGC1 TOP I2C DN/UP */ \
|
||||
TDA18273_AGC1_Adapt_TOP_DN_UP_1_Step, /* AGC1 Adapt TOP DN/UP */ \
|
||||
TDA18273_AGC1_Mode_LNA_ADAPT_TOP_ADAPT, /* AGC1 mode */ \
|
||||
TDA18273_Range_LNA_Adapt_20dB_11dB, /* Range LNA Adapt */ \
|
||||
TDA18273_LNA_Adapt_RFAGC_Gv_Threshold_18_25dB, /* LNA Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC1_Top_Adapt_RFAGC_Gv_Threshold_15_25dB, /* AGC1 TOP Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC2_TOP_DN_UP_d90_u84dBuV, /* AGC2 TOP DN/UP */ \
|
||||
TDA18273_AGC3_TOP_I2C_96dBuV, /* AGC3 TOP I2C */ \
|
||||
TDA18273_AGC4_TOP_DN_UP_d105_u100dBuV, /* AGC4 TOP DN/UP */ \
|
||||
TDA18273_AGC5_TOP_DN_UP_d105_u100dBuV, /* AGC5 TOP DN/UP */ \
|
||||
TDA18273_Top_Adapt_TOP_ADAPT34, /* AGC3 TOP Adapt Algorithm */ \
|
||||
TDA18273_AGC3_Adapt_TOP_1_Step, /* AGC3 Adapt */ \
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_4_5_min_3_5, /* AGC Overload TOP */ \
|
||||
TDA18273_TH_AGC_Adapt34_5dB, /* Adapt TOP 34 Gain Threshold */ \
|
||||
TDA18273_RF_Atten_3dB_Disabled, /* RF Atten 3dB */ \
|
||||
TDA18273_IF_Output_Level_0_7Vpp_min_9_21dB, /* IF Output Level */ \
|
||||
TDA18273_S2D_Gain_6dB, /* S2D Gain */ \
|
||||
TDA18273_Negative_Modulation_Enabled, /* Negative Modulation */ \
|
||||
TDA18273_AGCK_Steps_0_2dB, /* Step */ \
|
||||
TDA18273_AGCK_Time_Constant_1_STEP_EACH_VSYNC_RISING_EDGE, /* AGCK Time Constant */ \
|
||||
TDA18273_AGC5_HPF_Enabled, /* AGC5 HPF */ \
|
||||
TDA18273_Pulse_Shaper_Disable_Enabled, /* Pulse Shaper Disable */ \
|
||||
TDA18273_VHF_III_Mode_Disabled, /* VHF III Mode */ \
|
||||
TDA18273_LO_CP_Current_Enabled /* LO CP Current */ \
|
||||
}
|
||||
|
||||
#define TDA18273_INSTANCE_CUSTOM_STD_ANALOG_B \
|
||||
{ /* PAL B */ \
|
||||
6400000, /* IF */ \
|
||||
2250000, /* CF_Offset */ \
|
||||
TDA18273_LPF_7MHz, /* LPF */ \
|
||||
TDA18273_LPFOffset_0pc, /* LPF_Offset */ \
|
||||
TDA18273_DC_Notch_IF_PPF_Disabled, /* DC notch IF PPF */ \
|
||||
TDA18273_IF_HPF_Disabled, /* Hi Pass */ \
|
||||
TDA18273_IF_Notch_Disabled, /* IF notch */ \
|
||||
TDA18273_IFnotchToRSSI_Enabled, /* IF notch To RSSI */ \
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d95_u89dBuV, /* AGC1 TOP I2C DN/UP */ \
|
||||
TDA18273_AGC1_Adapt_TOP_DN_UP_1_Step, /* AGC1 Adapt TOP DN/UP */ \
|
||||
TDA18273_AGC1_Mode_LNA_ADAPT_TOP_ADAPT, /* AGC1 mode */ \
|
||||
TDA18273_Range_LNA_Adapt_20dB_11dB, /* Range LNA Adapt */ \
|
||||
TDA18273_LNA_Adapt_RFAGC_Gv_Threshold_18_25dB, /* LNA Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC1_Top_Adapt_RFAGC_Gv_Threshold_15_25dB, /* AGC1 TOP Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC2_TOP_DN_UP_d90_u84dBuV, /* AGC2 TOP DN/UP */ \
|
||||
TDA18273_AGC3_TOP_I2C_96dBuV, /* AGC3 TOP I2C */ \
|
||||
TDA18273_AGC4_TOP_DN_UP_d105_u100dBuV, /* AGC4 TOP DN/UP */ \
|
||||
TDA18273_AGC5_TOP_DN_UP_d105_u100dBuV, /* AGC5 TOP DN/UP */ \
|
||||
TDA18273_Top_Adapt_TOP_ADAPT34, /* AGC3 TOP Adapt Algorithm */ \
|
||||
TDA18273_AGC3_Adapt_TOP_1_Step, /* AGC3 Adapt */ \
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_4_5_min_3_5, /* AGC Overload TOP */ \
|
||||
TDA18273_TH_AGC_Adapt34_5dB, /* Adapt TOP 34 Gain Threshold */ \
|
||||
TDA18273_RF_Atten_3dB_Disabled, /* RF Atten 3dB */ \
|
||||
TDA18273_IF_Output_Level_0_7Vpp_min_9_21dB, /* IF Output Level */ \
|
||||
TDA18273_S2D_Gain_6dB, /* S2D Gain */ \
|
||||
TDA18273_Negative_Modulation_Enabled, /* Negative Modulation */ \
|
||||
TDA18273_AGCK_Steps_0_2dB, /* Step */ \
|
||||
TDA18273_AGCK_Time_Constant_1_STEP_EACH_VSYNC_RISING_EDGE, /* AGCK Time Constant */ \
|
||||
TDA18273_AGC5_HPF_Enabled, /* AGC5 HPF */ \
|
||||
TDA18273_Pulse_Shaper_Disable_Enabled, /* Pulse Shaper Disable */ \
|
||||
TDA18273_VHF_III_Mode_Disabled, /* VHF III Mode */ \
|
||||
TDA18273_LO_CP_Current_Enabled /* LO CP Current */ \
|
||||
}
|
||||
|
||||
#define TDA18273_INSTANCE_CUSTOM_STD_ANALOG_GH \
|
||||
{ /* PAL G/H */ \
|
||||
6750000, /* IF */ \
|
||||
2750000, /* CF_Offset */ \
|
||||
TDA18273_LPF_8MHz, /* LPF */ \
|
||||
TDA18273_LPFOffset_0pc, /* LPF_Offset */ \
|
||||
TDA18273_DC_Notch_IF_PPF_Disabled, /* DC notch IF PPF */ \
|
||||
TDA18273_IF_HPF_Disabled, /* Hi Pass */ \
|
||||
TDA18273_IF_Notch_Disabled, /* IF notch */ \
|
||||
TDA18273_IFnotchToRSSI_Enabled, /* IF notch To RSSI */ \
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d95_u89dBuV, /* AGC1 TOP I2C DN/UP */ \
|
||||
TDA18273_AGC1_Adapt_TOP_DN_UP_1_Step, /* AGC1 Adapt TOP DN/UP */ \
|
||||
TDA18273_AGC1_Mode_LNA_ADAPT_TOP_ADAPT, /* AGC1 mode */ \
|
||||
TDA18273_Range_LNA_Adapt_20dB_11dB, /* Range LNA Adapt */ \
|
||||
TDA18273_LNA_Adapt_RFAGC_Gv_Threshold_18_25dB, /* LNA Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC1_Top_Adapt_RFAGC_Gv_Threshold_15_25dB, /* AGC1 TOP Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC2_TOP_DN_UP_d90_u84dBuV, /* AGC2 TOP DN/UP */ \
|
||||
TDA18273_AGC3_TOP_I2C_96dBuV, /* AGC3 TOP I2C */ \
|
||||
TDA18273_AGC4_TOP_DN_UP_d105_u100dBuV, /* AGC4 TOP DN/UP */ \
|
||||
TDA18273_AGC5_TOP_DN_UP_d105_u100dBuV, /* AGC5 TOP DN/UP */ \
|
||||
TDA18273_Top_Adapt_TOP_ADAPT34, /* AGC3 TOP Adapt Algorithm */ \
|
||||
TDA18273_AGC3_Adapt_TOP_1_Step, /* AGC3 Adapt */ \
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_4_5_min_3_5, /* AGC Overload TOP */ \
|
||||
TDA18273_TH_AGC_Adapt34_5dB, /* Adapt TOP 34 Gain Threshold */ \
|
||||
TDA18273_RF_Atten_3dB_Disabled, /* RF Atten 3dB */ \
|
||||
TDA18273_IF_Output_Level_0_7Vpp_min_9_21dB, /* IF Output Level */ \
|
||||
TDA18273_S2D_Gain_6dB, /* S2D Gain */ \
|
||||
TDA18273_Negative_Modulation_Enabled, /* Negative Modulation */ \
|
||||
TDA18273_AGCK_Steps_0_2dB, /* Step */ \
|
||||
TDA18273_AGCK_Time_Constant_1_STEP_EACH_VSYNC_RISING_EDGE, /* AGCK Time Constant */ \
|
||||
TDA18273_AGC5_HPF_Enabled, /* AGC5 HPF */ \
|
||||
TDA18273_Pulse_Shaper_Disable_Enabled, /* Pulse Shaper Disable */ \
|
||||
TDA18273_VHF_III_Mode_Disabled, /* VHF III Mode */ \
|
||||
TDA18273_LO_CP_Current_Enabled /* LO CP Current */ \
|
||||
}
|
||||
|
||||
#define TDA18273_INSTANCE_CUSTOM_STD_ANALOG_I \
|
||||
{ /* PAL I */ \
|
||||
7250000, /* IF */ \
|
||||
2750000, /* CF_Offset */ \
|
||||
TDA18273_LPF_8MHz, /* LPF */ \
|
||||
TDA18273_LPFOffset_0pc, /* LPF_Offset */ \
|
||||
TDA18273_DC_Notch_IF_PPF_Disabled, /* DC notch IF PPF */ \
|
||||
TDA18273_IF_HPF_Disabled, /* Hi Pass */ \
|
||||
TDA18273_IF_Notch_Disabled, /* IF notch */ \
|
||||
TDA18273_IFnotchToRSSI_Enabled, /* IF notch To RSSI */ \
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d95_u89dBuV, /* AGC1 TOP I2C DN/UP */ \
|
||||
TDA18273_AGC1_Adapt_TOP_DN_UP_1_Step, /* AGC1 Adapt TOP DN/UP */ \
|
||||
TDA18273_AGC1_Mode_LNA_ADAPT_TOP_ADAPT, /* AGC1 mode */ \
|
||||
TDA18273_Range_LNA_Adapt_20dB_11dB, /* Range LNA Adapt */ \
|
||||
TDA18273_LNA_Adapt_RFAGC_Gv_Threshold_18_25dB, /* LNA Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC1_Top_Adapt_RFAGC_Gv_Threshold_15_25dB, /* AGC1 TOP Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC2_TOP_DN_UP_d90_u84dBuV, /* AGC2 TOP DN/UP */ \
|
||||
TDA18273_AGC3_TOP_I2C_96dBuV, /* AGC3 TOP I2C */ \
|
||||
TDA18273_AGC4_TOP_DN_UP_d105_u100dBuV, /* AGC4 TOP DN/UP */ \
|
||||
TDA18273_AGC5_TOP_DN_UP_d105_u100dBuV, /* AGC5 TOP DN/UP */ \
|
||||
TDA18273_Top_Adapt_TOP_ADAPT34, /* AGC3 TOP Adapt Algorithm */ \
|
||||
TDA18273_AGC3_Adapt_TOP_1_Step, /* AGC3 Adapt */ \
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_4_5_min_3_5, /* AGC Overload TOP */ \
|
||||
TDA18273_TH_AGC_Adapt34_5dB, /* Adapt TOP 34 Gain Threshold */ \
|
||||
TDA18273_RF_Atten_3dB_Disabled, /* RF Atten 3dB */ \
|
||||
TDA18273_IF_Output_Level_0_7Vpp_min_9_21dB, /* IF Output Level */ \
|
||||
TDA18273_S2D_Gain_6dB, /* S2D Gain */ \
|
||||
TDA18273_Negative_Modulation_Enabled, /* Negative Modulation */ \
|
||||
TDA18273_AGCK_Steps_0_2dB, /* Step */ \
|
||||
TDA18273_AGCK_Time_Constant_1_STEP_EACH_VSYNC_RISING_EDGE, /* AGCK Time Constant */ \
|
||||
TDA18273_AGC5_HPF_Enabled, /* AGC5 HPF */ \
|
||||
TDA18273_Pulse_Shaper_Disable_Enabled, /* Pulse Shaper Disable */ \
|
||||
TDA18273_VHF_III_Mode_Disabled, /* VHF III Mode */ \
|
||||
TDA18273_LO_CP_Current_Enabled /* LO CP Current */ \
|
||||
}
|
||||
|
||||
#define TDA18273_INSTANCE_CUSTOM_STD_ANALOG_DK \
|
||||
{ /* SECAM D/K */ \
|
||||
6850000, /* IF */ \
|
||||
2750000, /* CF_Offset */ \
|
||||
TDA18273_LPF_8MHz, /* LPF */ \
|
||||
TDA18273_LPFOffset_0pc, /* LPF_Offset */ \
|
||||
TDA18273_DC_Notch_IF_PPF_Disabled, /* DC notch IF PPF */ \
|
||||
TDA18273_IF_HPF_Disabled, /* Hi Pass */ \
|
||||
TDA18273_IF_Notch_Enabled, /* IF notch */ \
|
||||
TDA18273_IFnotchToRSSI_Disabled, /* IF notch To RSSI */ \
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d95_u89dBuV, /* AGC1 TOP I2C DN/UP */ \
|
||||
TDA18273_AGC1_Adapt_TOP_DN_UP_1_Step, /* AGC1 Adapt TOP DN/UP */ \
|
||||
TDA18273_AGC1_Mode_LNA_ADAPT_TOP_ADAPT, /* AGC1 mode */ \
|
||||
TDA18273_Range_LNA_Adapt_20dB_11dB, /* Range LNA Adapt */ \
|
||||
TDA18273_LNA_Adapt_RFAGC_Gv_Threshold_18_25dB, /* LNA Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC1_Top_Adapt_RFAGC_Gv_Threshold_15_25dB, /* AGC1 TOP Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC2_TOP_DN_UP_d90_u84dBuV, /* AGC2 TOP DN/UP */ \
|
||||
TDA18273_AGC3_TOP_I2C_96dBuV, /* AGC3 TOP I2C */ \
|
||||
TDA18273_AGC4_TOP_DN_UP_d105_u100dBuV, /* AGC4 TOP DN/UP */ \
|
||||
TDA18273_AGC5_TOP_DN_UP_d105_u100dBuV, /* AGC5 TOP DN/UP */ \
|
||||
TDA18273_Top_Adapt_TOP_ADAPT34, /* AGC3 TOP Adapt Algorithm */ \
|
||||
TDA18273_AGC3_Adapt_TOP_1_Step, /* AGC3 Adapt */ \
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_4_5_min_3_5, /* AGC Overload TOP */ \
|
||||
TDA18273_TH_AGC_Adapt34_5dB, /* Adapt TOP 34 Gain Threshold */ \
|
||||
TDA18273_RF_Atten_3dB_Disabled, /* RF Atten 3dB */ \
|
||||
TDA18273_IF_Output_Level_0_7Vpp_min_9_21dB, /* IF Output Level */ \
|
||||
TDA18273_S2D_Gain_6dB, /* S2D Gain */ \
|
||||
TDA18273_Negative_Modulation_Enabled, /* Negative Modulation */ \
|
||||
TDA18273_AGCK_Steps_0_2dB, /* Step */ \
|
||||
TDA18273_AGCK_Time_Constant_1_STEP_EACH_VSYNC_RISING_EDGE, /* AGCK Time Constant */ \
|
||||
TDA18273_AGC5_HPF_Enabled, /* AGC5 HPF */ \
|
||||
TDA18273_Pulse_Shaper_Disable_Enabled, /* Pulse Shaper Disable */ \
|
||||
TDA18273_VHF_III_Mode_Disabled, /* VHF III Mode */ \
|
||||
TDA18273_LO_CP_Current_Enabled /* LO CP Current */ \
|
||||
}
|
||||
|
||||
#define TDA18273_INSTANCE_CUSTOM_STD_ANALOG_L \
|
||||
{ /* SECAM L */ \
|
||||
6750000, /* IF */ \
|
||||
2750000, /* CF_Offset */ \
|
||||
TDA18273_LPF_8MHz, /* LPF */ \
|
||||
TDA18273_LPFOffset_0pc, /* LPF_Offset */ \
|
||||
TDA18273_DC_Notch_IF_PPF_Disabled, /* DC notch IF PPF */ \
|
||||
TDA18273_IF_HPF_Disabled, /* Hi Pass */ \
|
||||
TDA18273_IF_Notch_Enabled, /* IF notch */ \
|
||||
TDA18273_IFnotchToRSSI_Disabled, /* IF notch To RSSI */ \
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d95_u89dBuV, /* AGC1 TOP I2C DN/UP */ \
|
||||
TDA18273_AGC1_Adapt_TOP_DN_UP_1_Step, /* AGC1 Adapt TOP DN/UP */ \
|
||||
TDA18273_AGC1_Mode_LNA_ADAPT_TOP_ADAPT, /* AGC1 mode */ \
|
||||
TDA18273_Range_LNA_Adapt_20dB_11dB, /* Range LNA Adapt */ \
|
||||
TDA18273_LNA_Adapt_RFAGC_Gv_Threshold_18_25dB, /* LNA Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC1_Top_Adapt_RFAGC_Gv_Threshold_15_25dB, /* AGC1 TOP Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC2_TOP_DN_UP_d90_u84dBuV, /* AGC2 TOP DN/UP */ \
|
||||
TDA18273_AGC3_TOP_I2C_96dBuV, /* AGC3 TOP I2C */ \
|
||||
TDA18273_AGC4_TOP_DN_UP_d105_u100dBuV, /* AGC4 TOP DN/UP */ \
|
||||
TDA18273_AGC5_TOP_DN_UP_d105_u100dBuV, /* AGC5 TOP DN/UP */ \
|
||||
TDA18273_Top_Adapt_TOP_ADAPT34, /* AGC3 TOP Adapt Algorithm */ \
|
||||
TDA18273_AGC3_Adapt_TOP_1_Step, /* AGC3 Adapt */ \
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_6_min_9, /* AGC Overload TOP */ \
|
||||
TDA18273_TH_AGC_Adapt34_5dB, /* Adapt TOP 34 Gain Threshold */ \
|
||||
TDA18273_RF_Atten_3dB_Disabled, /* RF Atten 3dB */ \
|
||||
TDA18273_IF_Output_Level_0_7Vpp_min_9_21dB, /* IF Output Level */ \
|
||||
TDA18273_S2D_Gain_6dB, /* S2D Gain */ \
|
||||
TDA18273_Negative_Modulation_Disabled, /* Negative Modulation */ \
|
||||
TDA18273_AGCK_Steps_0_2dB, /* Step */ \
|
||||
TDA18273_AGCK_Time_Constant_1_STEP_EACH_VSYNC_RISING_EDGE, /* AGCK Time Constant */ \
|
||||
TDA18273_AGC5_HPF_Enabled, /* AGC5 HPF */ \
|
||||
TDA18273_Pulse_Shaper_Disable_Enabled, /* Pulse Shaper Disable */ \
|
||||
TDA18273_VHF_III_Mode_Disabled, /* VHF III Mode */ \
|
||||
TDA18273_LO_CP_Current_Enabled /* LO CP Current */ \
|
||||
}
|
||||
|
||||
#define TDA18273_INSTANCE_CUSTOM_STD_ANALOG_LL \
|
||||
{ /* SECAM L' */ \
|
||||
1250000, /* IF */ \
|
||||
-2750000, /* CF_Offset */ \
|
||||
TDA18273_LPF_8MHz, /* LPF */ \
|
||||
TDA18273_LPFOffset_0pc, /* LPF_Offset */ \
|
||||
TDA18273_DC_Notch_IF_PPF_Disabled, /* DC notch IF PPF */ \
|
||||
TDA18273_IF_HPF_Disabled, /* Hi Pass */ \
|
||||
TDA18273_IF_Notch_Disabled, /* IF notch */ \
|
||||
TDA18273_IFnotchToRSSI_Enabled, /* IF notch To RSSI */ \
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d95_u89dBuV, /* AGC1 TOP I2C DN/UP */ \
|
||||
TDA18273_AGC1_Adapt_TOP_DN_UP_1_Step, /* AGC1 Adapt TOP DN/UP */ \
|
||||
TDA18273_AGC1_Mode_LNA_ADAPT_TOP_ADAPT, /* AGC1 mode */ \
|
||||
TDA18273_Range_LNA_Adapt_20dB_11dB, /* Range LNA Adapt */ \
|
||||
TDA18273_LNA_Adapt_RFAGC_Gv_Threshold_18_25dB, /* LNA Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC1_Top_Adapt_RFAGC_Gv_Threshold_15_25dB, /* AGC1 TOP Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC2_TOP_DN_UP_d90_u84dBuV, /* AGC2 TOP DN/UP */ \
|
||||
TDA18273_AGC3_TOP_I2C_96dBuV, /* AGC3 TOP I2C */ \
|
||||
TDA18273_AGC4_TOP_DN_UP_d105_u100dBuV, /* AGC4 TOP DN/UP */ \
|
||||
TDA18273_AGC5_TOP_DN_UP_d105_u100dBuV, /* AGC5 TOP DN/UP */ \
|
||||
TDA18273_Top_Adapt_TOP_ADAPT34, /* AGC3 TOP Adapt Algorithm */ \
|
||||
TDA18273_AGC3_Adapt_TOP_1_Step, /* AGC3 Adapt */ \
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_6_min_9, /* AGC Overload TOP */ \
|
||||
TDA18273_TH_AGC_Adapt34_5dB, /* Adapt TOP 34 Gain Threshold */ \
|
||||
TDA18273_RF_Atten_3dB_Disabled, /* RF Atten 3dB */ \
|
||||
TDA18273_IF_Output_Level_0_7Vpp_min_9_21dB, /* IF Output Level */ \
|
||||
TDA18273_S2D_Gain_6dB, /* S2D Gain */ \
|
||||
TDA18273_Negative_Modulation_Disabled, /* Negative Modulation */ \
|
||||
TDA18273_AGCK_Steps_0_2dB, /* Step */ \
|
||||
TDA18273_AGCK_Time_Constant_1_STEP_EACH_VSYNC_RISING_EDGE, /* AGCK Time Constant */ \
|
||||
TDA18273_AGC5_HPF_Disabled, /* AGC5 HPF */ \
|
||||
TDA18273_Pulse_Shaper_Disable_Enabled, /* Pulse Shaper Disable */ \
|
||||
TDA18273_VHF_III_Mode_Disabled, /* VHF III Mode */ \
|
||||
TDA18273_LO_CP_Current_Enabled /* LO CP Current */ \
|
||||
}
|
||||
|
||||
#define TDA18273_INSTANCE_CUSTOM_STD_ANALOG_BLIND_SCANNING \
|
||||
{ /* Blind Scanning copy of PAL-I */ \
|
||||
7250000, /* IF */ \
|
||||
2750000, /* CF_Offset */ \
|
||||
TDA18273_LPF_8MHz, /* LPF */ \
|
||||
TDA18273_LPFOffset_0pc, /* LPF_Offset */ \
|
||||
TDA18273_DC_Notch_IF_PPF_Disabled, /* DC notch IF PPF */ \
|
||||
TDA18273_IF_HPF_Disabled, /* Hi Pass */ \
|
||||
TDA18273_IF_Notch_Disabled, /* IF notch */ \
|
||||
TDA18273_IFnotchToRSSI_Enabled, /* IF notch To RSSI */ \
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d95_u89dBuV, /* AGC1 TOP I2C DN/UP */ \
|
||||
TDA18273_AGC1_Adapt_TOP_DN_UP_1_Step, /* AGC1 Adapt TOP DN/UP */ \
|
||||
TDA18273_AGC1_Mode_LNA_ADAPT_TOP_ADAPT, /* AGC1 mode */ \
|
||||
TDA18273_Range_LNA_Adapt_20dB_11dB, /* Range LNA Adapt */ \
|
||||
TDA18273_LNA_Adapt_RFAGC_Gv_Threshold_18_25dB, /* LNA Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC1_Top_Adapt_RFAGC_Gv_Threshold_15_25dB, /* AGC1 TOP Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC2_TOP_DN_UP_d90_u84dBuV, /* AGC2 TOP DN/UP */ \
|
||||
TDA18273_AGC3_TOP_I2C_96dBuV, /* AGC3 TOP I2C */ \
|
||||
TDA18273_AGC4_TOP_DN_UP_d105_u100dBuV, /* AGC4 TOP DN/UP */ \
|
||||
TDA18273_AGC5_TOP_DN_UP_d105_u100dBuV, /* AGC5 TOP DN/UP */ \
|
||||
TDA18273_Top_Adapt_TOP_ADAPT34, /* AGC3 TOP Adapt Algorithm */ \
|
||||
TDA18273_AGC3_Adapt_TOP_1_Step, /* AGC3 Adapt */ \
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_4_5_min_3_5, /* AGC Overload TOP */ \
|
||||
TDA18273_TH_AGC_Adapt34_5dB, /* Adapt TOP 34 Gain Threshold */ \
|
||||
TDA18273_RF_Atten_3dB_Disabled, /* RF Atten 3dB */ \
|
||||
TDA18273_IF_Output_Level_0_7Vpp_min_9_21dB, /* IF Output Level */ \
|
||||
TDA18273_S2D_Gain_6dB, /* S2D Gain */ \
|
||||
TDA18273_Negative_Modulation_Disabled, /* Negative Modulation */ \
|
||||
TDA18273_AGCK_Steps_0_2dB, /* Step */ \
|
||||
TDA18273_AGCK_Time_Constant_1_STEP_EACH_VSYNC_RISING_EDGE, /* AGCK Time Constant */ \
|
||||
TDA18273_AGC5_HPF_Enabled, /* AGC5 HPF */ \
|
||||
TDA18273_Pulse_Shaper_Disable_Enabled, /* Pulse Shaper Disable */ \
|
||||
TDA18273_VHF_III_Mode_Disabled, /* VHF III Mode */ \
|
||||
TDA18273_LO_CP_Current_Enabled /* LO CP Current */ \
|
||||
}
|
||||
|
||||
#define TDA18273_INSTANCE_CUSTOM_STD_SCANXPRESS \
|
||||
{ /* ScanXpress */ \
|
||||
5000000, /* IF */ \
|
||||
0, /* CF_Offset */ \
|
||||
TDA18273_LPF_9MHz, /* LPF */ \
|
||||
TDA18273_LPFOffset_min_8pc, /* LPF_Offset */ \
|
||||
TDA18273_DC_Notch_IF_PPF_Enabled, /* DC notch IF PPF */ \
|
||||
TDA18273_IF_HPF_0_85MHz, /* Hi Pass */ \
|
||||
TDA18273_IF_Notch_Disabled, /* IF notch */ \
|
||||
TDA18273_IFnotchToRSSI_Enabled, /* IF notch To RSSI */ \
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d95_u89wdBuV, /* AGC1 TOP I2C DN/UP */ \
|
||||
TDA18273_AGC1_Adapt_TOP_DN_UP_0_Step, /* AGC1 Adapt TOP DN/UP */ \
|
||||
TDA18273_AGC1_Mode_LNA_ADAPT_WIDE, /* AGC1 mode */ \
|
||||
TDA18273_Range_LNA_Adapt_20dB_11dB, /* Range LNA Adapt */ \
|
||||
TDA18273_LNA_Adapt_RFAGC_Gv_Threshold_18_25dB, /* LNA Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC1_Top_Adapt_RFAGC_Gv_Threshold_16_75dB, /* AGC1 TOP Adapt RFAGC Gv Threshold */ \
|
||||
TDA18273_AGC2_TOP_DN_UP_d90_u84dBuV, /* AGC2 TOP DN/UP */ \
|
||||
TDA18273_AGC3_TOP_I2C_100dBuV, /* AGC3 TOP I2C */ \
|
||||
TDA18273_AGC4_TOP_DN_UP_d110_u105dBuV, /* AGC4 TOP DN/UP */ \
|
||||
TDA18273_AGC5_TOP_DN_UP_d110_u105dBuV, /* AGC5 TOP DN/UP */ \
|
||||
TDA18273_Top_Adapt_NO_TOP_ADAPT, /* AGC3 TOP Adapt Algorithm */ \
|
||||
TDA18273_AGC3_Adapt_TOP_0_Step, /* AGC3 Adapt */ \
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_4_5_min_3_5, /* AGC Overload TOP */ \
|
||||
TDA18273_TH_AGC_Adapt34_5dB, /* Adapt TOP 34 Gain Threshold */ \
|
||||
TDA18273_RF_Atten_3dB_Disabled, /* RF Atten 3dB */ \
|
||||
TDA18273_IF_Output_Level_1Vpp_min_6_24dB, /* IF Output Level */ \
|
||||
TDA18273_S2D_Gain_6dB, /* S2D Gain */ \
|
||||
TDA18273_Negative_Modulation_Disabled, /* Negative Modulation */ \
|
||||
TDA18273_AGCK_Steps_0_2dB, /* Step */ \
|
||||
TDA18273_AGCK_Time_Constant_32_768ms, /* AGCK Time Constant */ \
|
||||
TDA18273_AGC5_HPF_Disabled, /* AGC5 HPF */ \
|
||||
TDA18273_Pulse_Shaper_Disable_Enabled, /* Pulse Shaper Disable */ \
|
||||
TDA18273_VHF_III_Mode_Disabled, /* VHF III Mode */ \
|
||||
TDA18273_LO_CP_Current_Enabled /* LO CP Current */ \
|
||||
}
|
||||
|
||||
/* Default configuration */
|
||||
#define TDA18273_INSTANCE_CUSTOM_CURPOWERSTATE_DEF tmPowerMax
|
||||
#define TDA18273_INSTANCE_CUSTOM_CURLLPOWERSTATE_DEF TDA18273_PowerMax
|
||||
#define TDA18273_INSTANCE_CUSTOM_RF_DEF 0
|
||||
#define TDA18273_INSTANCE_CUSTOM_PROG_RF_DEF 0
|
||||
#define TDA18273_INSTANCE_CUSTOM_IF_DEF 0
|
||||
#define TDA18273_INSTANCE_CUSTOM_STANDARDMODE_DEF TDA18273_StandardMode_Max
|
||||
|
||||
/* Power settings */
|
||||
#define TDA18273_INSTANCE_CUSTOM_POWER_DEF \
|
||||
TDA18273_INSTANCE_CUSTOM_CURPOWERSTATE_DEF, /* curPowerState */ \
|
||||
TDA18273_INSTANCE_CUSTOM_CURLLPOWERSTATE_DEF, /* curLLPowerState */ \
|
||||
{ /* mapLLPowerState */ \
|
||||
TDA18273_PowerNormalMode, /* tmPowerOn (D0) */ \
|
||||
TDA18273_PowerStandbyWithXtalOn, /* tmPowerStandby (D1) */ \
|
||||
TDA18273_PowerStandbyWithXtalOn, /* tmPowerSuspend (D2) */ \
|
||||
TDA18273_PowerStandbyWithXtalOn /* tmPowerOff (D3) */ \
|
||||
}
|
||||
|
||||
/* Standard Presets Aggregation: */
|
||||
#define TDA18273_INSTANCE_CUSTOM_STD_DEF \
|
||||
{ \
|
||||
TDA18273_INSTANCE_CUSTOM_STD_QAM_6MHZ, \
|
||||
TDA18273_INSTANCE_CUSTOM_STD_QAM_8MHZ, \
|
||||
TDA18273_INSTANCE_CUSTOM_STD_ATSC_6MHZ, \
|
||||
TDA18273_INSTANCE_CUSTOM_STD_ISDBT_6MHZ, \
|
||||
TDA18273_INSTANCE_CUSTOM_STD_DVBT_1_7MHZ, \
|
||||
TDA18273_INSTANCE_CUSTOM_STD_DVBT_6MHZ, \
|
||||
TDA18273_INSTANCE_CUSTOM_STD_DVBT_7MHZ, \
|
||||
TDA18273_INSTANCE_CUSTOM_STD_DVBT_8MHZ, \
|
||||
TDA18273_INSTANCE_CUSTOM_STD_DVBT_10MHZ, \
|
||||
TDA18273_INSTANCE_CUSTOM_STD_DMBT_8MHZ, \
|
||||
TDA18273_INSTANCE_CUSTOM_STD_ANALOG_FM_RADIO, \
|
||||
TDA18273_INSTANCE_CUSTOM_STD_ANALOG_MN, \
|
||||
TDA18273_INSTANCE_CUSTOM_STD_ANALOG_B, \
|
||||
TDA18273_INSTANCE_CUSTOM_STD_ANALOG_GH, \
|
||||
TDA18273_INSTANCE_CUSTOM_STD_ANALOG_I, \
|
||||
TDA18273_INSTANCE_CUSTOM_STD_ANALOG_DK, \
|
||||
TDA18273_INSTANCE_CUSTOM_STD_ANALOG_L, \
|
||||
TDA18273_INSTANCE_CUSTOM_STD_ANALOG_LL, \
|
||||
TDA18273_INSTANCE_CUSTOM_STD_ANALOG_BLIND_SCANNING, \
|
||||
TDA18273_INSTANCE_CUSTOM_STD_SCANXPRESS \
|
||||
}
|
||||
|
||||
#define TDA18273_INSTANCE_CUSTOM_REGMAP_DEF \
|
||||
{ \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 \
|
||||
}
|
||||
|
||||
#define TDA18273_INSTANCE_CUSTOM_MASTER_0 \
|
||||
TDA18273_INSTANCE_CUSTOM_POWER_DEF, \
|
||||
TDA18273_INSTANCE_CUSTOM_RF_DEF, /* uRF */ \
|
||||
TDA18273_INSTANCE_CUSTOM_PROG_RF_DEF, /* uProgRF */ \
|
||||
TDA18273_INSTANCE_CUSTOM_IF_DEF, /* uIF */ \
|
||||
TDA18273_INSTANCE_CUSTOM_STANDARDMODE_DEF, /* StandardMode */ \
|
||||
Null, /* pStandard */ \
|
||||
False, /* PLD_CC_algorithm */ \
|
||||
False, /* bBufferMode */ \
|
||||
True, /* bIRQWait */ \
|
||||
True, /* bIRQWaitHwInit */ \
|
||||
True, /* bOverridePLL */ \
|
||||
TDA18273_HwState_InitNotDone, /* eHwState */ \
|
||||
TDA18273_INSTANCE_CUSTOM_STD_DEF, \
|
||||
TDA18273_INSTANCE_CUSTOM_REGMAP_DEF
|
||||
|
||||
#define TDA18273_INSTANCE_CUSTOM_MASTER_1 \
|
||||
TDA18273_INSTANCE_CUSTOM_POWER_DEF, \
|
||||
TDA18273_INSTANCE_CUSTOM_RF_DEF, /* uRF */ \
|
||||
TDA18273_INSTANCE_CUSTOM_PROG_RF_DEF, /* uProgRF */ \
|
||||
TDA18273_INSTANCE_CUSTOM_IF_DEF, /* uIF */ \
|
||||
TDA18273_INSTANCE_CUSTOM_STANDARDMODE_DEF, /* StandardMode */ \
|
||||
Null, /* pStandard */ \
|
||||
False, /* PLD_CC_algorithm */ \
|
||||
True, /* bBufferMode */ \
|
||||
True, /* bIRQWait */ \
|
||||
True, /* bIRQWaitHwInit */ \
|
||||
True, /* bOverridePLL */ \
|
||||
TDA18273_HwState_InitNotDone, /* eHwState */ \
|
||||
TDA18273_INSTANCE_CUSTOM_STD_DEF, \
|
||||
TDA18273_INSTANCE_CUSTOM_REGMAP_DEF
|
||||
|
||||
|
||||
/* Custom Driver Instance Parameters: (Path 0) */
|
||||
#define TDA18273_INSTANCE_CUSTOM_0 \
|
||||
TDA18273_INSTANCE_CUSTOM_MASTER_0
|
||||
|
||||
/* Custom Driver Instance Parameters: (Path 1) */
|
||||
#define TDA18273_INSTANCE_CUSTOM_1 \
|
||||
TDA18273_INSTANCE_CUSTOM_MASTER_1
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TDA18273_INSTANCE_CUSTOM_H */
|
||||
|
||||
|
||||
@@ -0,0 +1,581 @@
|
||||
/*
|
||||
Copyright (C) 2010 NXP B.V., All Rights Reserved.
|
||||
This source code and any compilation or derivative thereof is the proprietary
|
||||
information of NXP B.V. and is confidential in nature. Under no circumstances
|
||||
is this software to be exposed to or placed under an Open Source License of
|
||||
any type without the expressed written permission of NXP B.V.
|
||||
*
|
||||
* \file tmbslTDA18273_Local.h
|
||||
*
|
||||
* %version: 11 %
|
||||
*
|
||||
* \date %modify_time%
|
||||
*
|
||||
* \author David LEGENDRE
|
||||
* Michael VANNIER
|
||||
* Christophe CAZETTES
|
||||
*
|
||||
* \brief Describe briefly the purpose of this file.
|
||||
*
|
||||
* REFERENCE DOCUMENTS :
|
||||
* TDA18273_Driver_User_Guide.pdf
|
||||
*
|
||||
* TVFE SW Arch V4 Template: Author Christophe CAZETTES
|
||||
*
|
||||
* \section info Change Information
|
||||
*
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
#ifndef _TMBSL_TDA18273_LOCAL_H
|
||||
#define _TMBSL_TDA18273_LOCAL_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*============================================================================*/
|
||||
/* Types and defines: */
|
||||
/*============================================================================*/
|
||||
|
||||
/* Maximum number of systems supported by driver */
|
||||
#define TDA18273_MAX_UNITS 2
|
||||
|
||||
/* Driver version definition */
|
||||
#define TDA18273_COMP_NUM 2 /* Major protocol change - Specification change required */
|
||||
#define TDA18273_MAJOR_VER 17 /* Minor protocol change - Specification change required */
|
||||
#define TDA18273_MINOR_VER 0 /* Software update - No protocol change - No specification change required */
|
||||
|
||||
/* Instance macros */
|
||||
#define P_OBJ_VALID (pObj != Null)
|
||||
|
||||
/* I/O Functions macros */
|
||||
#define P_SIO pObj->sIo
|
||||
#define P_SIO_READ P_SIO.Read
|
||||
#define P_SIO_WRITE P_SIO.Write
|
||||
#define P_SIO_READ_VALID (P_OBJ_VALID && (P_SIO_READ != Null))
|
||||
#define P_SIO_WRITE_VALID (P_OBJ_VALID && (P_SIO_WRITE != Null))
|
||||
|
||||
/* Time Functions macros */
|
||||
#define P_STIME pObj->sTime
|
||||
#define P_STIME_WAIT P_STIME.Wait
|
||||
#define P_STIME_WAIT_VALID (P_OBJ_VALID && (P_STIME_WAIT != Null))
|
||||
|
||||
/* Debug Functions macros */
|
||||
#define P_SDEBUG pObj->sDebug
|
||||
#define P_DBGPRINTEx P_SDEBUG.Print
|
||||
#define P_DBGPRINTVALID (P_OBJ_VALID && (P_DBGPRINTEx != Null))
|
||||
|
||||
/* Mutex Functions macros */
|
||||
#define P_SMUTEX pObj->sMutex
|
||||
#ifdef _TVFE_SW_ARCH_V4
|
||||
#define P_SMUTEX_OPEN P_SMUTEX.Open
|
||||
#define P_SMUTEX_CLOSE P_SMUTEX.Close
|
||||
#else
|
||||
#define P_SMUTEX_OPEN P_SMUTEX.Init
|
||||
#define P_SMUTEX_CLOSE P_SMUTEX.DeInit
|
||||
#endif
|
||||
#define P_SMUTEX_ACQUIRE P_SMUTEX.Acquire
|
||||
#define P_SMUTEX_RELEASE P_SMUTEX.Release
|
||||
|
||||
#define P_SMUTEX_OPEN_VALID (P_OBJ_VALID && (P_SMUTEX_OPEN != Null))
|
||||
#define P_SMUTEX_CLOSE_VALID (P_OBJ_VALID && (P_SMUTEX_CLOSE != Null))
|
||||
#define P_SMUTEX_ACQUIRE_VALID (P_OBJ_VALID && (P_SMUTEX_ACQUIRE != Null))
|
||||
#define P_SMUTEX_RELEASE_VALID (P_OBJ_VALID && (P_SMUTEX_RELEASE != Null))
|
||||
|
||||
/* Driver Mutex macros */
|
||||
#define TDA18273_MUTEX_TIMEOUT (5000)
|
||||
#define P_MUTEX pObj->pMutex
|
||||
#define P_MUTEX_VALID (P_MUTEX != Null)
|
||||
|
||||
#ifdef _TVFE_IMPLEMENT_MUTEX
|
||||
#define _MUTEX_ACQUIRE(_NAME) \
|
||||
if(err == TM_OK) \
|
||||
{ \
|
||||
/* Try to acquire driver mutex */ \
|
||||
err = i##_NAME##_MutexAcquire(pObj, _NAME##_MUTEX_TIMEOUT); \
|
||||
} \
|
||||
if(err == TM_OK) \
|
||||
{
|
||||
|
||||
#define _MUTEX_RELEASE(_NAME) \
|
||||
(void)i##_NAME##_MutexRelease(pObj); \
|
||||
}
|
||||
#else
|
||||
#define _MUTEX_ACQUIRE(_NAME) \
|
||||
if(err == TM_OK) \
|
||||
{
|
||||
|
||||
#define _MUTEX_RELEASE(_NAME) \
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/* TDA18273 Driver State Machine */
|
||||
typedef enum _TDA18273HwState_t {
|
||||
TDA18273_HwState_Unknown = 0, /* Hw State Unknown */
|
||||
TDA18273_HwState_InitNotDone, /* Hw Init Not Done */
|
||||
TDA18273_HwState_InitPending, /* Hw Init Pending */
|
||||
TDA18273_HwState_InitDone, /* Hw Init Done */
|
||||
TDA18273_HwState_SetStdDone, /* Set Standard Done */
|
||||
TDA18273_HwState_SetRFDone, /* Set RF Done */
|
||||
TDA18273_HwState_SetFineRFDone, /* Set Fine RF Done */
|
||||
TDA18273_HwState_Max
|
||||
} TDA18273HwState_t, *pTDA18273HwState_t;
|
||||
|
||||
typedef enum _TDA18273HwStateCaller_t {
|
||||
TDA18273_HwStateCaller_Unknown = 0, /* Caller Unknown */
|
||||
TDA18273_HwStateCaller_SetPower, /* Caller SetPowerState */
|
||||
TDA18273_HwStateCaller_HwInit, /* Caller HwInit */
|
||||
TDA18273_HwStateCaller_SetStd, /* Caller SetStandardMode */
|
||||
TDA18273_HwStateCaller_SetRF, /* Caller SetRF */
|
||||
TDA18273_HwStateCaller_SetFineRF, /* Caller SetFineRF */
|
||||
TDA18273_HwStateCaller_GetRSSI, /* Caller GetRSSI */
|
||||
TDA18273_HwStateCaller_SetRawRF, /* Caller SetRawRF */
|
||||
TDA18273_HwStateCaller_Max
|
||||
} TDA18273HwStateCaller_t, *pTDA18273HwStateCaller_t;
|
||||
|
||||
/* TDA18273 specific powerstate bits: */
|
||||
typedef enum _TDA18273SM_Reg_t {
|
||||
TDA18273_SM_NONE = 0x00, /* No SM bit to set */
|
||||
TDA18273_SM_XT = 0x01, /* SM_XT bit to set */
|
||||
TDA18273_SM = 0x02 /* SM bit to set */
|
||||
} TDA18273SM_Reg_t, *pTDA18273SM_Reg_t;
|
||||
|
||||
/* TDA18273 specific MSM: */
|
||||
typedef enum _TDA18273MSM_t {
|
||||
TDA18273_MSM_Calc_PLL = 0x01, /* Calc_PLL bit */
|
||||
TDA18273_MSM_RC_Cal = 0x02, /* RC_Cal bit */
|
||||
TDA18273_MSM_IR_CAL_Wanted = 0x04, /* IR_CAL_Wanted bit */
|
||||
TDA18273_MSM_IR_Cal_Image = 0x08, /* IR_Cal_Image bit */
|
||||
TDA18273_MSM_IR_CAL_Loop = 0x10, /* IR_CAL_Loop bit */
|
||||
TDA18273_MSM_RF_CAL = 0x20, /* RF_CAL bit */
|
||||
TDA18273_MSM_RF_CAL_AV = 0x40, /* RF_CAL_AV bit */
|
||||
TDA18273_MSM_RSSI_Meas = 0x80, /* RSSI_Meas bit */
|
||||
/* Performs all CALs except IR_CAL */
|
||||
TDA18273_MSM_HwInit = TDA18273_MSM_Calc_PLL\
|
||||
|TDA18273_MSM_RC_Cal\
|
||||
|TDA18273_MSM_RF_CAL,
|
||||
/* Performs all IR_CAL */
|
||||
TDA18273_MSM_IrCal = TDA18273_MSM_IR_Cal_Image\
|
||||
|TDA18273_MSM_IR_CAL_Loop,
|
||||
TDA18273_MSM_SetRF = TDA18273_MSM_Calc_PLL\
|
||||
|TDA18273_MSM_RF_CAL_AV,
|
||||
TDA18273_MSM_GetPowerLevel = TDA18273_MSM_RSSI_Meas
|
||||
} TDA18273MSM_t, *pTDA18273MSM_t;
|
||||
|
||||
/* TDA18273 Standard settings: */
|
||||
typedef enum _TDA18273LPF_t {
|
||||
TDA18273_LPF_6MHz = 0, /* 6MHz LPFc */
|
||||
TDA18273_LPF_7MHz, /* 7MHz LPFc */
|
||||
TDA18273_LPF_8MHz, /* 8MHz LPFc */
|
||||
TDA18273_LPF_9MHz, /* 9MHz LPFc */
|
||||
TDA18273_LPF_1_5MHz, /* 1.5MHz LPFc */
|
||||
TDA18273_LPF_Max
|
||||
} TDA18273LPF_t, *pTDA18273LPF_t;
|
||||
|
||||
typedef enum _TDA18273LPFOffset_t {
|
||||
TDA18273_LPFOffset_0pc = 0, /* LPFc 0% */
|
||||
TDA18273_LPFOffset_min_4pc, /* LPFc -4% */
|
||||
TDA18273_LPFOffset_min_8pc, /* LPFc -8% */
|
||||
TDA18273_LPFOffset_min_12pc, /* LPFc -12% */
|
||||
TDA18273_LPFOffset_Max
|
||||
} TDA18273LPFOffset_t, *pTDA18273LPFOffset_t;
|
||||
|
||||
typedef enum TDA18273DC_Notch_IF_PPF_t {
|
||||
TDA18273_DC_Notch_IF_PPF_Disabled = 0, /* IF Notch Disabled */
|
||||
TDA18273_DC_Notch_IF_PPF_Enabled, /* IF Notch Enabled */
|
||||
TDA18273_DC_Notch_IF_PPF_Max
|
||||
} TDA18273DC_Notch_IF_PPF_t, *pTDA18273DC_Notch_IF_PPF_t;
|
||||
|
||||
typedef enum _TDA18273IF_HPF_t {
|
||||
TDA18273_IF_HPF_Disabled = 0, /* IF HPF disabled */
|
||||
TDA18273_IF_HPF_0_4MHz, /* IF HPF 0.4MHz */
|
||||
TDA18273_IF_HPF_0_85MHz, /* IF HPF 0.85MHz */
|
||||
TDA18273_IF_HPF_1MHz, /* IF HPF 1MHz */
|
||||
TDA18273_IF_HPF_1_5MHz, /* IF HPF 1.5MHz */
|
||||
TDA18273_IF_HPF_Max
|
||||
} TDA18273IF_HPF_t, *pTDA18273IF_HPF_t;
|
||||
|
||||
typedef enum _TDA18273IF_Notch_t {
|
||||
TDA18273_IF_Notch_Disabled = 0, /* IF Notch Disabled */
|
||||
TDA18273_IF_Notch_Enabled, /* IF Notch Enabled */
|
||||
TDA18273_IF_Notch_Max
|
||||
} TDA18273IF_Notch_t, *pTDA18273IF_Notch_t;
|
||||
|
||||
typedef enum _TDA18273IFnotchToRSSI_t {
|
||||
TDA18273_IFnotchToRSSI_Disabled = 0, /* IFnotchToRSSI Disabled */
|
||||
TDA18273_IFnotchToRSSI_Enabled, /* IFnotchToRSSI Enabled */
|
||||
TDA18273_IFnotchToRSSI_Max
|
||||
} TDA18273IFnotchToRSSI_t, *pTDA18273IFnotchToRSSI_t;
|
||||
|
||||
typedef enum _TDA18273AGC1_TOP_I2C_DN_UP_t {
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d88_u82dBuV = 0, /* AGC1 TOP I2C DN/UP down 88 up 82 dBuV */
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d90_u84dBuV, /* AGC1 TOP I2C DN/UP down 90 up 84 dBuV */
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d95_u89wdBuV, /* AGC1 TOP I2C DN/UP down 95 up 89 dBuV */
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d93_u87dBuV, /* AGC1 TOP I2C DN/UP down 93 up 87 dBuV */
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d95_u89dBuV, /* AGC1 TOP I2C DN/UP down 95 up 89 dBuV */
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d99_u84dBuV, /* AGC1 TOP I2C DN/UP down 99 up 84 dBuV */
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d100_u82dBuV, /* AGC1 TOP I2C DN/UP down 100 up 82 dBuV */
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d100_u94bisdBuV, /* AGC1 TOP I2C DN/UP down 100 up 94 dBuV */
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d102_u82dBuV, /* AGC1 TOP I2C DN/UP down 102 up 82 dBuV */
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d102_u84dBuV, /* AGC1 TOP I2C DN/UP down 102 up 84 dBuV */
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_d100_u94dBuV, /* AGC1 TOP I2C DN/UP down 100 up 94 dBuV */
|
||||
TDA18273_AGC1_TOP_I2C_DN_UP_Max
|
||||
} TDA18273AGC1_TOP_I2C_DN_UP_t, *pTDA18273AGC1_TOP_I2C_DN_UP_t;
|
||||
|
||||
typedef enum _TDA18273AGC1_Adapt_TOP_DN_UP_t {
|
||||
TDA18273_AGC1_Adapt_TOP_DN_UP_0_Step = 0, /* AGC1 Adapt TOP DN/UP 0 Step */
|
||||
TDA18273_AGC1_Adapt_TOP_DN_UP_1_Step, /* AGC1 Adapt TOP DN/UP 1 Step */
|
||||
TDA18273_AGC1_Adapt_TOP_DN_UP_2_Step, /* AGC1 Adapt TOP DN/UP 2 Step */
|
||||
TDA18273_AGC1_Adapt_TOP_DN_UP_3_Step, /* AGC1 Adapt TOP DN/UP 3 Step */
|
||||
TDA18273_AGC1_Adapt_TOP_DN_UP_Max
|
||||
} TDA18273AGC1_Adapt_TOP_DN_UP_t, *pTDA18273AGC1_Adapt_TOP_DN_UP_t;
|
||||
|
||||
typedef enum _TDA18273AGC1_Mode_t {
|
||||
TDA18273_AGC1_Mode_No_Mode = 0, /* AGC1 Mode */
|
||||
TDA18273_AGC1_Mode_TOP_ADAPT, /* AGC1 Mode: TOP ADAPT */
|
||||
TDA18273_AGC1_Mode_LNA_ADAPT, /* AGC1 Mode: LNA ADAPT */
|
||||
TDA18273_AGC1_Mode_LNA_ADAPT_TOP_ADAPT, /* AGC1 Mode: LNA ADAPT & TOP ADAPT */
|
||||
TDA18273_AGC1_Mode_FREEZE, /* AGC1 Mode: FREEZE */
|
||||
TDA18273_AGC1_Mode_WIDE, /* AGC1 Mode: WIDE */
|
||||
TDA18273_AGC1_Mode_LNA_ADAPT_FREEZE, /* AGC1 Mode: LNA ADAPT & FREEZE */
|
||||
TDA18273_AGC1_Mode_LNA_ADAPT_WIDE, /* AGC1 Mode: LNA ADAPT & WIDE */
|
||||
TDA18273_AGC1_Mode_Max
|
||||
} TDA18273AGC1_Mode_t, *pTDA18273AGC1_Mode_t;
|
||||
|
||||
typedef enum _TDA18273Range_LNA_Adapt_t {
|
||||
TDA18273_Range_LNA_Adapt_20dB_8dB = 0, /* Range LNA Adapt 20dB-8dB */
|
||||
TDA18273_Range_LNA_Adapt_20dB_11dB, /* Range LNA Adapt 20dB-11dB */
|
||||
TDA18273_Range_LNA_Adapt_Max
|
||||
} TDA18273Range_LNA_Adapt_t, *pTDA18273Range_LNA_Adapt_t;
|
||||
|
||||
typedef enum _TDA18273LNA_Adapt_RFAGC_Gv_Threshold {
|
||||
TDA18273_LNA_Adapt_RFAGC_Gv_Threshold_18_25dB = 0, /* 18.25dB */
|
||||
TDA18273_LNA_Adapt_RFAGC_Gv_Threshold_16_75dB, /* 16.75dB */
|
||||
TDA18273_LNA_Adapt_RFAGC_Gv_Threshold_15_25dB, /* 15.25dB */
|
||||
TDA18273_LNA_Adapt_RFAGC_Gv_Threshold_13_75dB, /* 13.75dB */
|
||||
TDA18273_LNA_Adapt_RFAGC_Gv_Threshold_Max
|
||||
} TDA18273LNA_Adapt_RFAGC_Gv_Threshold, *pTDA18273LNA_Adapt_RFAGC_Gv_Threshold;
|
||||
|
||||
typedef enum _TDA18273AGC1_Top_Adapt_RFAGC_Gv_Threshold {
|
||||
TDA18273_AGC1_Top_Adapt_RFAGC_Gv_Threshold_16_75dB = 0, /* 16.75dB */
|
||||
TDA18273_AGC1_Top_Adapt_RFAGC_Gv_Threshold_15_25dB, /* 15.25dB */
|
||||
TDA18273_AGC1_Top_Adapt_RFAGC_Gv_Threshold_13_75dB, /* 13.75dB */
|
||||
TDA18273_AGC1_Top_Adapt_RFAGC_Gv_Threshold_12_25dB, /* 12.25dB */
|
||||
TDA18273_AGC1_Top_Adapt_RFAGC_Gv_Threshold_Max
|
||||
} TDA18273AGC1_Top_Adapt_RFAGC_Gv_Threshold, *pTDA18273AGC1_Top_Adapt_RFAGC_Gv_Threshold;
|
||||
|
||||
typedef enum _TDA18273AGC2_TOP_DN_UP_t {
|
||||
TDA18273_AGC2_TOP_DN_UP_d88_u81dBuV = 0, /* AGC2 TOP DN/UP down 88 up 81 dBuV */
|
||||
TDA18273_AGC2_TOP_DN_UP_d90_u83dBuV, /* AGC2 TOP DN/UP down 90 up 83 dBuV */
|
||||
TDA18273_AGC2_TOP_DN_UP_d93_u86dBuV, /* AGC2 TOP DN/UP down 93 up 86 dBuV */
|
||||
TDA18273_AGC2_TOP_DN_UP_d95_u88dBuV, /* AGC2 TOP DN/UP down 95 up 88 dBuV */
|
||||
TDA18273_AGC2_TOP_DN_UP_d88_u82dBuV, /* AGC2 TOP DN/UP down 88 up 82 dBuV */
|
||||
TDA18273_AGC2_TOP_DN_UP_d90_u84dBuV, /* AGC2 TOP DN/UP down 90 up 84 dBuV */
|
||||
TDA18273_AGC2_TOP_DN_UP_d93_u87dBuV, /* AGC2 TOP DN/UP down 93 up 87 dBuV */
|
||||
TDA18273_AGC2_TOP_DN_UP_d95_u89dBuV, /* AGC2 TOP DN/UP down 95 up 89 dBuV */
|
||||
TDA18273_AGC2_TOP_DN_UP_Max
|
||||
} TDA18273AGC2_TOP_DN_UP_t, *pTDA18273AGC2_TOP_DN_UP_t;
|
||||
|
||||
typedef enum _TDA18273AGC3_TOP_I2C_t {
|
||||
TDA18273_AGC3_TOP_I2C_94dBuV = 0, /* AGC3 TOP I2C 94 dBuV */
|
||||
TDA18273_AGC3_TOP_I2C_96dBuV, /* AGC3 TOP I2C 96 dBuV */
|
||||
TDA18273_AGC3_TOP_I2C_98dBuV, /* AGC3 TOP I2C 98 dBuV */
|
||||
TDA18273_AGC3_TOP_I2C_100dBuV, /* AGC3 TOP I2C 100 dBuV */
|
||||
TDA18273_AGC3_TOP_I2C_102dBuV, /* AGC3 TOP I2C 102 dBuV */
|
||||
TDA18273_AGC3_TOP_I2C_104dBuV, /* AGC3 TOP I2C 104 dBuV */
|
||||
TDA18273_AGC3_TOP_I2C_106dBuV, /* AGC3 TOP I2C 106 dBuV */
|
||||
TDA18273_AGC3_TOP_I2C_107dBuV, /* AGC3 TOP I2C 107 dBuV */
|
||||
TDA18273_AGC3_TOP_I2C_Max
|
||||
} TDA18273AGC3_TOP_I2C_t, *pTDA18273AGC3_TOP_I2C_t;
|
||||
|
||||
#define TDA18273_AGC3_TOP_I2C_FREQ_LIM 291000000
|
||||
|
||||
typedef enum _TDA18273AGC4_TOP_DN_UP_t {
|
||||
TDA18273_AGC4_TOP_DN_UP_d105_u99dBuV = 0, /* AGC4 TOP DN/UP down 105 up 99 dBuV */
|
||||
TDA18273_AGC4_TOP_DN_UP_d105_u100dBuV, /* AGC4 TOP DN/UP down 105 up 100 dBuV */
|
||||
TDA18273_AGC4_TOP_DN_UP_d105_u101dBuV, /* AGC4 TOP DN/UP down 105 up 101 dBuV */
|
||||
TDA18273_AGC4_TOP_DN_UP_d107_u101dBuV, /* AGC4 TOP DN/UP down 107 up 101 dBuV */
|
||||
TDA18273_AGC4_TOP_DN_UP_d107_u102dBuV, /* AGC4 TOP DN/UP down 107 up 102 dBuV */
|
||||
TDA18273_AGC4_TOP_DN_UP_d107_u103dBuV, /* AGC4 TOP DN/UP down 107 up 103 dBuV */
|
||||
TDA18273_AGC4_TOP_DN_UP_d108_u102dBuV, /* AGC4 TOP DN/UP down 108 up 102 dBuV */
|
||||
TDA18273_AGC4_TOP_DN_UP_d109_u103dBuV, /* AGC4 TOP DN/UP down 109 up 103 dBuV */
|
||||
TDA18273_AGC4_TOP_DN_UP_d109_u104dBuV, /* AGC4 TOP DN/UP down 109 up 104 dBuV */
|
||||
TDA18273_AGC4_TOP_DN_UP_d109_u105dBuV, /* AGC4 TOP DN/UP down 109 up 105 dBuV */
|
||||
TDA18273_AGC4_TOP_DN_UP_d110_u104dBuV, /* AGC4 TOP DN/UP down 110 up 104 dBuV */
|
||||
TDA18273_AGC4_TOP_DN_UP_d110_u105dBuV, /* AGC4 TOP DN/UP down 110 up 105 dBuV */
|
||||
TDA18273_AGC4_TOP_DN_UP_d110_u106dBuV, /* AGC4 TOP DN/UP down 110 up 106 dBuV */
|
||||
TDA18273_AGC4_TOP_DN_UP_d112_u106dBuV, /* AGC4 TOP DN/UP down 112 up 106 dBuV */
|
||||
TDA18273_AGC4_TOP_DN_UP_d112_u107dBuV, /* AGC4 TOP DN/UP down 112 up 107 dBuV */
|
||||
TDA18273_AGC4_TOP_DN_UP_d112_u108dBuV, /* AGC4 TOP DN/UP down 112 up 108 dBuV */
|
||||
TDA18273_AGC4_TOP_DN_UP_Max
|
||||
} TDA18273AGC4_TOP_DN_UP_t, *pTDA18273AGC4_TOP_DN_UP_t;
|
||||
|
||||
typedef enum _TDA18273AGC5_TOP_DN_UP_t {
|
||||
TDA18273_AGC5_TOP_DN_UP_d105_u99dBuV = 0, /* AGC5 TOP DN/UP down 105 up 99 dBuV */
|
||||
TDA18273_AGC5_TOP_DN_UP_d105_u100dBuV, /* AGC5 TOP DN/UP down 105 up 100 dBuV */
|
||||
TDA18273_AGC5_TOP_DN_UP_d105_u101dBuV, /* AGC5 TOP DN/UP down 105 up 101 dBuV */
|
||||
TDA18273_AGC5_TOP_DN_UP_d107_u101dBuV, /* AGC5 TOP DN/UP down 107 up 101 dBuV */
|
||||
TDA18273_AGC5_TOP_DN_UP_d107_u102dBuV, /* AGC5 TOP DN/UP down 107 up 102 dBuV */
|
||||
TDA18273_AGC5_TOP_DN_UP_d107_u103dBuV, /* AGC5 TOP DN/UP down 107 up 103 dBuV */
|
||||
TDA18273_AGC5_TOP_DN_UP_d108_u102dBuV, /* AGC5 TOP DN/UP down 108 up 102 dBuV */
|
||||
TDA18273_AGC5_TOP_DN_UP_d109_u103dBuV, /* AGC5 TOP DN/UP down 109 up 103 dBuV */
|
||||
TDA18273_AGC5_TOP_DN_UP_d109_u104dBuV, /* AGC5 TOP DN/UP down 109 up 104 dBuV */
|
||||
TDA18273_AGC5_TOP_DN_UP_d109_u105dBuV, /* AGC5 TOP DN/UP down 109 up 105 dBuV */
|
||||
TDA18273_AGC5_TOP_DN_UP_d110_u104dBuV, /* AGC5 TOP DN/UP down 108 up 104 dBuV */
|
||||
TDA18273_AGC5_TOP_DN_UP_d110_u105dBuV, /* AGC5 TOP DN/UP down 108 up 105 dBuV */
|
||||
TDA18273_AGC5_TOP_DN_UP_d110_u106dBuV, /* AGC5 TOP DN/UP down 108 up 106 dBuV */
|
||||
TDA18273_AGC5_TOP_DN_UP_d112_u106dBuV, /* AGC5 TOP DN/UP down 108 up 106 dBuV */
|
||||
TDA18273_AGC5_TOP_DN_UP_d112_u107dBuV, /* AGC5 TOP DN/UP down 108 up 107 dBuV */
|
||||
TDA18273_AGC5_TOP_DN_UP_d112_u108dBuV, /* AGC5 TOP DN/UP down 108 up 108 dBuV */
|
||||
TDA18273_AGC5_TOP_DN_UP_Max
|
||||
} TDA18273AGC5_TOP_DN_UP_t, *pTDA18273AGC5_TOP_DN_UP_t;
|
||||
|
||||
typedef enum _TDA18273AGC3_Top_Adapt_Algorithm {
|
||||
TDA18273_Top_Adapt_NO_TOP_ADAPT = 0, /* NO TOP ADAPT */
|
||||
TDA18273_Top_Adapt_TOP_ADAPT35, /* TOP ADAPT35 */
|
||||
TDA18273_Top_Adapt_TOP_ADAPT34, /* TOP ADAPT34 */
|
||||
TDA18273_Top_Adapt_Max
|
||||
} TDA18273AGC3_Top_Adapt_Algorithm, *pTDA18273AGC3_Top_Adapt_Algorithm;
|
||||
|
||||
typedef enum _TDA18273AGC3_Adapt_TOP_t {
|
||||
TDA18273_AGC3_Adapt_TOP_0_Step = 0, /* same level as AGC3 TOP */
|
||||
TDA18273_AGC3_Adapt_TOP_1_Step, /* 1 level below AGC3 TOP */
|
||||
TDA18273_AGC3_Adapt_TOP_2_Step, /* 2 level below AGC3 TOP */
|
||||
TDA18273_AGC3_Adapt_TOP_3_Step /* 3 level below AGC3 TOP */
|
||||
} TDA18273AGC3_Adapt_TOP_t, *pTDA18273AGC3_Adapt_TOP_t;
|
||||
|
||||
#define TDA18273_AGC3_ADAPT_TOP_FREQ_LIM 291000000
|
||||
|
||||
typedef enum _TDA18273AGC_Overload_TOP_t {
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_3_5_min_3_5 = 0, /* +9/+3.5/-3.5 */
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_4_5_min_4_5, /* +9/+4.5/-4.5 */
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_4_5_min_3_5, /* +9/+4.5/-3.5 */
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_6_min_4_5, /* +9/+6/-4.5 */
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_6_min_6, /* +9/+6/-6 */
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_6_min_9, /* +9/+6/-9 */
|
||||
TDA18273_AGC_Overload_TOP_plus_9_plus_7_5_min_9, /* +9/+7.5/-9 */
|
||||
TDA18273_AGC_Overload_TOP_plus_12_plus_7_5_min_9 /* +12/+7.5/-9 */
|
||||
} TDA18273AGC_Overload_TOP_t, *pTDA18273AGC_Overload_TOP_t;
|
||||
|
||||
typedef enum _TDA18273TH_AGC_Adapt34_t {
|
||||
TDA18273_TH_AGC_Adapt34_2dB = 0, /* Adapt TOP 34 Gain Threshold 2dB */
|
||||
TDA18273_TH_AGC_Adapt34_5dB /* Adapt TOP 34 Gain Threshold 5dB */
|
||||
} TDA18273TH_AGC_Adapt34_t, *pTDA18273TH_AGC_Adapt34_t;
|
||||
|
||||
typedef enum _TDA18273RF_Atten_3dB_t {
|
||||
TDA18273_RF_Atten_3dB_Disabled = 0, /* RF_Atten_3dB Disabled */
|
||||
TDA18273_RF_Atten_3dB_Enabled, /* RF_Atten_3dB Enabled */
|
||||
TDA18273_RF_Atten_3dB_Max
|
||||
} TDA18273RF_Atten_3dB_t, *pTDA18273RF_Atten_3dB_t;
|
||||
|
||||
typedef enum _TDA18273IF_Output_Level_t {
|
||||
TDA18273_IF_Output_Level_2Vpp_0_30dB = 0, /* 2Vpp 0 - 30dB */
|
||||
TDA18273_IF_Output_Level_1_25Vpp_min_4_26dB, /* 1.25Vpp -4 - 26dB */
|
||||
TDA18273_IF_Output_Level_1Vpp_min_6_24dB, /* 1Vpp -6 - 24dB */
|
||||
TDA18273_IF_Output_Level_0_8Vpp_min_8_22dB, /* 0.8Vpp -8 - 22dB */
|
||||
TDA18273_IF_Output_Level_0_85Vpp_min_7_5_22_5dB, /* 0.85Vpp -7.5 - 22.5dB */
|
||||
TDA18273_IF_Output_Level_0_7Vpp_min_9_21dB, /* 0.7Vpp -9 - 21dB */
|
||||
TDA18273_IF_Output_Level_0_6Vpp_min_10_3_19_7dB, /* 0.6Vpp -10.3 - 19.7dB */
|
||||
TDA18273_IF_Output_Level_0_5Vpp_min_12_18dB, /* 0.5Vpp -12 - 18dB */
|
||||
TDA18273_IF_Output_Level_Max
|
||||
} TDA18273IF_Output_Level_t, *pTDA18273IF_Output_Level_t;
|
||||
|
||||
typedef enum _TDA18273S2D_Gain_t {
|
||||
TDA18273_S2D_Gain_3dB = 0, /* 3dB */
|
||||
TDA18273_S2D_Gain_6dB, /* 6dB */
|
||||
TDA18273_S2D_Gain_9dB, /* 9dB */
|
||||
TDA18273_S2D_Gain_Max
|
||||
} TDA18273S2D_Gain_t, *pTDA18273S2D_Gain_t;
|
||||
|
||||
typedef enum _TDA18273Negative_Modulation_t {
|
||||
TDA18273_Negative_Modulation_Disabled = 0,
|
||||
TDA18273_Negative_Modulation_Enabled,
|
||||
TDA18273_Negative_Modulation_Max
|
||||
} TDA18273Negative_Modulation_t, *pTDA18273Negative_Modulation_t;
|
||||
|
||||
typedef enum _TDA18273AGCK_Steps_t {
|
||||
TDA18273_AGCK_Steps_0_2dB = 0, /* 0.2dB */
|
||||
TDA18273_AGCK_Steps_0_4dB, /* 0.4dB */
|
||||
TDA18273_AGCK_Steps_0_6dB, /* 0.6dB */
|
||||
TDA18273_AGCK_Steps_0_8dB, /* 0.8dB */
|
||||
TDA18273_AGCK_Steps_Max
|
||||
} TDA18273AGCK_Steps_t, *pTDA18273AGCK_Steps_t;
|
||||
|
||||
typedef enum _TDA18273AGCK_Time_Constant_t {
|
||||
TDA18273_AGCK_Time_Constant_1_STEP_EACH_VSYNC_RISING_EDGE = 0, /* 1 Step Each VSYNC Rising Edge */
|
||||
TDA18273_AGCK_Time_Constant_0_512ms, /* 0.512ms */
|
||||
TDA18273_AGCK_Time_Constant_8_192ms, /* 8.192ms */
|
||||
TDA18273_AGCK_Time_Constant_32_768ms, /* 32.768ms */
|
||||
TDA18273_AGCK_Time_Constant_Max
|
||||
} TDA18273AGCK_Time_Constant_t, *pTDA18273AGCK_Time_Constant_t;
|
||||
|
||||
typedef enum _TDA18273AGC5_HPF_t {
|
||||
TDA18273_AGC5_HPF_Disabled = 0, /* AGC5 HPF Disabled */
|
||||
TDA18273_AGC5_HPF_Enabled, /* AGC5 HPF Enabled */
|
||||
TDA18273_AGC5_HPF_Max
|
||||
} TDA18273AGC5_HPF_t, *pTDA18273AGC5_HPF_t;
|
||||
|
||||
typedef enum _TDA18273Pulse_Shaper_Disable_t {
|
||||
TDA18273_Pulse_Shaper_Disable_Disabled = 0,
|
||||
TDA18273_Pulse_Shaper_Disable_Enabled,
|
||||
TDA18273_Pulse_Shaper_Disable_Max
|
||||
} TDA18273Pulse_Shaper_Disable_t, *pTDA18273Pulse_Shaper_Disable_t;
|
||||
|
||||
typedef enum _TDA18273VHF_III_Mode_t {
|
||||
TDA18273_VHF_III_Mode_Disabled = 0, /* VHF_III_Mode Disabled */
|
||||
TDA18273_VHF_III_Mode_Enabled, /* VHF_III_Mode Enabled */
|
||||
TDA18273_VHF_III_Mode_Max
|
||||
} TDA18273VHF_III_Mode_t, *pTDA18273VHF_III_Mode_t;
|
||||
|
||||
typedef enum _TDA18273LO_CP_Current_t {
|
||||
TDA18273_LO_CP_Current_Disabled = 0, /* LO CP Current Disabled */
|
||||
TDA18273_LO_CP_Current_Enabled, /* LO CP Current Enabled */
|
||||
TDA18273_LO_CP_Current_Max
|
||||
} TDA18273LO_CP_Current_t, *pTDA18273LO_CP_Current_t;
|
||||
|
||||
typedef struct _TDA18273StdCoefficients
|
||||
{
|
||||
/****************************************************************/
|
||||
/* IF Settings */
|
||||
/****************************************************************/
|
||||
UInt32 IF; /* IF Frequency */
|
||||
Int32 CF_Offset;
|
||||
|
||||
/****************************************************************/
|
||||
/* IF SELECTIVITY Settings */
|
||||
/****************************************************************/
|
||||
TDA18273LPF_t LPF; /* LPF Cut off */
|
||||
TDA18273LPFOffset_t LPF_Offset; /* LPF offset */
|
||||
TDA18273DC_Notch_IF_PPF_t DC_Notch_IF_PPF; /* DC notch IF PPF */
|
||||
TDA18273IF_HPF_t IF_HPF; /* Hi Pass */
|
||||
TDA18273IF_Notch_t IF_Notch; /* IF notch */
|
||||
TDA18273IFnotchToRSSI_t IFnotchToRSSI; /* IFnotchToRSSI */
|
||||
|
||||
/****************************************************************/
|
||||
/* AGC TOP Settings */
|
||||
/****************************************************************/
|
||||
TDA18273AGC1_TOP_I2C_DN_UP_t AGC1_TOP_I2C_DN_UP; /* AGC1 TOP I2C DN/UP */
|
||||
TDA18273AGC1_Adapt_TOP_DN_UP_t AGC1_Adapt_TOP_DN_UP; /* AGC1 Adapt TOP DN/UP */
|
||||
TDA18273AGC1_Mode_t AGC1_Mode; /* AGC1 mode */
|
||||
TDA18273Range_LNA_Adapt_t Range_LNA_Adapt; /* Range_LNA_Adapt */
|
||||
TDA18273LNA_Adapt_RFAGC_Gv_Threshold LNA_Adapt_RFAGC_Gv_Threshold; /* LNA_Adapt_RFAGC_Gv_Threshold */
|
||||
TDA18273AGC1_Top_Adapt_RFAGC_Gv_Threshold AGC1_Top_Adapt_RFAGC_Gv_Threshold; /* AGC1_Top_Adapt_RFAGC_Gv_Threshold */
|
||||
TDA18273AGC2_TOP_DN_UP_t AGC2_TOP_DN_UP; /* AGC2 TOP DN/UP */
|
||||
TDA18273AGC3_TOP_I2C_t AGC3_TOP_I2C; /* AGC3 TOP I2C */
|
||||
TDA18273AGC4_TOP_DN_UP_t AGC4_TOP_DN_UP; /* AGC4 TOP DN/UP */
|
||||
TDA18273AGC5_TOP_DN_UP_t AGC5_TOP_DN_UP; /* AGC5 TOP DN/UP */
|
||||
TDA18273AGC3_Top_Adapt_Algorithm AGC3_Top_Adapt_Algorithm; /* AGC3_Top_Adapt_Algorithm */
|
||||
TDA18273AGC3_Adapt_TOP_t AGC3_Adapt_TOP; /* AGC3 Adapt TOP */
|
||||
TDA18273AGC_Overload_TOP_t AGC_Overload_TOP; /* AGC Overload TOP */
|
||||
TDA18273TH_AGC_Adapt34_t TH_AGC_Adapt34; /* Adapt TOP 34 Gain Threshold */
|
||||
TDA18273RF_Atten_3dB_t RF_Atten_3dB; /* RF atten 3dB */
|
||||
TDA18273IF_Output_Level_t IF_Output_Level; /* IF Output Level */
|
||||
TDA18273S2D_Gain_t S2D_Gain; /* S2D gain */
|
||||
TDA18273Negative_Modulation_t Negative_Modulation; /* Negative modulation */
|
||||
|
||||
/****************************************************************/
|
||||
/* GSK Settings */
|
||||
/****************************************************************/
|
||||
TDA18273AGCK_Steps_t AGCK_Steps; /* Step */
|
||||
TDA18273AGCK_Time_Constant_t AGCK_Time_Constant; /* AGCK Time Constant */
|
||||
TDA18273AGC5_HPF_t AGC5_HPF; /* AGC5 HPF */
|
||||
TDA18273Pulse_Shaper_Disable_t Pulse_Shaper_Disable; /* Pulse Shaper Disable */
|
||||
|
||||
/****************************************************************/
|
||||
/* H3H5 Settings */
|
||||
/****************************************************************/
|
||||
TDA18273VHF_III_Mode_t VHF_III_Mode; /* VHF_III_Mode */
|
||||
|
||||
/****************************************************************/
|
||||
/* PLL Settings */
|
||||
/****************************************************************/
|
||||
TDA18273LO_CP_Current_t LO_CP_Current; /* LO_CP_Current */
|
||||
} TDA18273StdCoefficients, *pTDA18273StdCoefficients;
|
||||
|
||||
|
||||
|
||||
typedef struct _TDA18273Object_t
|
||||
{
|
||||
tmUnitSelect_t tUnit;
|
||||
tmUnitSelect_t tUnitW;
|
||||
ptmbslFrontEndMutexHandle pMutex;
|
||||
Bool init;
|
||||
tmbslFrontEndIoFunc_t sIo;
|
||||
tmbslFrontEndTimeFunc_t sTime;
|
||||
tmbslFrontEndDebugFunc_t sDebug;
|
||||
tmbslFrontEndMutexFunc_t sMutex;
|
||||
/* Device specific part: */
|
||||
tmPowerState_t curPowerState;
|
||||
TDA18273PowerState_t curLLPowerState;
|
||||
TDA18273PowerState_t mapLLPowerState[tmPowerMax];
|
||||
UInt32 uRF;
|
||||
UInt32 uProgRF;
|
||||
UInt32 uIF;
|
||||
TDA18273StandardMode_t StandardMode;
|
||||
pTDA18273StdCoefficients pStandard;
|
||||
Bool PLD_CC_algorithm; /* Enables or not the PLD CC algorithm : PLD immunity against adjacents */
|
||||
Bool bBufferMode; /* Indicates if bufferMode is enabled on the tuner */
|
||||
Bool bIRQWait; /* Indicates if wait is performed inside the driver */
|
||||
Bool bIRQWaitHwInit; /* Indicates if wait is performed in HwInit */
|
||||
Bool bOverridePLL; /* Indicates if PLL is put into manual mode during setRF */
|
||||
TDA18273HwState_t eHwState; /* Indicates HwInit state */
|
||||
TDA18273StdCoefficients Std_Array[TDA18273_StandardMode_Max-1];
|
||||
#ifdef _TDA18273_REGMAP_BITFIELD_DEFINED
|
||||
TDA18273_Reg_Map_t RegMap;
|
||||
#else
|
||||
UInt8 RegMap[TDA18273_REG_MAP_NB_BYTES];
|
||||
#endif
|
||||
} TDA18273Object_t, *pTDA18273Object_t, **ppTDA18273Object_t;
|
||||
|
||||
|
||||
/*============================================================================*/
|
||||
/* Internal Prototypes: */
|
||||
/*============================================================================*/
|
||||
|
||||
extern tmErrorCode_t
|
||||
iTDA18273_CheckCalcPLL(pTDA18273Object_t pObj);
|
||||
|
||||
extern tmErrorCode_t
|
||||
iTDA18273_CheckHwState(pTDA18273Object_t pObj, TDA18273HwStateCaller_t caller);
|
||||
|
||||
extern tmErrorCode_t
|
||||
iTDA18273_SetRF(pTDA18273Object_t pObj);
|
||||
|
||||
extern tmErrorCode_t
|
||||
iTDA18273_SetRF_Freq(pTDA18273Object_t pObj, UInt32 uRF);
|
||||
|
||||
extern tmErrorCode_t
|
||||
iTDA18273_SetMSM(pTDA18273Object_t pObj, UInt8 uValue, Bool bLaunch);
|
||||
|
||||
extern tmErrorCode_t
|
||||
iTDA18273_WaitIRQ(pTDA18273Object_t pObj, UInt32 timeOut, UInt32 waitStep, UInt8 irqStatus);
|
||||
|
||||
extern tmErrorCode_t
|
||||
iTDA18273_Write(pTDA18273Object_t pObj, const TDA18273_BitField_t* pBitField, UInt8 uData, eBusAccess_t eBusAccess);
|
||||
|
||||
extern tmErrorCode_t
|
||||
iTDA18273_Read(pTDA18273Object_t pObj, const TDA18273_BitField_t* pBitField, UInt8* puData, eBusAccess_t eBusAccess);
|
||||
|
||||
extern tmErrorCode_t
|
||||
iTDA18273_WriteRegMap(pTDA18273Object_t pObj, UInt8 uAddress, UInt32 uWriteLen);
|
||||
|
||||
extern tmErrorCode_t
|
||||
iTDA18273_ReadRegMap(pTDA18273Object_t pObj, UInt8 uAddress, UInt32 uReadLen);
|
||||
|
||||
extern tmErrorCode_t
|
||||
iTDA18273_Wait(pTDA18273Object_t pObj, UInt32 Time);
|
||||
|
||||
#ifdef _TVFE_IMPLEMENT_MUTEX
|
||||
extern tmErrorCode_t iTDA18273_MutexAcquire(pTDA18273Object_t pObj, UInt32 timeOut);
|
||||
extern tmErrorCode_t iTDA18273_MutexRelease(pTDA18273Object_t pObj);
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TMBSL_TDA18273_LOCAL_H */
|
||||
|
||||
@@ -0,0 +1,820 @@
|
||||
/*
|
||||
Copyright (C) 2010 NXP B.V., All Rights Reserved.
|
||||
This source code and any compilation or derivative thereof is the proprietary
|
||||
information of NXP B.V. and is confidential in nature. Under no circumstances
|
||||
is this software to be exposed to or placed under an Open Source License of
|
||||
any type without the expressed written permission of NXP B.V.
|
||||
*
|
||||
* \file tmbslTDA18273_RegDef.c
|
||||
*
|
||||
* %version: 3 %
|
||||
*
|
||||
* \date %modify_time%
|
||||
*
|
||||
* \author Christophe CAZETTES
|
||||
*
|
||||
* \brief Describe briefly the purpose of this file.
|
||||
*
|
||||
* REFERENCE DOCUMENTS :
|
||||
* TDA18273_Driver_User_Guide.pdf
|
||||
*
|
||||
* TVFE SW Arch V4 Template: Author Christophe CAZETTES
|
||||
*
|
||||
* \section info Change Information
|
||||
*
|
||||
*/
|
||||
|
||||
/* File generated automatically from register description file */
|
||||
|
||||
#include "../inc/config.h"
|
||||
|
||||
#if USE_TUNER
|
||||
/*============================================================================*/
|
||||
/* Standard include files: */
|
||||
/*============================================================================*/
|
||||
#include "tmNxTypes.h"
|
||||
#include "tmNxCompId.h"
|
||||
#include "tmFrontEnd.h"
|
||||
#include "tmbslFrontEndTypes.h"
|
||||
|
||||
/*============================================================================*/
|
||||
/* Project include files: */
|
||||
/*============================================================================*/
|
||||
#include "tmbslTDA18273.h"
|
||||
#include "tmbslTDA18273_RegDef.h"
|
||||
|
||||
/*============================================================================*/
|
||||
/* Global data: */
|
||||
/*============================================================================*/
|
||||
|
||||
/* TDA18273 Register ID_byte_1 0x00 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_ID_byte_1 = { 0x00, 0x00, 0x08, 0x00 };
|
||||
/* MS bit(s): Indicate if Device is a Master or a Slave */
|
||||
/* 1 => Master device */
|
||||
/* 0 => Slave device */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_ID_byte_1__MS = { 0x00, 0x07, 0x01, 0x00 };
|
||||
/* Ident_1 bit(s): MSB of device identifier */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_ID_byte_1__Ident_1 = { 0x00, 0x00, 0x07, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register ID_byte_2 0x01 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_ID_byte_2 = { 0x01, 0x00, 0x08, 0x00 };
|
||||
/* Ident_2 bit(s): LSB of device identifier */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_ID_byte_2__Ident_2 = { 0x01, 0x00, 0x08, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register ID_byte_3 0x02 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_ID_byte_3 = { 0x02, 0x00, 0x08, 0x00 };
|
||||
/* Major_rev bit(s): Major revision of device */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_ID_byte_3__Major_rev = { 0x02, 0x04, 0x04, 0x00 };
|
||||
/* Major_rev bit(s): Minor revision of device */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_ID_byte_3__Minor_rev = { 0x02, 0x00, 0x04, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register Thermo_byte_1 0x03 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Thermo_byte_1 = { 0x03, 0x00, 0x08, 0x00 };
|
||||
/* TM_D bit(s): Device temperature */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Thermo_byte_1__TM_D = { 0x03, 0x00, 0x07, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register Thermo_byte_2 0x04 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Thermo_byte_2 = { 0x04, 0x00, 0x08, 0x00 };
|
||||
/* TM_ON bit(s): Set device temperature measurement to ON or OFF */
|
||||
/* 1 => Temperature measurement ON */
|
||||
/* 0 => Temperature measurement OFF */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Thermo_byte_2__TM_ON = { 0x04, 0x00, 0x01, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register Power_state_byte_1 0x05 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Power_state_byte_1 = { 0x05, 0x00, 0x08, 0x00 };
|
||||
/* POR bit(s): Indicates that device just powered ON */
|
||||
/* 1 => POR: No access done to device */
|
||||
/* 0 => At least one access has been done to device */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Power_state_byte_1__POR = { 0x05, 0x07, 0x01, 0x00 };
|
||||
/* AGCs_Lock bit(s): Indicates that AGCs are locked */
|
||||
/* 1 => AGCs locked */
|
||||
/* 0 => AGCs not locked */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Power_state_byte_1__AGCs_Lock = { 0x05, 0x02, 0x01, 0x00 };
|
||||
/* Vsync_Lock bit(s): Indicates that VSync is locked */
|
||||
/* 1 => VSync locked */
|
||||
/* 0 => VSync not locked */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Power_state_byte_1__Vsync_Lock = { 0x05, 0x01, 0x01, 0x00 };
|
||||
/* LO_Lock bit(s): Indicates that LO is locked */
|
||||
/* 1 => LO locked */
|
||||
/* 0 => LO not locked */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Power_state_byte_1__LO_Lock = { 0x05, 0x00, 0x01, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register Power_state_byte_2 0x06 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Power_state_byte_2 = { 0x06, 0x00, 0x08, 0x00 };
|
||||
/* SM bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Power_state_byte_2__SM = { 0x06, 0x01, 0x01, 0x00 };
|
||||
/* SM_XT bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Power_state_byte_2__SM_XT = { 0x06, 0x00, 0x01, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register Input_Power_Level_byte 0x07 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Input_Power_Level_byte = { 0x07, 0x00, 0x08, 0x00 };
|
||||
/* Power_Level bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Input_Power_Level_byte__Power_Level = { 0x07, 0x00, 0x08, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register IRQ_status 0x08 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_status = { 0x08, 0x00, 0x08, 0x00 };
|
||||
/* IRQ_status bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_status__IRQ_status = { 0x08, 0x07, 0x01, 0x00 };
|
||||
/* MSM_XtalCal_End bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_status__MSM_XtalCal_End = { 0x08, 0x05, 0x01, 0x00 };
|
||||
/* MSM_RSSI_End bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_status__MSM_RSSI_End = { 0x08, 0x04, 0x01, 0x00 };
|
||||
/* MSM_LOCalc_End bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_status__MSM_LOCalc_End = { 0x08, 0x03, 0x01, 0x00 };
|
||||
/* MSM_RFCal_End bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_status__MSM_RFCal_End = { 0x08, 0x02, 0x01, 0x00 };
|
||||
/* MSM_IRCAL_End bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_status__MSM_IRCAL_End = { 0x08, 0x01, 0x01, 0x00 };
|
||||
/* MSM_RCCal_End bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_status__MSM_RCCal_End = { 0x08, 0x00, 0x01, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register IRQ_enable 0x09 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_enable = { 0x09, 0x00, 0x08, 0x00 };
|
||||
/* IRQ_Enable bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_enable__IRQ_Enable = { 0x09, 0x07, 0x01, 0x00 };
|
||||
/* MSM_XtalCal_Enable bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_enable__MSM_XtalCal_Enable = { 0x09, 0x05, 0x01, 0x00 };
|
||||
/* MSM_RSSI_Enable bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_enable__MSM_RSSI_Enable = { 0x09, 0x04, 0x01, 0x00 };
|
||||
/* MSM_LOCalc_Enable bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_enable__MSM_LOCalc_Enable = { 0x09, 0x03, 0x01, 0x00 };
|
||||
/* MSM_RFCal_Enable bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_enable__MSM_RFCal_Enable = { 0x09, 0x02, 0x01, 0x00 };
|
||||
/* MSM_IRCAL_Enable bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_enable__MSM_IRCAL_Enable = { 0x09, 0x01, 0x01, 0x00 };
|
||||
/* MSM_RCCal_Enable bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_enable__MSM_RCCal_Enable = { 0x09, 0x00, 0x01, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register IRQ_clear 0x0A */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_clear = { 0x0A, 0x00, 0x08, 0x00 };
|
||||
/* IRQ_Clear bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_clear__IRQ_Clear = { 0x0A, 0x07, 0x01, 0x00 };
|
||||
/* MSM_XtalCal_Clear bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_clear__MSM_XtalCal_Clear = { 0x0A, 0x05, 0x01, 0x00 };
|
||||
/* MSM_RSSI_Clear bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_clear__MSM_RSSI_Clear = { 0x0A, 0x04, 0x01, 0x00 };
|
||||
/* MSM_LOCalc_Clear bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_clear__MSM_LOCalc_Clear = { 0x0A, 0x03, 0x01, 0x00 };
|
||||
/* MSM_RFCal_Clear bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_clear__MSM_RFCal_Clear = { 0x0A, 0x02, 0x01, 0x00 };
|
||||
/* MSM_IRCAL_Clear bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_clear__MSM_IRCAL_Clear = { 0x0A, 0x01, 0x01, 0x00 };
|
||||
/* MSM_RCCal_Clear bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_clear__MSM_RCCal_Clear = { 0x0A, 0x00, 0x01, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register IRQ_set 0x0B */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_set = { 0x0B, 0x00, 0x08, 0x00 };
|
||||
/* IRQ_Set bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_set__IRQ_Set = { 0x0B, 0x07, 0x01, 0x00 };
|
||||
/* MSM_XtalCal_Set bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_set__MSM_XtalCal_Set = { 0x0B, 0x05, 0x01, 0x00 };
|
||||
/* MSM_RSSI_Set bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_set__MSM_RSSI_Set = { 0x0B, 0x04, 0x01, 0x00 };
|
||||
/* MSM_LOCalc_Set bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_set__MSM_LOCalc_Set = { 0x0B, 0x03, 0x01, 0x00 };
|
||||
/* MSM_RFCal_Set bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_set__MSM_RFCal_Set = { 0x0B, 0x02, 0x01, 0x00 };
|
||||
/* MSM_IRCAL_Set bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_set__MSM_IRCAL_Set = { 0x0B, 0x01, 0x01, 0x00 };
|
||||
/* MSM_RCCal_Set bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IRQ_set__MSM_RCCal_Set = { 0x0B, 0x00, 0x01, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register AGC1_byte_1 0x0C */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_1 = { 0x0C, 0x00, 0x08, 0x00 };
|
||||
/* AGC1_TOP bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_1__AGC1_TOP = { 0x0C, 0x00, 0x04, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register AGC1_byte_2 0x0D */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_2 = { 0x0D, 0x00, 0x08, 0x00 };
|
||||
/* AGC1_Top_Mode_Val bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_2__AGC1_Top_Mode_Val = { 0x0D, 0x03, 0x02, 0x00 };
|
||||
/* AGC1_Top_Mode bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_2__AGC1_Top_Mode = { 0x0D, 0x00, 0x03, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register AGC2_byte_1 0x0E */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGC2_byte_1 = { 0x0E, 0x00, 0x08, 0x00 };
|
||||
/* AGC2_TOP bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGC2_byte_1__AGC2_TOP = { 0x0E, 0x00, 0x03, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register AGCK_byte_1 0x0F */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGCK_byte_1 = { 0x0F, 0x00, 0x08, 0x00 };
|
||||
/* AGCs_Up_Step_assym bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGCK_byte_1__AGCs_Up_Step_assym = { 0x0F, 0x06, 0x02, 0x00 };
|
||||
/* Pulse_Shaper_Disable bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGCK_byte_1__Pulse_Shaper_Disable = { 0x0F, 0x04, 0x01, 0x00 };
|
||||
/* AGCK_Step bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGCK_byte_1__AGCK_Step = { 0x0F, 0x02, 0x02, 0x00 };
|
||||
/* AGCK_Mode bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGCK_byte_1__AGCK_Mode = { 0x0F, 0x00, 0x02, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register RF_AGC_byte 0x10 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_AGC_byte = { 0x10, 0x00, 0x08, 0x00 };
|
||||
/* PD_AGC_Adapt3x bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_AGC_byte__PD_AGC_Adapt3x = { 0x10, 0x06, 0x02, 0x00 };
|
||||
/* RFAGC_Adapt_TOP bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_AGC_byte__RFAGC_Adapt_TOP = { 0x10, 0x04, 0x02, 0x00 };
|
||||
/* RFAGC_Low_BW bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_AGC_byte__RFAGC_Low_BW = { 0x10, 0x03, 0x01, 0x00 };
|
||||
/* RFAGC_Top bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_AGC_byte__RFAGC_Top = { 0x10, 0x00, 0x03, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register W_Filter_byte 0x11 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_W_Filter_byte = { 0x11, 0x00, 0x08, 0x00 };
|
||||
/* VHF_III_mode bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_W_Filter_byte__VHF_III_mode = { 0x11, 0x07, 0x01, 0x00 };
|
||||
/* RF_Atten_3dB bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_W_Filter_byte__RF_Atten_3dB = { 0x11, 0x06, 0x01, 0x00 };
|
||||
/* W_Filter_Enable bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_W_Filter_byte__W_Filter_Enable = { 0x11, 0x05, 0x01, 0x00 };
|
||||
/* W_Filter_Bypass bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_W_Filter_byte__W_Filter_Bypass = { 0x11, 0x04, 0x01, 0x00 };
|
||||
/* W_Filter bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_W_Filter_byte__W_Filter = { 0x11, 0x02, 0x02, 0x00 };
|
||||
/* W_Filter_Offset bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_W_Filter_byte__W_Filter_Offset = { 0x11, 0x00, 0x02, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register IR_Mixer_byte_1 0x12 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IR_Mixer_byte_1 = { 0x12, 0x00, 0x08, 0x00 };
|
||||
/* S2D_Gain bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IR_Mixer_byte_1__S2D_Gain = { 0x12, 0x04, 0x02, 0x00 };
|
||||
/* IR_Mixer_Top bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IR_Mixer_byte_1__IR_Mixer_Top = { 0x12, 0x00, 0x04, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register AGC5_byte_1 0x13 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_1 = { 0x13, 0x00, 0x08, 0x00 };
|
||||
/* AGCs_Do_Step_assym bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_1__AGCs_Do_Step_assym = { 0x13, 0x05, 0x02, 0x00 };
|
||||
/* AGC5_Ana bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_1__AGC5_Ana = { 0x13, 0x04, 0x01, 0x00 };
|
||||
/* AGC5_TOP bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_1__AGC5_TOP = { 0x13, 0x00, 0x04, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register IF_AGC_byte 0x14 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IF_AGC_byte = { 0x14, 0x00, 0x08, 0x00 };
|
||||
/* IFnotchToRSSI bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IF_AGC_byte__IFnotchToRSSI = { 0x14, 0x07, 0x01, 0x00 };
|
||||
/* LPF_DCOffset_Corr bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IF_AGC_byte__LPF_DCOffset_Corr = { 0x14, 0x06, 0x01, 0x00 };
|
||||
/* IF_level bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IF_AGC_byte__IF_level = { 0x14, 0x00, 0x03, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register IF_Byte_1 0x15 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IF_Byte_1 = { 0x15, 0x00, 0x08, 0x00 };
|
||||
/* IF_HP_Fc bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IF_Byte_1__IF_HP_Fc = { 0x15, 0x06, 0x02, 0x00 };
|
||||
/* IF_ATSC_Notch bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IF_Byte_1__IF_ATSC_Notch = { 0x15, 0x05, 0x01, 0x00 };
|
||||
/* LP_FC_Offset bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IF_Byte_1__LP_FC_Offset = { 0x15, 0x03, 0x02, 0x00 };
|
||||
/* LP_Fc bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IF_Byte_1__LP_Fc = { 0x15, 0x00, 0x03, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register Reference_Byte 0x16 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Reference_Byte = { 0x16, 0x00, 0x08, 0x00 };
|
||||
/* Digital_Clock_Mode bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Reference_Byte__Digital_Clock_Mode = { 0x16, 0x06, 0x02, 0x00 };
|
||||
/* XTout bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Reference_Byte__XTout = { 0x16, 0x00, 0x02, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register IF_Frequency_byte 0x17 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IF_Frequency_byte = { 0x17, 0x00, 0x08, 0x00 };
|
||||
/* IF_Freq bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IF_Frequency_byte__IF_Freq = { 0x17, 0x00, 0x08, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register RF_Frequency_byte_1 0x18 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Frequency_byte_1 = { 0x18, 0x00, 0x08, 0x00 };
|
||||
/* RF_Freq_1 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Frequency_byte_1__RF_Freq_1 = { 0x18, 0x00, 0x04, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register RF_Frequency_byte_2 0x19 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Frequency_byte_2 = { 0x19, 0x00, 0x08, 0x00 };
|
||||
/* RF_Freq_2 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Frequency_byte_2__RF_Freq_2 = { 0x19, 0x00, 0x08, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register RF_Frequency_byte_3 0x1A */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Frequency_byte_3 = { 0x1A, 0x00, 0x08, 0x00 };
|
||||
/* RF_Freq_3 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Frequency_byte_3__RF_Freq_3 = { 0x1A, 0x00, 0x08, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register MSM_byte_1 0x1B */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1 = { 0x1B, 0x00, 0x08, 0x00 };
|
||||
/* RSSI_Meas bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1__RSSI_Meas = { 0x1B, 0x07, 0x01, 0x00 };
|
||||
/* RF_CAL_AV bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1__RF_CAL_AV = { 0x1B, 0x06, 0x01, 0x00 };
|
||||
/* RF_CAL bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1__RF_CAL = { 0x1B, 0x05, 0x01, 0x00 };
|
||||
/* IR_CAL_Loop bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1__IR_CAL_Loop = { 0x1B, 0x04, 0x01, 0x00 };
|
||||
/* IR_Cal_Image bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1__IR_Cal_Image = { 0x1B, 0x03, 0x01, 0x00 };
|
||||
/* IR_CAL_Wanted bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1__IR_CAL_Wanted = { 0x1B, 0x02, 0x01, 0x00 };
|
||||
/* RC_Cal bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1__RC_Cal = { 0x1B, 0x01, 0x01, 0x00 };
|
||||
/* Calc_PLL bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1__Calc_PLL = { 0x1B, 0x00, 0x01, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register MSM_byte_2 0x1C */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_2 = { 0x1C, 0x00, 0x08, 0x00 };
|
||||
/* XtalCal_Launch bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_2__XtalCal_Launch = { 0x1C, 0x01, 0x01, 0x00 };
|
||||
/* MSM_Launch bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_2__MSM_Launch = { 0x1C, 0x00, 0x01, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register PowerSavingMode 0x1D */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_PowerSavingMode = { 0x1D, 0x00, 0x08, 0x00 };
|
||||
/* PSM_AGC1 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_PowerSavingMode__PSM_AGC1 = { 0x1D, 0x07, 0x01, 0x00 };
|
||||
/* PSM_Bandsplit_Filter bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_PowerSavingMode__PSM_Bandsplit_Filter = { 0x1D, 0x05, 0x02, 0x00 };
|
||||
/* PSM_RFpoly bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_PowerSavingMode__PSM_RFpoly = { 0x1D, 0x04, 0x01, 0x00 };
|
||||
/* PSM_Mixer bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_PowerSavingMode__PSM_Mixer = { 0x1D, 0x03, 0x01, 0x00 };
|
||||
/* PSM_Ifpoly bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_PowerSavingMode__PSM_Ifpoly = { 0x1D, 0x02, 0x01, 0x00 };
|
||||
/* PSM_Lodriver bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_PowerSavingMode__PSM_Lodriver = { 0x1D, 0x00, 0x02, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register Power_Level_byte_2 0x1E */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Power_Level_byte_2 = { 0x1E, 0x00, 0x08, 0x00 };
|
||||
/* PD_PLD_read bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Power_Level_byte_2__PD_PLD_read = { 0x1E, 0x07, 0x01, 0x00 };
|
||||
/* IR_Target bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Power_Level_byte_2__PLD_Temp_Slope = { 0x1E, 0x05, 0x02, 0x00 };
|
||||
/* IR_GStep bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Power_Level_byte_2__PLD_Gain_Corr = { 0x1E, 0x00, 0x05, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register Adapt_Top_byte 0x1F */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Adapt_Top_byte = { 0x1F, 0x00, 0x08, 0x00 };
|
||||
/* Fast_Mode_AGC bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Adapt_Top_byte__Fast_Mode_AGC = { 0x1F, 0x06, 0x01, 0x00 };
|
||||
/* Range_LNA_Adapt bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Adapt_Top_byte__Range_LNA_Adapt = { 0x1F, 0x05, 0x01, 0x00 };
|
||||
/* Index_K_LNA_Adapt bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Adapt_Top_byte__Index_K_LNA_Adapt = { 0x1F, 0x03, 0x02, 0x00 };
|
||||
/* Index_K_Top_Adapt bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Adapt_Top_byte__Index_K_Top_Adapt = { 0x1F, 0x01, 0x02, 0x00 };
|
||||
/* Ovld_Udld_FastUp bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Adapt_Top_byte__Ovld_Udld_FastUp = { 0x1F, 0x00, 0x01, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register Vsync_byte 0x20 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Vsync_byte = { 0x20, 0x00, 0x08, 0x00 };
|
||||
/* Neg_modulation bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Vsync_byte__Neg_modulation = { 0x20, 0x07, 0x01, 0x00 };
|
||||
/* Tracer_Step bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Vsync_byte__Tracer_Step = { 0x20, 0x05, 0x02, 0x00 };
|
||||
/* Vsync_int bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Vsync_byte__Vsync_int = { 0x20, 0x04, 0x01, 0x00 };
|
||||
/* Vsync_Thresh bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Vsync_byte__Vsync_Thresh = { 0x20, 0x02, 0x02, 0x00 };
|
||||
/* Vsync_Len bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Vsync_byte__Vsync_Len = { 0x20, 0x00, 0x02, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register Vsync_Mgt_byte 0x21 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Vsync_Mgt_byte = { 0x21, 0x00, 0x08, 0x00 };
|
||||
/* PD_Vsync_Mgt bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Vsync_Mgt_byte__PD_Vsync_Mgt = { 0x21, 0x07, 0x01, 0x00 };
|
||||
/* PD_Ovld bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Vsync_Mgt_byte__PD_Ovld = { 0x21, 0x06, 0x01, 0x00 };
|
||||
/* PD_Ovld_RF bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Vsync_Mgt_byte__PD_Ovld_RF = { 0x21, 0x05, 0x01, 0x00 };
|
||||
/* AGC_Ovld_TOP bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Vsync_Mgt_byte__AGC_Ovld_TOP = { 0x21, 0x02, 0x03, 0x00 };
|
||||
/* Up_Step_Ovld bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Vsync_Mgt_byte__Up_Step_Ovld = { 0x21, 0x01, 0x01, 0x00 };
|
||||
/* AGC_Ovld_Timer bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Vsync_Mgt_byte__AGC_Ovld_Timer = { 0x21, 0x00, 0x01, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register IR_Mixer_byte_2 0x22 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IR_Mixer_byte_2 = { 0x22, 0x00, 0x08, 0x00 };
|
||||
/* IR_Mixer_loop_off bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IR_Mixer_byte_2__IR_Mixer_loop_off = { 0x22, 0x07, 0x01, 0x00 };
|
||||
/* IR_Mixer_Do_step bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IR_Mixer_byte_2__IR_Mixer_Do_step = { 0x22, 0x05, 0x02, 0x00 };
|
||||
/* Hi_Pass bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IR_Mixer_byte_2__Hi_Pass = { 0x22, 0x01, 0x01, 0x00 };
|
||||
/* IF_Notch bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IR_Mixer_byte_2__IF_Notch = { 0x22, 0x00, 0x01, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register AGC1_byte_3 0x23 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_3 = { 0x23, 0x00, 0x08, 0x00 };
|
||||
/* AGC1_loop_off bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_3__AGC1_loop_off = { 0x23, 0x07, 0x01, 0x00 };
|
||||
/* AGC1_Do_step bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_3__AGC1_Do_step = { 0x23, 0x05, 0x02, 0x00 };
|
||||
/* Force_AGC1_gain bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_3__Force_AGC1_gain = { 0x23, 0x04, 0x01, 0x00 };
|
||||
/* AGC1_Gain bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_3__AGC1_Gain = { 0x23, 0x00, 0x04, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register RFAGCs_Gain_byte_1 0x24 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_1 = { 0x24, 0x00, 0x08, 0x00 };
|
||||
/* PLD_DAC_Scale bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_1__PLD_DAC_Scale = { 0x24, 0x07, 0x01, 0x00 };
|
||||
/* PLD_CC_Enable bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_1__PLD_CC_Enable = { 0x24, 0x06, 0x01, 0x00 };
|
||||
/* PLD_Temp_Enable bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_1__PLD_Temp_Enable = { 0x24, 0x05, 0x01, 0x00 };
|
||||
/* TH_AGC_Adapt34 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_1__TH_AGC_Adapt34 = { 0x24, 0x04, 0x01, 0x00 };
|
||||
/* RFAGC_Sense_Enable bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_1__RFAGC_Sense_Enable = { 0x24, 0x02, 0x01, 0x00 };
|
||||
/* RFAGC_K_Bypass bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_1__RFAGC_K_Bypass = { 0x24, 0x01, 0x01, 0x00 };
|
||||
/* RFAGC_K_8 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_1__RFAGC_K_8 = { 0x24, 0x00, 0x01, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register RFAGCs_Gain_byte_2 0x25 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_2 = { 0x25, 0x00, 0x08, 0x00 };
|
||||
/* RFAGC_K bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_2__RFAGC_K = { 0x25, 0x00, 0x08, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register AGC5_byte_2 0x26 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_2 = { 0x26, 0x00, 0x08, 0x00 };
|
||||
/* AGC5_loop_off bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_2__AGC5_loop_off = { 0x26, 0x07, 0x01, 0x00 };
|
||||
/* AGC5_Do_step bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_2__AGC5_Do_step = { 0x26, 0x05, 0x02, 0x00 };
|
||||
/* Force_AGC5_gain bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_2__Force_AGC5_gain = { 0x26, 0x03, 0x01, 0x00 };
|
||||
/* AGC5_Gain bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_2__AGC5_Gain = { 0x26, 0x00, 0x03, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register RF_Cal_byte_1 0x27 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_1 = { 0x27, 0x00, 0x08, 0x00 };
|
||||
/* RFCAL_Offset_Cprog0 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_1__RFCAL_Offset_Cprog0 = { 0x27, 0x06, 0x02, 0x00 };
|
||||
/* RFCAL_Offset_Cprog1 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_1__RFCAL_Offset_Cprog1 = { 0x27, 0x04, 0x02, 0x00 };
|
||||
/* RFCAL_Offset_Cprog2 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_1__RFCAL_Offset_Cprog2 = { 0x27, 0x02, 0x02, 0x00 };
|
||||
/* RFCAL_Offset_Cprog3 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_1__RFCAL_Offset_Cprog3 = { 0x27, 0x00, 0x02, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register RF_Cal_byte_2 0x28 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_2 = { 0x28, 0x00, 0x08, 0x00 };
|
||||
/* RFCAL_Offset_Cprog4 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_2__RFCAL_Offset_Cprog4 = { 0x28, 0x06, 0x02, 0x00 };
|
||||
/* RFCAL_Offset_Cprog5 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_2__RFCAL_Offset_Cprog5 = { 0x28, 0x04, 0x02, 0x00 };
|
||||
/* RFCAL_Offset_Cprog6 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_2__RFCAL_Offset_Cprog6 = { 0x28, 0x02, 0x02, 0x00 };
|
||||
/* RFCAL_Offset_Cprog7 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_2__RFCAL_Offset_Cprog7 = { 0x28, 0x00, 0x02, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register RF_Cal_byte_3 0x29 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_3 = { 0x29, 0x00, 0x08, 0x00 };
|
||||
/* RFCAL_Offset_Cprog8 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_3__RFCAL_Offset_Cprog8 = { 0x29, 0x06, 0x02, 0x00 };
|
||||
/* RFCAL_Offset_Cprog9 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_3__RFCAL_Offset_Cprog9 = { 0x29, 0x04, 0x02, 0x00 };
|
||||
/* RFCAL_Offset_Cprog10 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_3__RFCAL_Offset_Cprog10 = { 0x29, 0x02, 0x02, 0x00 };
|
||||
/* RFCAL_Offset_Cprog11 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_3__RFCAL_Offset_Cprog11 = { 0x29, 0x00, 0x02, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register Bandsplit_Filter_byte 0x2A */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Bandsplit_Filter_byte = { 0x2A, 0x00, 0x08, 0x00 };
|
||||
/* Bandsplit_Filter_SubBand bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Bandsplit_Filter_byte__Bandsplit_Filter_SubBand = { 0x2A, 0x00, 0x02, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register RF_Filters_byte_1 0x2B */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_1 = { 0x2B, 0x00, 0x08, 0x00 };
|
||||
/* RF_Filter_Bypass bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_1__RF_Filter_Bypass = { 0x2B, 0x07, 0x01, 0x00 };
|
||||
/* AGC2_loop_off bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_1__AGC2_loop_off = { 0x2B, 0x05, 0x01, 0x00 };
|
||||
/* Force_AGC2_gain bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_1__Force_AGC2_gain = { 0x2B, 0x04, 0x01, 0x00 };
|
||||
/* RF_Filter_Gv bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_1__RF_Filter_Gv = { 0x2B, 0x02, 0x02, 0x00 };
|
||||
/* RF_Filter_Band bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_1__RF_Filter_Band = { 0x2B, 0x00, 0x02, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register RF_Filters_byte_2 0x2C */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_2 = { 0x2C, 0x00, 0x08, 0x00 };
|
||||
/* RF_Filter_Cap bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_2__RF_Filter_Cap = { 0x2C, 0x00, 0x08, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register RF_Filters_byte_3 0x2D */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_3 = { 0x2D, 0x00, 0x08, 0x00 };
|
||||
/* AGC2_Do_step bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_3__AGC2_Do_step = { 0x2D, 0x06, 0x02, 0x00 };
|
||||
/* Gain_Taper bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_3__Gain_Taper = { 0x2D, 0x00, 0x06, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register RF_Band_Pass_Filter_byte 0x2E */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Band_Pass_Filter_byte = { 0x2E, 0x00, 0x08, 0x00 };
|
||||
/* RF_BPF_Bypass bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Band_Pass_Filter_byte__RF_BPF_Bypass = { 0x2E, 0x07, 0x01, 0x00 };
|
||||
/* RF_BPF bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RF_Band_Pass_Filter_byte__RF_BPF = { 0x2E, 0x00, 0x03, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register CP_Current_byte 0x2F */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_CP_Current_byte = { 0x2F, 0x00, 0x08, 0x00 };
|
||||
/* LO_CP_Current bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_CP_Current_byte__LO_CP_Current = { 0x2F, 0x07, 0x01, 0x00 };
|
||||
/* N_CP_Current bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_CP_Current_byte__N_CP_Current = { 0x2F, 0x00, 0x07, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register AGCs_DetOut_byte 0x30 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte = { 0x30, 0x00, 0x08, 0x00 };
|
||||
/* Up_AGC5 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte__Up_AGC5 = { 0x30, 0x07, 0x01, 0x00 };
|
||||
/* Do_AGC5 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte__Do_AGC5 = { 0x30, 0x06, 0x01, 0x00 };
|
||||
/* Up_AGC4 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte__Up_AGC4 = { 0x30, 0x05, 0x01, 0x00 };
|
||||
/* Do_AGC4 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte__Do_AGC4 = { 0x30, 0x04, 0x01, 0x00 };
|
||||
/* Up_AGC2 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte__Up_AGC2 = { 0x30, 0x03, 0x01, 0x00 };
|
||||
/* Do_AGC2 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte__Do_AGC2 = { 0x30, 0x02, 0x01, 0x00 };
|
||||
/* Up_AGC1 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte__Up_AGC1 = { 0x30, 0x01, 0x01, 0x00 };
|
||||
/* Do_AGC1 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte__Do_AGC1 = { 0x30, 0x00, 0x01, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register RFAGCs_Gain_byte_3 0x31 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_3 = { 0x31, 0x00, 0x08, 0x00 };
|
||||
/* AGC2_Gain_Read bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_3__AGC2_Gain_Read = { 0x31, 0x04, 0x02, 0x00 };
|
||||
/* AGC1_Gain_Read bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_3__AGC1_Gain_Read = { 0x31, 0x00, 0x04, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register RFAGCs_Gain_byte_4 0x32 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_4 = { 0x32, 0x00, 0x08, 0x00 };
|
||||
/* Cprog_Read bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_4__Cprog_Read = { 0x32, 0x00, 0x08, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register RFAGCs_Gain_byte_5 0x33 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_5 = { 0x33, 0x00, 0x08, 0x00 };
|
||||
/* RFAGC_Read_K_8 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_5__RFAGC_Read_K_8 = { 0x33, 0x07, 0x01, 0x00 };
|
||||
/* Do_AGC1bis bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_5__Do_AGC1bis = { 0x33, 0x06, 0x01, 0x00 };
|
||||
/* AGC1_Top_Adapt_Low bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_5__AGC1_Top_Adapt_Low = { 0x33, 0x05, 0x01, 0x00 };
|
||||
/* Up_LNA_Adapt bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_5__Up_LNA_Adapt = { 0x33, 0x04, 0x01, 0x00 };
|
||||
/* Do_LNA_Adapt bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_5__Do_LNA_Adapt = { 0x33, 0x03, 0x01, 0x00 };
|
||||
/* TOP_AGC3_Read bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_5__TOP_AGC3_Read = { 0x33, 0x00, 0x03, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register RFAGCs_Gain_byte_6 0x34 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_6 = { 0x34, 0x00, 0x08, 0x00 };
|
||||
/* RFAGC_Read_K bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_6__RFAGC_Read_K = { 0x34, 0x00, 0x08, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register IFAGCs_Gain_byte 0x35 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IFAGCs_Gain_byte = { 0x35, 0x00, 0x08, 0x00 };
|
||||
/* AGC5_Gain_Read bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IFAGCs_Gain_byte__AGC5_Gain_Read = { 0x35, 0x03, 0x03, 0x00 };
|
||||
/* AGC4_Gain_Read bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IFAGCs_Gain_byte__AGC4_Gain_Read = { 0x35, 0x00, 0x03, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register RSSI_byte_1 0x36 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RSSI_byte_1 = { 0x36, 0x00, 0x08, 0x00 };
|
||||
/* RSSI bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RSSI_byte_1__RSSI = { 0x36, 0x00, 0x08, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register RSSI_byte_2 0x37 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RSSI_byte_2 = { 0x37, 0x00, 0x08, 0x00 };
|
||||
/* RSSI_AV bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RSSI_byte_2__RSSI_AV = { 0x37, 0x05, 0x01, 0x00 };
|
||||
/* RSSI_Cap_Reset_En bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RSSI_byte_2__RSSI_Cap_Reset_En = { 0x37, 0x03, 0x01, 0x00 };
|
||||
/* RSSI_Cap_Val bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RSSI_byte_2__RSSI_Cap_Val = { 0x37, 0x02, 0x01, 0x00 };
|
||||
/* RSSI_Ck_Speed bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RSSI_byte_2__RSSI_Ck_Speed = { 0x37, 0x01, 0x01, 0x00 };
|
||||
/* RSSI_Dicho_not bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_RSSI_byte_2__RSSI_Dicho_not = { 0x37, 0x00, 0x01, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register Misc_byte 0x38 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Misc_byte = { 0x38, 0x00, 0x08, 0x00 };
|
||||
/* RFCALPOR_I2C bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Misc_byte__RFCALPOR_I2C = { 0x38, 0x06, 0x01, 0x00 };
|
||||
/* PD_Underload bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Misc_byte__PD_Underload = { 0x38, 0x05, 0x01, 0x00 };
|
||||
/* DDS_Polarity bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Misc_byte__DDS_Polarity = { 0x38, 0x04, 0x01, 0x00 };
|
||||
/* IRQ_Mode bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Misc_byte__IRQ_Mode = { 0x38, 0x01, 0x01, 0x00 };
|
||||
/* IRQ_Polarity bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Misc_byte__IRQ_Polarity = { 0x38, 0x00, 0x01, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register rfcal_log_0 0x39 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_0 = { 0x39, 0x00, 0x08, 0x00 };
|
||||
/* rfcal_log_0 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_0__rfcal_log_0 = { 0x39, 0x00, 0x08, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register rfcal_log_1 0x3A */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_1 = { 0x3A, 0x00, 0x08, 0x00 };
|
||||
/* rfcal_log_1 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_1__rfcal_log_1 = { 0x3A, 0x00, 0x08, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register rfcal_log_2 0x3B */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_2 = { 0x3B, 0x00, 0x08, 0x00 };
|
||||
/* rfcal_log_2 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_2__rfcal_log_2 = { 0x3B, 0x00, 0x08, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register rfcal_log_3 0x3C */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_3 = { 0x3C, 0x00, 0x08, 0x00 };
|
||||
/* rfcal_log_3 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_3__rfcal_log_3 = { 0x3C, 0x00, 0x08, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register rfcal_log_4 0x3D */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_4 = { 0x3D, 0x00, 0x08, 0x00 };
|
||||
/* rfcal_log_4 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_4__rfcal_log_4 = { 0x3D, 0x00, 0x08, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register rfcal_log_5 0x3E */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_5 = { 0x3E, 0x00, 0x08, 0x00 };
|
||||
/* rfcal_log_5 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_5__rfcal_log_5 = { 0x3E, 0x00, 0x08, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register rfcal_log_6 0x3F */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_6 = { 0x3F, 0x00, 0x08, 0x00 };
|
||||
/* rfcal_log_6 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_6__rfcal_log_6 = { 0x3F, 0x00, 0x08, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register rfcal_log_7 0x40 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_7 = { 0x40, 0x00, 0x08, 0x00 };
|
||||
/* rfcal_log_7 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_7__rfcal_log_7 = { 0x40, 0x00, 0x08, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register rfcal_log_8 0x41 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_8 = { 0x41, 0x00, 0x08, 0x00 };
|
||||
/* rfcal_log_8 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_8__rfcal_log_8 = { 0x41, 0x00, 0x08, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register rfcal_log_9 0x42 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_9 = { 0x42, 0x00, 0x08, 0x00 };
|
||||
/* rfcal_log_9 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_9__rfcal_log_9 = { 0x42, 0x00, 0x08, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register rfcal_log_10 0x43 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_10 = { 0x43, 0x00, 0x08, 0x00 };
|
||||
/* rfcal_log_10 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_10__rfcal_log_10 = { 0x43, 0x00, 0x08, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register rfcal_log_11 0x44 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_11 = { 0x44, 0x00, 0x08, 0x00 };
|
||||
/* rfcal_log_11 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_11__rfcal_log_11 = { 0x44, 0x00, 0x08, 0x00 };
|
||||
|
||||
|
||||
|
||||
/* TDA18273 Register Main_Post_Divider_byte 0x51 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Main_Post_Divider_byte = { 0x51, 0x00, 0x08, 0x00 };
|
||||
/* LOPostDiv bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Main_Post_Divider_byte__LOPostDiv = { 0x51, 0x04, 0x03, 0x00 };
|
||||
/* LOPresc bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Main_Post_Divider_byte__LOPresc = { 0x51, 0x00, 0x04, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register Sigma_delta_byte_1 0x52 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_1 = { 0x52, 0x00, 0x08, 0x00 };
|
||||
/* LO_Int bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_1__LO_Int = { 0x52, 0x00, 0x07, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register Sigma_delta_byte_2 0x53 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_2 = { 0x53, 0x00, 0x08, 0x00 };
|
||||
/* LO_Frac_2 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_2__LO_Frac_2 = { 0x53, 0x00, 0x07, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register Sigma_delta_byte_3 0x54 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_3 = { 0x54, 0x00, 0x08, 0x00 };
|
||||
/* LO_Frac_1 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_3__LO_Frac_1 = { 0x54, 0x00, 0x08, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register Sigma_delta_byte_4 0x55 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_4 = { 0x55, 0x00, 0x08, 0x00 };
|
||||
/* LO_Frac_0 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_4__LO_Frac_0 = { 0x55, 0x00, 0x08, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register Sigma_delta_byte_5 0x56 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_5 = { 0x56, 0x00, 0x08, 0x00 };
|
||||
/* N_K_correct_manual bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_5__N_K_correct_manual = { 0x56, 0x01, 0x01, 0x00 };
|
||||
/* LO_Calc_Disable bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_5__LO_Calc_Disable = { 0x56, 0x00, 0x01, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register Regulators_byte 0x58 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Regulators_byte = { 0x58, 0x00, 0x08, 0x00 };
|
||||
/* RF_Reg bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Regulators_byte__RF_Reg = { 0x58, 0x02, 0x02, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register IR_Cal_byte_5 0x5B */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IR_Cal_byte_5 = { 0x5B, 0x00, 0x08, 0x00 };
|
||||
/* Mixer_Gain_Bypass bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IR_Cal_byte_5__Mixer_Gain_Bypass = { 0x5B, 0x07, 0x01, 0x00 };
|
||||
/* IR_Mixer_Gain bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_IR_Cal_byte_5__IR_Mixer_Gain = { 0x5B, 0x04, 0x03, 0x00 };
|
||||
|
||||
|
||||
/* TDA18273 Register Power_Down_byte_2 0x5F */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Power_Down_byte_2 = { 0x5F, 0x00, 0x08, 0x00 };
|
||||
/* PD_LNA bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Power_Down_byte_2__PD_LNA = { 0x5F, 0x07, 0x01, 0x00 };
|
||||
/* PD_Det4 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Power_Down_byte_2__PD_Det4 = { 0x5F, 0x03, 0x01, 0x00 };
|
||||
/* PD_Det3 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Power_Down_byte_2__PD_Det3 = { 0x5F, 0x02, 0x01, 0x00 };
|
||||
/* PD_Det1 bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Power_Down_byte_2__PD_Det1 = { 0x5F, 0x00, 0x01, 0x00 };
|
||||
|
||||
/* TDA18273 Register Power_Down_byte_3 0x60 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Power_Down_byte_3 = { 0x60, 0x00, 0x08, 0x00 };
|
||||
/* Force_Soft_Reset bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Power_Down_byte_3__Force_Soft_Reset = { 0x60, 0x01, 0x01, 0x00 };
|
||||
/* Soft_Reset bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Power_Down_byte_3__Soft_Reset = { 0x60, 0x00, 0x01, 0x00 };
|
||||
|
||||
/* TDA18273 Register Charge_pump_byte 0x64 */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Charge_pump_byte = { 0x64, 0x00, 0x08, 0x00 };
|
||||
/* ICP_Bypass bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Charge_pump_byte__ICP_Bypass = { 0x64, 0x07, 0x01, 0x00 };
|
||||
/* ICP bit(s): */
|
||||
const TDA18273_BitField_t gTDA18273_Reg_Charge_pump_byte__ICP = { 0x64, 0x00, 0x02, 0x00 };
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
@@ -0,0 +1,302 @@
|
||||
/**
|
||||
Copyright (C) 2008 NXP B.V., All Rights Reserved.
|
||||
This source code and any compilation or derivative thereof is the proprietary
|
||||
information of NXP B.V. and is confidential in nature. Under no circumstances
|
||||
is this software to be exposed to or placed under an Open Source License of
|
||||
any type without the expressed written permission of NXP B.V.
|
||||
*
|
||||
* \file tmdlI2C.h
|
||||
* %version: 4 %
|
||||
*
|
||||
* \date %date_modified%
|
||||
*
|
||||
* \brief Describe briefly the purpose of this file.
|
||||
*
|
||||
* REFERENCE DOCUMENTS :
|
||||
*
|
||||
* Detailed description may be added here.
|
||||
*
|
||||
* \section info Change Information
|
||||
*
|
||||
* \verbatim
|
||||
Date Modified by CRPRNr TASKNr Maintenance description
|
||||
-------------|-----------|-------|-------|-----------------------------------
|
||||
9-JULY-2007 | A.TANT | | | CREATION OF I2C ARCHITECTURE 2.0.0
|
||||
-------------|-----------|-------|-------|-----------------------------------
|
||||
| | | |
|
||||
-------------|-----------|-------|-------|-----------------------------------
|
||||
\endverbatim
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#ifndef TMDLI2C_H
|
||||
#define TMDLI2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/*============================================================================*/
|
||||
/* INCLUDE FILES */
|
||||
/*============================================================================*/
|
||||
|
||||
/*============================================================================*/
|
||||
/* MACRO DEFINITION */
|
||||
/*============================================================================*/
|
||||
|
||||
/* SW Error codes */
|
||||
#define I2C_ERR_BASE (CID_COMP_PARPORT | CID_LAYER_HWAPI)
|
||||
#define I2C_ERR_COMP (CID_COMP_PARPORT | CID_LAYER_HWAPI | TM_ERR_COMP_UNIQUE_START)
|
||||
|
||||
#define I2C_ERR_BAD_UNIT_NUMBER (I2C_ERR_BASE + TM_ERR_BAD_UNIT_NUMBER)
|
||||
#define I2C_ERR_NOT_INITIALIZED (I2C_ERR_BASE + TM_ERR_NOT_INITIALIZED)
|
||||
//#define I2C_ERR_INIT_FAILED (I2C_ERR_BASE + TM_ERR_INIT_FAILED)
|
||||
#define I2C_ERR_BAD_PARAMETER (I2C_ERR_BASE + TM_ERR_BAD_PARAMETER)
|
||||
#define I2C_ERR_NOT_SUPPORTED (I2C_ERR_BASE + TM_ERR_NOT_SUPPORTED)
|
||||
#define I2C_ERR_NOT_INSTALLED (I2C_ERR_COMP + 0x0001)
|
||||
#define I2C_ERR_FAILED (I2C_ERR_COMP + 0x0002)
|
||||
#define I2C_ERR_HW (I2C_ERR_COMP + 0x0003)
|
||||
//#define I2C_ERR_NOT_READY (I2C_ERR_COMP + 0x0002)
|
||||
//#define I2C_ERR_BAD_CRC (I2C_ERR_COMP + 0x0003)
|
||||
//#define I2C_ERR_BAD_VERSION (I2C_ERR_COMP + 0x0004)
|
||||
|
||||
typedef enum _tmI2CInterfaceType_t {
|
||||
tmI2CInterfaceUnknown = 0, /* No I2C Interface Defined */
|
||||
tmI2CInterfaceURTParallel, /* URT Parallel I2C Interface */
|
||||
tmI2CInterfaceURTUSB, /* URT USB I2C Interface */
|
||||
tmI2CInterfaceMMPParallel, /* MMP Parallel I2C Interface */
|
||||
tmI2CInterfaceCypressUSB, /* Cypress USB I2C Interface */
|
||||
tmI2CInterfaceCustomer, /* Customer I2C Interface */
|
||||
tmI2CInterfaceSienaUSB, /* Siena USB I2C Interface */
|
||||
tmI2CInterfaceSimuSamba, /* Simu Samba I2C Interface */
|
||||
tmI2CInterfaceMax
|
||||
} tmI2CInterfaceType_t, *ptmI2CInterfaceType_t;
|
||||
|
||||
typedef enum _tmI2CPortType_t {
|
||||
tmI2CPortUnknown = 0, /* No Port Type Defined */
|
||||
tmI2CPortLPT1, /* LPT1 Port Type */
|
||||
tmI2CPortLPT2, /* LPT2 Port Type */
|
||||
tmI2CPortLPT3, /* LPT3 Port Type */
|
||||
tmI2CPortUSB, /* USB Port Type */
|
||||
tmI2CPortMax
|
||||
} tmI2CPortType_t, *ptmI2CPortType_t;
|
||||
|
||||
typedef enum _tmI2CAction_t
|
||||
{
|
||||
tmI2CActionUnknown,
|
||||
tmI2CActionWrite = 0,
|
||||
tmI2CActionRead,
|
||||
tmI2CActionMax
|
||||
} tmI2CAction_t, *ptmI2CAction_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
tmI2CIdentModeUnknown = 0,
|
||||
tmI2CIdentModePosition,
|
||||
tmI2CIdentModeInstanceIndex,
|
||||
tmI2CIdentModeSerialNumber,
|
||||
tmI2CIdentModeMax
|
||||
} tmI2CIdentMode_t, *ptmI2CIdentMode_t;
|
||||
|
||||
typedef struct _tmI2CLLDriverVersion
|
||||
{
|
||||
UInt32 major;
|
||||
UInt32 minor;
|
||||
UInt32 build;
|
||||
UInt32 revision;
|
||||
} tmI2CLLDriverVersion, *ptmI2CLLDriverVersion;
|
||||
|
||||
// Serial Number
|
||||
typedef struct _tmI2CSerialNumber
|
||||
{
|
||||
Bool biSerialNumberAvailable;
|
||||
UInt8 iSerialNumber[32];
|
||||
UInt32 dwInstanceIndex;
|
||||
} tmI2CSerialNumber, *ptmI2CSerialNumber;
|
||||
|
||||
// Enumeration
|
||||
typedef struct _tmI2CEnumDevices
|
||||
{
|
||||
UInt32 dwInstanceCount;
|
||||
tmI2CSerialNumber devices[8];
|
||||
} tmI2CEnumDevices, *ptmI2CEnumDevices;
|
||||
|
||||
typedef struct _tmI2CInterfaceConfig_t
|
||||
{
|
||||
tmI2CInterfaceType_t eInterfaceType; /* Interface Type */
|
||||
tmI2CPortType_t ePortType; /* Port Type */
|
||||
tmI2CIdentMode_t tIdentificationMode;
|
||||
union
|
||||
{
|
||||
UInt8 position;
|
||||
UInt32 dwInstanceIndex;
|
||||
UInt8 serialNumber[32];
|
||||
}Identification;
|
||||
UInt32 dwAdditionalDataSize; /* Additional Data Size */
|
||||
void* pAdditionalData; /* Additional Data Pointer */
|
||||
} tmI2CInterfaceConfig_t, *ptmI2CInterfaceConfig_t;
|
||||
|
||||
// Callback for I2C Log
|
||||
typedef tmErrorCode_t (*w_tmdlI2CCallBack) (tmUnitSelect_t tUnit, CUInt32 uHwAddress, CUInt32 addrSize, CUInt8* pAddr, CUInt32 dataSize, CUInt8* pData, tmErrorCode_t err, tmI2CAction_t i2cAction, Bool bHwAddrAsWriteAddr);
|
||||
|
||||
/*============================================================================*/
|
||||
/* ENUM OR TYPE DEFINITION */
|
||||
/*============================================================================*/
|
||||
|
||||
|
||||
/*============================================================================*/
|
||||
/* EXTERN DATA DEFINITION */
|
||||
/*============================================================================*/
|
||||
|
||||
|
||||
|
||||
/*============================================================================*/
|
||||
/* EXTERN FUNCTION PROTOTYPES */
|
||||
/*============================================================================*/
|
||||
|
||||
|
||||
extern tmErrorCode_t
|
||||
tmdlI2CGetSWVersion
|
||||
(
|
||||
ptmSWVersion_t pSWVersion /* O: Receives SW Version */
|
||||
);
|
||||
|
||||
extern tmErrorCode_t
|
||||
tmdlI2CGetLowLevelSWVersion
|
||||
(
|
||||
tmUnitSelect_t tUnit,
|
||||
ptmSWVersion_t pSWVersion, /* O: Receives SW Version */
|
||||
ptmI2CLLDriverVersion pLLSWVersion /* O: Receives LL SW Version */
|
||||
);
|
||||
|
||||
extern tmErrorCode_t
|
||||
tmdlI2CGetLowLevelDevices
|
||||
(
|
||||
tmUnitSelect_t tUnit,
|
||||
ptmI2CEnumDevices pDevices /* O: Receives LL Devices */
|
||||
);
|
||||
|
||||
extern tmErrorCode_t
|
||||
tmdlI2CInit
|
||||
(
|
||||
tmUnitSelect_t tUnit, /* I: FrontEnd unit number */
|
||||
tmbslFrontEndDependency_t* psSrvFunc
|
||||
);
|
||||
|
||||
extern tmErrorCode_t
|
||||
tmdlI2CDeInit
|
||||
(
|
||||
tmUnitSelect_t tUnit
|
||||
);
|
||||
|
||||
extern tmErrorCode_t
|
||||
tmdlI2CSetInterface
|
||||
(
|
||||
tmUnitSelect_t tUnit,
|
||||
ptmI2CInterfaceConfig_t psI2CInterface
|
||||
);
|
||||
|
||||
extern tmErrorCode_t
|
||||
tmdlI2CSetPath
|
||||
(
|
||||
tmUnitSelect_t tUnit,
|
||||
int pPath_length,
|
||||
wchar_t* My_path
|
||||
);
|
||||
|
||||
extern tmErrorCode_t
|
||||
tmdlI2CGetInterface
|
||||
(
|
||||
tmUnitSelect_t tUnit,
|
||||
ptmI2CInterfaceConfig_t psI2CInterface
|
||||
);
|
||||
|
||||
extern tmErrorCode_t
|
||||
tmdlI2CWrite
|
||||
(
|
||||
tmUnitSelect_t tUnit,
|
||||
UInt32 uHwAddress,
|
||||
UInt32 AddrSize,
|
||||
UInt8* pAddr,
|
||||
UInt32 WriteLen,
|
||||
UInt8* pData
|
||||
);
|
||||
|
||||
extern tmErrorCode_t
|
||||
tmdlI2CRead
|
||||
(
|
||||
tmUnitSelect_t tUnit,
|
||||
UInt32 uHwAddress,
|
||||
UInt32 AddrSize,
|
||||
UInt8* pAddr,
|
||||
UInt32 ReadLen,
|
||||
UInt8* pData
|
||||
);
|
||||
|
||||
extern tmErrorCode_t
|
||||
tmdlI2CSetErrorEnable
|
||||
(
|
||||
tmUnitSelect_t tUnit,
|
||||
Bool bErrorEnable
|
||||
);
|
||||
|
||||
extern tmErrorCode_t
|
||||
tmdlI2CGetErrorEnable
|
||||
(
|
||||
tmUnitSelect_t tUnit,
|
||||
Bool* pbErrorEnable
|
||||
);
|
||||
|
||||
extern tmErrorCode_t
|
||||
tmdlI2CSetPortType
|
||||
(
|
||||
tmUnitSelect_t tUnit,
|
||||
tmI2CPortType_t dwPortType
|
||||
);
|
||||
|
||||
extern tmErrorCode_t
|
||||
tmdlI2CGetPortType
|
||||
(
|
||||
tmUnitSelect_t tUnit,
|
||||
ptmI2CPortType_t pdwPortType
|
||||
);
|
||||
|
||||
extern tmErrorCode_t
|
||||
tmdlI2CSetBitrate
|
||||
(
|
||||
tmUnitSelect_t tUnit,
|
||||
UInt32 dwBitrate
|
||||
);
|
||||
|
||||
extern tmErrorCode_t
|
||||
tmdlI2CGetBitrate
|
||||
(
|
||||
tmUnitSelect_t tUnit,
|
||||
UInt32* pdwBitrate
|
||||
);
|
||||
|
||||
extern tmErrorCode_t
|
||||
tmdlI2CSetHwAddrAsWriteAddr
|
||||
(
|
||||
tmUnitSelect_t tUnit,
|
||||
Bool bHwAddrAsWriteAddr
|
||||
);
|
||||
|
||||
extern tmErrorCode_t
|
||||
tmdlI2CGetHwAddrAsWriteAddr
|
||||
(
|
||||
tmUnitSelect_t tUnit,
|
||||
Bool* pbHwAddrAsWriteAddr
|
||||
);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* TMDLI2C_H */
|
||||
/*============================================================================*/
|
||||
/* END OF FILE */
|
||||
/*============================================================================*/
|
||||
|
||||
Executable
+489
@@ -0,0 +1,489 @@
|
||||
/*
|
||||
Copyright (C) 2010 NXP B.V., All Rights Reserved.
|
||||
This source code and any compilation or derivative thereof is the proprietary
|
||||
information of NXP B.V. and is confidential in nature. Under no circumstances
|
||||
is this software to be exposed to or placed under an Open Source License of
|
||||
any type without the expressed written permission of NXP B.V.
|
||||
*
|
||||
* \file main.c
|
||||
*
|
||||
* 3
|
||||
*
|
||||
* \date %2011.5.4%
|
||||
*
|
||||
* \brief V7 tuner driver
|
||||
*
|
||||
* REFERENCE DOCUMENTS :
|
||||
* OM3912_Driver_User_Guide.pdf
|
||||
*
|
||||
* Detailed description may be added here.
|
||||
*
|
||||
* \section info Change Information
|
||||
*
|
||||
*/
|
||||
#include "../inc/config.h"
|
||||
|
||||
#if USE_TUNER
|
||||
//*--------------------------------------------------------------------------------------
|
||||
//* Include Standard files
|
||||
//*--------------------------------------------------------------------------------------
|
||||
#include <stdio.h>
|
||||
#include <stdarg.h>
|
||||
#include "tmNxTypes.h"
|
||||
#include "tmCompId.h"
|
||||
#include "tmFrontEnd.h"
|
||||
#include "tmbslFrontEndTypes.h"
|
||||
#include "../inc/delay.h"
|
||||
|
||||
|
||||
//*--------------------------------------------------------------------------------------
|
||||
//* Include Driver files
|
||||
//*--------------------------------------------------------------------------------------
|
||||
#include "tmbslTDA18273.h"
|
||||
|
||||
//*--------------------------------------------------------------------------------------
|
||||
//* Tuner I2C device address
|
||||
//*--------------------------------------------------------------------------------------
|
||||
#define TUN_I2C_ADDR 0xC6 //0xC0
|
||||
|
||||
uint32 tuner_byte_write(uint32 addr,uint8 data);
|
||||
uint8 tuner_byte_read(uint32 addr);
|
||||
|
||||
/**** Device table. List of device drivers for newlib. ****/
|
||||
const struct device_table_entry *device_table[] = {
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0 }; /* end of list */
|
||||
|
||||
/* It seems that int isatty(int) is no longer provided by the environment, see the
|
||||
example lpc2106_hello_rs232_newlib and the various syscalls.c for a workaround if
|
||||
the error message "unknown reference to isatty" appears during the link-process.
|
||||
(Reason might be the additional configure-option --disable-newlib-supplied-syscalls for
|
||||
newlib which had to be added since the build of newlib 1.14.0 failed when the "supplied"
|
||||
syscalls were not disabled.) */
|
||||
int isatty(int);
|
||||
|
||||
extern int isatty(int fd)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
//*--------------------------------------------------------------------------------------
|
||||
//* Prototype of function to be provided by customer
|
||||
//*--------------------------------------------------------------------------------------
|
||||
tmErrorCode_t UserWrittenWait(tmUnitSelect_t tUnit, UInt32 tms);
|
||||
tmErrorCode_t UserWrittenPrint(UInt32 level, const char* format, ...);
|
||||
tmErrorCode_t UserWrittenMutexInit(ptmbslFrontEndMutexHandle *ppMutexHandle);
|
||||
tmErrorCode_t UserWrittenMutexDeInit( ptmbslFrontEndMutexHandle pMutex);
|
||||
tmErrorCode_t UserWrittenMutexAcquire(ptmbslFrontEndMutexHandle pMutex, UInt32 timeOut);
|
||||
tmErrorCode_t UserWrittenMutexRelease(ptmbslFrontEndMutexHandle pMutex);
|
||||
|
||||
//*--------------------------------------------------------------------------------------
|
||||
//* Template of function to be provided by customer
|
||||
//*--------------------------------------------------------------------------------------
|
||||
|
||||
//*--------------------------------------------------------------------------------------
|
||||
//* Function Name : UserWrittenI2CRead
|
||||
//* Object :
|
||||
//* Input Parameters : tmUnitSelect_t tUnit
|
||||
//* UInt32 AddrSize,
|
||||
//* UInt8* pAddr,
|
||||
//* UInt32 ReadLen,
|
||||
//* UInt8* pData
|
||||
//* Output Parameters : tmErrorCode_t.
|
||||
//*--------------------------------------------------------------------------------------
|
||||
static tmErrorCode_t UserWrittenI2CRead(tmUnitSelect_t tUnit, UInt32 AddrSize, UInt8* pAddr,UInt32 ReadLen, UInt8* pData)
|
||||
{
|
||||
tmErrorCode_t err = TM_OK;
|
||||
#if USE_TUNER_18273
|
||||
UInt8 reg_addr;
|
||||
|
||||
reg_addr = *pAddr;
|
||||
|
||||
while(ReadLen--)
|
||||
{
|
||||
*pData++ = tuner_byte_read(reg_addr++);
|
||||
}
|
||||
#endif
|
||||
return err;
|
||||
}
|
||||
|
||||
//*--------------------------------------------------------------------------------------
|
||||
//* Function Name : UserWrittenI2CWrite
|
||||
//* Object :
|
||||
//* Input Parameters : tmUnitSelect_t tUnit
|
||||
//* UInt32 AddrSize,
|
||||
//* UInt8* pAddr,
|
||||
//* UInt32 WriteLen,
|
||||
//* UInt8* pData
|
||||
//* Output Parameters : tmErrorCode_t.
|
||||
//*--------------------------------------------------------------------------------------
|
||||
static tmErrorCode_t UserWrittenI2CWrite (tmUnitSelect_t tUnit,UInt32 AddrSize, UInt8* pAddr,UInt32 WriteLen, UInt8* pData)
|
||||
{
|
||||
tmErrorCode_t err = TM_OK;
|
||||
#if USE_TUNER_18273
|
||||
unsigned char reg_addr;
|
||||
|
||||
reg_addr = *pAddr;
|
||||
|
||||
while(WriteLen--)
|
||||
{
|
||||
tuner_byte_write(reg_addr++,*pData++);
|
||||
}
|
||||
#endif
|
||||
return err;
|
||||
}
|
||||
|
||||
//extern uint32 UserWrittenI2CRead(int tUnit,uint32 AddrSize, uint8* pAddr,uint32 ReadLen, uint8* pData);
|
||||
//extern uint32 UserWrittenI2CWrite(int tUnit,uint32 AddrSize, uint8* pAddr,uint32 WriteLen, uint8* pData);
|
||||
//*--------------------------------------------------------------------------------------
|
||||
//* Function Name : Main
|
||||
//* Object : Software entry point
|
||||
//* Input Parameters : none.
|
||||
//* Output Parameters : none.
|
||||
//* Current Unit is : 0
|
||||
//*--------------------------------------------------------------------------------------
|
||||
int TunerConf(uint32 conf_rf_freq)
|
||||
{//* Begin
|
||||
|
||||
/* Variable declarations */
|
||||
tmErrorCode_t err = TM_OK;
|
||||
tmbslFrontEndDependency_t sSrvTunerFunc;
|
||||
#if USE_TUNER_18273
|
||||
tmTDA18273StandardMode_t stdMode = tmTDA18273_QAM_6MHz; // modified to Winnetech standard
|
||||
#else
|
||||
tmTDA18273StandardMode_t stdMode = tmTDA18273_ATSC_6MHz;
|
||||
#endif
|
||||
UInt32 uRF; // RF frequency in Hz
|
||||
tmbslFrontEndState_t PLLLock = tmbslFrontEndStateUnknown;
|
||||
UInt32 uIF = 0;
|
||||
|
||||
uRF = conf_rf_freq;
|
||||
|
||||
/* Driver layer struct set-up to link with user written functions */
|
||||
sSrvTunerFunc.sIo.Write = UserWrittenI2CWrite;
|
||||
sSrvTunerFunc.sIo.Read = UserWrittenI2CRead;
|
||||
sSrvTunerFunc.sTime.Get = Null;
|
||||
sSrvTunerFunc.sTime.Wait = UserWrittenWait;
|
||||
sSrvTunerFunc.sDebug.Print = UserWrittenPrint;
|
||||
sSrvTunerFunc.sMutex.Init = NULL;
|
||||
sSrvTunerFunc.sMutex.DeInit = NULL;
|
||||
sSrvTunerFunc.sMutex.Acquire = NULL;
|
||||
sSrvTunerFunc.sMutex.Release = NULL;
|
||||
sSrvTunerFunc.dwAdditionalDataSize = 0;
|
||||
sSrvTunerFunc.pAdditionalData = Null;
|
||||
|
||||
/*Deinitialize former Instance, if necessary*/
|
||||
tmbslTDA18273_Close(0); // or tmbslTDA18273DeInit(0);
|
||||
|
||||
/* TDA18273 Driver initialization */
|
||||
err = tmbslTDA18273_Open(0, &sSrvTunerFunc); // or tmbslTDA18273Init(0, &sSrvTunerFunc);
|
||||
|
||||
if(err == TM_OK)
|
||||
{
|
||||
/* TDA18273 Hardware initialization */
|
||||
err = tmbslTDA18273_HwInit(0); // or tmbslTDA18273Reset(0);
|
||||
}//else
|
||||
// printf("err.%s %d\n",__FUNCTION__,__LINE__);
|
||||
|
||||
|
||||
tmbslTDA18273_CheckHWVersion(0);
|
||||
|
||||
if(err == TM_OK)
|
||||
{
|
||||
/* TDA18273 standard mode selection */
|
||||
err = tmbslTDA18273_SetStandardMode(0, stdMode); // or tmbslTDA18273SetStandardMode(0, stdMode);
|
||||
}//else
|
||||
// printf("err.%s %d\n",__FUNCTION__,__LINE__);
|
||||
//-----<< -----have err on there
|
||||
|
||||
if(err == TM_OK)
|
||||
{
|
||||
/* TDA18273 RF frequency selection */
|
||||
err = tmbslTDA18273_SetRF(0, uRF); // or tmbslTDA18273SetRf(0, uRF);
|
||||
}//else
|
||||
// printf("err.%s %d\n",__FUNCTION__,__LINE__);
|
||||
if(err == TM_OK)
|
||||
{
|
||||
/* Get TDA18273 PLL Lock status */
|
||||
err = tmbslTDA18273_GetLockStatus(0, &PLLLock); // or tmbslTDA18273GetLockStatus(0, &PLLLock);
|
||||
//printf("Tuner Lock State = %d\n",PLLLock);
|
||||
}//else
|
||||
// printf("err.%s %d\n",__FUNCTION__,__LINE__);
|
||||
|
||||
if(err == TM_OK)
|
||||
{
|
||||
/* Get TDA18273 IF value */
|
||||
err = tmbslTDA18273_GetIF(0, &uIF); // or tmbslTDA18273GetIF(0, &uIF);
|
||||
}//else
|
||||
// printf("err.%s %d\n",__FUNCTION__,__LINE__);
|
||||
|
||||
if(err == TM_OK)
|
||||
{
|
||||
/* Put TDA18273 in standby mode: */
|
||||
err = tmbslTDA18273_SetPowerState(0, tmPowerOn);
|
||||
}//else
|
||||
// printf("err.%s %d\n",__FUNCTION__,__LINE__);
|
||||
|
||||
if(err == TM_OK)
|
||||
{
|
||||
/*Do not Deinitialize TDA18273 here */
|
||||
/* DeInitialize TDA18273 Driver */
|
||||
//err = tmbslTDA18273_Close(0); // or tmbslTDA18273DeInit(0);
|
||||
}
|
||||
|
||||
return err;
|
||||
}//* End
|
||||
|
||||
int iic_rx_tun_readstate(void)
|
||||
{//Begin
|
||||
tmErrorCode_t err = TM_OK;
|
||||
unsigned char i2caddr = 0x31;
|
||||
unsigned char i2cdata = 0;
|
||||
unsigned short temp;
|
||||
/*read RSSI*/
|
||||
err = tmbslTDA18273_GetPowerLevel(0,&i2cdata);
|
||||
//printf("RSSI\t=\t%fdBuV\n", ((float)i2cdata)/2.0);
|
||||
/*read RF filter gain*/
|
||||
if(err == TM_OK)
|
||||
{
|
||||
err = UserWrittenI2CRead(0, 1, &i2caddr, 1, &i2cdata);
|
||||
}
|
||||
if(err == TM_OK)
|
||||
{
|
||||
temp = (i2cdata & 0x30)>>4;
|
||||
switch(temp){
|
||||
case 0: printf("RF filter gain\t=\t-11dB(min)\n");break;
|
||||
case 1: printf("RF filter gain\t=\t-08dB\n");break;
|
||||
case 2: printf("RF filter gain\t=\t-05dB\n");break;
|
||||
case 3: printf("RF filter gain\t=\t-02dB(max)\n");break;
|
||||
}
|
||||
}
|
||||
/*read LNA gain*/
|
||||
if(err == TM_OK)
|
||||
{
|
||||
temp = i2cdata & 0x0F;
|
||||
switch(temp){
|
||||
case 0: printf("LNA gain\t=\t-10dB(min)\n");break;
|
||||
case 1: printf("LNA gain\t=\t-07dB\n");break;
|
||||
case 2: printf("LNA gain\t=\t-04dB\n");break;
|
||||
case 3: printf("LNA gain\t=\t-01dB\n");break;
|
||||
case 4: printf("LNA gain\t=\t+02dB\n");break;
|
||||
case 5: printf("LNA gain\t=\t+05dB\n");break;
|
||||
case 6: printf("LNA gain\t=\t+08dB\n");break;
|
||||
case 7: printf("LNA gain\t=\t+11dB\n");break;
|
||||
case 8: printf("LNA gain\t=\t+14dB\n");break;
|
||||
case 9: printf("LNA gain\t=\t+17dB\n");break;
|
||||
case 10: printf("LNA gain\t=\t+20dB(max)\n");break;
|
||||
}
|
||||
}
|
||||
/*read RFAGC gain*/
|
||||
if(err == TM_OK)
|
||||
{
|
||||
i2caddr = 0x34;
|
||||
err = UserWrittenI2CRead(0, 1, &i2caddr, 1, &i2cdata);
|
||||
}
|
||||
if(err == TM_OK)
|
||||
{
|
||||
temp = i2cdata;
|
||||
i2caddr = 0x33;
|
||||
err = UserWrittenI2CRead(0, 1, &i2caddr, 1, &i2cdata);
|
||||
}
|
||||
if(err == TM_OK)
|
||||
{
|
||||
temp = temp|((i2cdata&0x80)<<1);
|
||||
printf("RFAGC Gain\t=\t0x%.3x",temp);
|
||||
if(temp == 0)
|
||||
printf("(min)\n");
|
||||
else if(temp == 0x1FF)
|
||||
printf("(max)\n");
|
||||
else
|
||||
printf("\n");
|
||||
}
|
||||
/*read IF AGC gain*/
|
||||
if(err == TM_OK)
|
||||
{
|
||||
i2caddr = 0x35;
|
||||
err = UserWrittenI2CRead(0, 1, &i2caddr, 1, &i2cdata);
|
||||
}
|
||||
if(err == TM_OK)
|
||||
{
|
||||
temp = (i2cdata & 0x38)>>3;
|
||||
switch(temp){
|
||||
case 0: printf("Lowpass gain\t=\t-06dB(min)\n");break;
|
||||
case 1: printf("Lowpass gain\t=\t-03dB\n");break;
|
||||
case 2: printf("Lowpass gain\t=\t+00dB\n");break;
|
||||
case 3: printf("Lowpass gain\t=\t+03dB\n");break;
|
||||
case 4: printf("Lowpass gain\t=\t+06dB\n");break;
|
||||
case 5: printf("Lowpass gain\t=\t+09dB\n");break;
|
||||
case 6: printf("Lowpass gain\t=\t+12dB\n");break;
|
||||
case 7: printf("Lowpass gain\t=\t+15dB(max)\n");break;
|
||||
}
|
||||
}
|
||||
if(err == TM_OK)
|
||||
{
|
||||
temp = i2cdata & 0x07;
|
||||
switch(temp){
|
||||
case 0: printf("Mixer gain\t=\t+02dB(min)\n");break;
|
||||
case 1: printf("Mixer gain\t=\t+05dB\n");break;
|
||||
case 2: printf("Mixer gain\t=\t+08dB\n");break;
|
||||
case 3: printf("Mixer gain\t=\t+11dB\n");break;
|
||||
case 4: printf("Mixer gain\t=\t+14dB(max)\n");break;
|
||||
}
|
||||
}
|
||||
return err;
|
||||
|
||||
}//*End
|
||||
|
||||
int TunerReadRSSI(unsigned char* pRSSI)
|
||||
{
|
||||
return tmbslTDA18273_GetPowerLevel(0,pRSSI);
|
||||
}
|
||||
int TunerRead18273lock(void)
|
||||
{
|
||||
tmbslFrontEndState_t lock;
|
||||
|
||||
tmbslTDA18273_GetLockStatus(0,&lock);
|
||||
return (int)lock;
|
||||
}
|
||||
|
||||
int TunerRead18273mode(void)
|
||||
{
|
||||
TDA18273StandardMode_t smode;
|
||||
|
||||
tmbslTDA18273_GetStandardMode(0,&smode);
|
||||
return (int)smode;
|
||||
}
|
||||
|
||||
|
||||
//*--------------------------------------------------------------------------------------
|
||||
//* Function Name : UserWrittenWait
|
||||
//* Object :
|
||||
//* Input Parameters : tmUnitSelect_t tUnit
|
||||
//* UInt32 tms
|
||||
//* Output Parameters : tmErrorCode_t.
|
||||
//* Not used in the driver
|
||||
//*--------------------------------------------------------------------------------------
|
||||
tmErrorCode_t UserWrittenWait(tmUnitSelect_t tUnit, UInt32 tms)
|
||||
{
|
||||
/* Variable declarations */
|
||||
tmErrorCode_t err = TM_OK;
|
||||
|
||||
/* Customer code here */
|
||||
/* ...*/
|
||||
delay_ms(tms);
|
||||
/* ...*/
|
||||
/* End of Customer code here */
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
//*--------------------------------------------------------------------------------------
|
||||
//* Function Name : UserWrittenPrint
|
||||
//* Object :
|
||||
//* Input Parameters : UInt32 level, const char* format, ...
|
||||
//*
|
||||
//* Output Parameters : tmErrorCode_t.
|
||||
//*--------------------------------------------------------------------------------------
|
||||
tmErrorCode_t UserWrittenPrint(UInt32 level, const char* format, ...)
|
||||
{
|
||||
/* Variable declarations */
|
||||
tmErrorCode_t err = TM_OK;
|
||||
|
||||
/* Customer code here */
|
||||
/* ...*/
|
||||
va_list argp;
|
||||
va_start(argp,format);
|
||||
printf(format,argp);
|
||||
va_end(argp);
|
||||
/* ...*/
|
||||
/* End of Customer code here */
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
//*--------------------------------------------------------------------------------------
|
||||
//* Function Name : UserWrittenMutexInit
|
||||
//* Object :
|
||||
//* Input Parameters : ptmbslFrontEndMutexHandle *ppMutexHandle
|
||||
//* Output Parameters : tmErrorCode_t.
|
||||
//*--------------------------------------------------------------------------------------
|
||||
tmErrorCode_t UserWrittenMutexInit(ptmbslFrontEndMutexHandle *ppMutexHandle)
|
||||
{
|
||||
/* Variable declarations */
|
||||
tmErrorCode_t err = TM_OK;
|
||||
|
||||
/* Customer code here */
|
||||
/* ...*/
|
||||
|
||||
/* ...*/
|
||||
/* End of Customer code here */
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
//*--------------------------------------------------------------------------------------
|
||||
//* Function Name : UserWrittenMutexDeInit
|
||||
//* Object :
|
||||
//* Input Parameters : ptmbslFrontEndMutexHandle pMutex
|
||||
//* Output Parameters : tmErrorCode_t.
|
||||
//*--------------------------------------------------------------------------------------
|
||||
tmErrorCode_t UserWrittenMutexDeInit( ptmbslFrontEndMutexHandle pMutex)
|
||||
{
|
||||
/* Variable declarations */
|
||||
tmErrorCode_t err = TM_OK;
|
||||
|
||||
/* Customer code here */
|
||||
/* ...*/
|
||||
|
||||
/* ...*/
|
||||
/* End of Customer code here */
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
|
||||
//*--------------------------------------------------------------------------------------
|
||||
//* Function Name : UserWrittenMutexAcquire
|
||||
//* Object :
|
||||
//* Input Parameters : ptmbslFrontEndMutexHandle pMutex, UInt32 timeOut
|
||||
//* Output Parameters : tmErrorCode_t.
|
||||
//*--------------------------------------------------------------------------------------
|
||||
tmErrorCode_t UserWrittenMutexAcquire(ptmbslFrontEndMutexHandle pMutex, UInt32 timeOut)
|
||||
{
|
||||
/* Variable declarations */
|
||||
tmErrorCode_t err = TM_OK;
|
||||
|
||||
/* Customer code here */
|
||||
/* ...*/
|
||||
|
||||
/* ...*/
|
||||
/* End of Customer code here */
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
//*--------------------------------------------------------------------------------------
|
||||
//* Function Name : UserWrittenMutexRelease
|
||||
//* Object :
|
||||
//* Input Parameters : ptmbslFrontEndMutexHandle pMutex
|
||||
//* Output Parameters : tmErrorCode_t.
|
||||
//*--------------------------------------------------------------------------------------
|
||||
tmErrorCode_t UserWrittenMutexRelease(ptmbslFrontEndMutexHandle pMutex)
|
||||
{
|
||||
/* Variable declarations */
|
||||
tmErrorCode_t err = TM_OK;
|
||||
|
||||
/* Customer code here */
|
||||
/* ...*/
|
||||
|
||||
/* ...*/
|
||||
/* End of Customer code here */
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,16 @@
|
||||
/*
|
||||
* tuner_conf.h
|
||||
*
|
||||
* Created on: 2011-5-4
|
||||
* Author: qi.li
|
||||
*/
|
||||
|
||||
#ifndef TUNER_CONF_H_
|
||||
#define TUNER_CONF_H_
|
||||
extern int TunerConf(u32 conf_rf_freq);
|
||||
extern int TunerReadRSSI(u8* pRSSI);
|
||||
extern int iic_rx_tun_readstate(void);
|
||||
int TunerRead18273lock(void);
|
||||
int TunerRead18273mode(void);
|
||||
|
||||
#endif /* TUNER_CONF_H_ */
|
||||
Binary file not shown.
Reference in New Issue
Block a user