#include #include #include #include #include //define O_WRONLY and O_RDONLY #include "../inc/type.h" #include "../inc/eeprom.h" #include "../inc/ipara_cfg.h" #include "../inc/i2c_drv.h" #include "../inc/minIni.h" #include "../inc/isys_com.h" #define __un_used_ip2ts_i2c__ 1 #define MAP_ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) #if 0 // map const S_PARA_IO_ELEMENT g_para_e1_map[65535] = { { EEPROM_DEFAULT_PARAM_ADDR, E_HW_SYS_PARA_TYPE, "def_para", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_STANDARD_ADDR, E_HW_SYS_PARA_TYPE, "exc_std", 0, E_NORMAL_FILE_TYPE, }, { EERPOM_RESET_TIME_ADDR, E_HW_SYS_PARA_TYPE, "rst_time", 0, E_NORMAL_FILE_TYPE, }, { EERPOM_NEXT , E_HW_SYS_PARA_TYPE, "next", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_ASI_ADDR , E_HW_SYS_PARA_TYPE, "asi", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DPD_ADDR, E_HW_SYS_PARA_TYPE, "dpd", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_NET_ADDR, E_HW_SYS_PARA_TYPE, "net", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_GPS_ADDR, E_HW_SYS_PARA_TYPE, "gps", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_BAUD_ADDR, E_HW_SYS_PARA_TYPE, "baud", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_ASI2_ADDR, E_HW_SYS_PARA_TYPE, "asi2", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_INPUT_ADDR, E_HW_SYS_PARA_TYPE, "input", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_SFN_ID_H, E_HW_SYS_PARA_TYPE, "sfn_id_h", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_SFN_ID_L, E_HW_SYS_PARA_TYPE, "sfn_id_l", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_CHANNEL_ADDR , E_HW_SYS_PARA_TYPE, "channel", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_RX_CH_ADDR, E_HW_SYS_PARA_TYPE, "rx_ch", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_AGC_ADDR, E_HW_SYS_PARA_TYPE, "agc", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_HZ_UIH_ADDR, E_HW_SYS_PARA_TYPE, "hz_ui_h", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_HZ_UIL_ADDR, E_HW_SYS_PARA_TYPE, "hz_ui_l", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_POWER_UIH_ADDR, E_HW_SYS_PARA_TYPE, "power_ui_h", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_POWER_UIL_ADDR, E_HW_SYS_PARA_TYPE, "power_ui_l", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_CW_ADDR, E_HW_SYS_PARA_TYPE, "cw", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_RF_ADDR, E_HW_SYS_PARA_TYPE, "rf", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_0DBFLAGH_ADDR, E_HW_SYS_PARA_TYPE, "odb_flg_h", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_0DBFLAGL_ADDR, E_HW_SYS_PARA_TYPE, "odb_flg_l", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_AGC_LAST_ADDR, E_HW_SYS_PARA_TYPE, "agc_last", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_LDPC_QAM_ADDR , E_HW_SYS_PARA_TYPE, "ldpc_qam", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_PN_ADDR, E_HW_SYS_PARA_TYPE, "pn", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_ZBPILOT_ADDR, E_HW_SYS_PARA_TYPE, "zbpilot", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_INT_ADDR, E_HW_SYS_PARA_TYPE, "int", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DELAY_ADDR1, E_HW_SYS_PARA_TYPE, "delay_a1", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DELAY_ADDR2, E_HW_SYS_PARA_TYPE, "delay_a2", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DELAY_ADDR3, E_HW_SYS_PARA_TYPE, "delay_a3", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DELAY_ADDR4, E_HW_SYS_PARA_TYPE, "delay_a4", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_TXID_H_ADDR, E_HW_SYS_PARA_TYPE, "txid_h", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_TXID_L_ADDR, E_HW_SYS_PARA_TYPE, "txid_l", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_CF_ADDR, E_HW_SYS_PARA_TYPE, "cf", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_SIPDEL_ADDR, E_HW_SYS_PARA_TYPE, "sipdel", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_ZP_ADDR, E_HW_SYS_PARA_TYPE, "zp", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DLY_SEC_ADDR, E_HW_SYS_PARA_TYPE, "dly_sec", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_TOD_EXT_ADDR, E_HW_SYS_PARA_TYPE, "tod_ext", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_BPS_ADDR , E_HW_SYS_PARA_TYPE, "bps", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_ID_ADDR, E_HW_SYS_PARA_TYPE, "id", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_ID_ADDR_M, E_HW_SYS_PARA_TYPE, "id_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_PCR_ADDR , E_HW_SYS_PARA_TYPE, "pcr", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DS3_ADDR, E_HW_SYS_PARA_TYPE, "ds3", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_HI_ADDR, E_HW_SYS_PARA_TYPE, "hi", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_GNSS_ADDR, E_HW_SYS_PARA_TYPE, "gnss", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_UBLOX_ADDR, E_HW_SYS_PARA_TYPE, "ublox", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_AUTO_ADPC_ADDR , E_HW_SYS_PARA_TYPE, "auto_adpc", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_A_DPD_TIME, E_HW_SYS_PARA_TYPE, "a_dpd_time", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_A_DPD_A_SNR, E_HW_SYS_PARA_TYPE, "a_dpd_a_snr", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_A_DPD_A_IMD, E_HW_SYS_PARA_TYPE, "a_dpd_a_imd", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_A_DPD_R_SNR, E_HW_SYS_PARA_TYPE, "a_dpd_r_snr", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_A_DPD_R_IMD, E_HW_SYS_PARA_TYPE, "a_dpd_r_imd", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_A_DPD_C_T, E_HW_SYS_PARA_TYPE, "a_dpd_c_t", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_A_DPD_USE_DPD, E_HW_SYS_PARA_TYPE, "a_dpd_dpd", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_AD3_POWER_REF_H, E_HW_SYS_PARA_TYPE, "ad3_pwr_ref_h", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_AD3_POWER_REF_L, E_HW_SYS_PARA_TYPE, "ad3_pwr_ref_l", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_AD3_FWD_CAL, E_HW_SYS_PARA_TYPE, "ad3_fwd_cal", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_AD3_BITRATE_THRESHOLD_HH, E_HW_SYS_PARA_TYPE, "ad3_btrate_th_hh", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_AD3_BITRATE_THRESHOLD_HL, E_HW_SYS_PARA_TYPE, "ad3_btrate_th_hl", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_AD3_BITRATE_THRESHOLD_LH, E_HW_SYS_PARA_TYPE, "ad3_btrate_th_lh", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_AD3_BITRATE_THRESHOLD_LL, E_HW_SYS_PARA_TYPE, "ad3_btrate_th_ll", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_PA_IP4_ADDR , E_HW_SYS_PARA_TYPE, "pa_ip4", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_PA_GATEWAY_ADDR, E_HW_SYS_PARA_TYPE, "pa_gw", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_PA_NETMASK_ADDR, E_HW_SYS_PARA_TYPE, "pa_netmask", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_AGC_standard_addrH , E_HW_SYS_PARA_TYPE, "agc_std_h", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_AGC_standard_addrL , E_HW_SYS_PARA_TYPE, "agc_std_l", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_PWRVREF_O_HADDR, E_HW_SYS_PARA_TYPE, "pwr_ref0_h", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_PWRVREF_O_LADDR, E_HW_SYS_PARA_TYPE, "pwr_ref0_l", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_PWRVREF_VLDO_ADDR, E_HW_SYS_PARA_TYPE, "pwr_vld0", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DPD_DISTORTION_SW, E_HW_SYS_PARA_TYPE, "dpd_distortion_sw", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DPD_AGC_PWR_L, E_HW_SYS_PARA_TYPE, "dpd_agc_pwr_l", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DPD_AGC_PWR_H, E_HW_SYS_PARA_TYPE, "dpd_agc_pwr_h", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DPD_ERR_TH_L, E_HW_SYS_PARA_TYPE, "dpd_err_th_l", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DPD_ERR_TH_H, E_HW_SYS_PARA_TYPE, "dpd_err_th_h", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DPD_ERR_CNT_TH, E_HW_SYS_PARA_TYPE, "dpd_err_cnt_th", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DPD_AMP_SAT_TH_L, E_HW_SYS_PARA_TYPE, "dpd_amp_sat_th_l", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DPD_AMP_SAT_TH_H, E_HW_SYS_PARA_TYPE, "dpd_amp_sat_th_h", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DPD_TEST_L, E_HW_SYS_PARA_TYPE, "dpd_test_l", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DPD_TEST_H, E_HW_SYS_PARA_TYPE, "dpd_test_h", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DPD_STEP, E_HW_SYS_PARA_TYPE, "dpd_step", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DPD_FLASH_VALID, E_HW_SYS_PARA_TYPE, "dpd_flash_valid", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DPD_PHASE6_MINUTE, E_HW_SYS_PARA_TYPE, "dpd_stg6_minute", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DPD_WPP_TH_L, E_HW_SYS_PARA_TYPE, "dpd_wpp_th_l", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DPD_WPP_TH_H, E_HW_SYS_PARA_TYPE, "dpd_wpp_th_h", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_NOTICE_PART_END, E_HW_SYS_PARA_TYPE, "notice_end", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_ASI_ADDR_M , E_HW_SYS_PARA_TYPE, "asi_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_ADPC_ADDR_M, E_HW_SYS_PARA_TYPE, "adpc_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_GPS_ADDR_M, E_HW_SYS_PARA_TYPE, "gps_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_MON_ADDR_M, E_HW_SYS_PARA_TYPE, "mon_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_PWRVREF_H_ADDR_M, E_HW_SYS_PARA_TYPE, "pwrref_h_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_PWRVREF_L_ADDR_M, E_HW_SYS_PARA_TYPE, "pwrref_l_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_PWRVREF_VLDO_ADDR_M, E_HW_SYS_PARA_TYPE, "pwrref_vldo_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_CHANNEL_ADDR_M , E_HW_SYS_PARA_TYPE, "channel_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_RXFREQ_ADDR_M, E_HW_SYS_PARA_TYPE, "rxfreq_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_CW_ADDR_M, E_HW_SYS_PARA_TYPE, "cw_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_RF_ADDR_M, E_HW_SYS_PARA_TYPE, "rf_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_AGC_ADDR_M, E_HW_SYS_PARA_TYPE, "agc_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_0DBFLAGH_ADDR_M, E_HW_SYS_PARA_TYPE, "odbflag_h_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_0DBFLAGL_ADDR_M, E_HW_SYS_PARA_TYPE, "odbflag_l_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_POWER_UIH_ADDR_M, E_HW_SYS_PARA_TYPE, "pwr_uih_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_POWER_UIL_ADDR_M, E_HW_SYS_PARA_TYPE, "pwr_uil_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_HZ_H_ADDR_M, E_HW_SYS_PARA_TYPE, "hz_h_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_HZ_L_ADDR_M, E_HW_SYS_PARA_TYPE, "hz_l_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_NET_ADDR_M , E_HW_SYS_PARA_TYPE, "net_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DVBC_EN_ADDR_M, E_HW_SYS_PARA_TYPE, "dvbc_en_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_NET_FREQ_ADDR_M, E_HW_SYS_PARA_TYPE, "net_freq_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_QAM_ADDR_M, E_HW_SYS_PARA_TYPE, "qam_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_SYM_ADDR_M, E_HW_SYS_PARA_TYPE, "sys_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_INVER_ADDR_M, E_HW_SYS_PARA_TYPE, "inver_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_TXID_ADDR_M, E_HW_SYS_PARA_TYPE, "txid_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_AREA_ADDR_M, E_HW_SYS_PARA_TYPE, "area_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_TRANS_ADDR_M, E_HW_SYS_PARA_TYPE, "trans_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_SLOT_ADDR_M, E_HW_SYS_PARA_TYPE, "slot_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DLY_H_ADDR_M, E_HW_SYS_PARA_TYPE, "dly_h", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DLY_M_ADDR_M, E_HW_SYS_PARA_TYPE, "dly_m", 0, E_NORMAL_FILE_TYPE, }, { EEPROM_DLY_L_ADDR_M, E_HW_SYS_PARA_TYPE, "dly_l", 0, E_NORMAL_FILE_TYPE, }, //end {0, 0, "e",0, E_NULL_FILE_TYPE}, }; const S_PARA_IO_ELEMENT g_para_e2_map[65535] = { { E2_AD3_POWER_REF_H, E_HW_SYS_PARA_TYPE, "ad3_pwr_ref_h", 0, E_BKP1_FILE_TYPE, }, { E2_AD3_POWER_REF_L, E_HW_SYS_PARA_TYPE, "ad3_pwr_ref_l", 0, E_BKP1_FILE_TYPE, }, { E2_PWRVREF_O_HADDR, E_HW_SYS_PARA_TYPE, "pwr_ref0_h", 0, E_BKP1_FILE_TYPE, }, { E2_PWRVREF_O_LADDR, E_HW_SYS_PARA_TYPE, "pwr_ref0_l", 0, E_BKP1_FILE_TYPE, }, { E2_PWRVREF_VLDO_ADDR, E_HW_SYS_PARA_TYPE, "pwr_vld0", 0, E_BKP1_FILE_TYPE, }, { E2_AGC_ADDR, E_HW_SYS_PARA_TYPE, "agc", 0, E_BKP1_FILE_TYPE, }, { E2_POWER_UIH_ADDR, E_HW_SYS_PARA_TYPE, "e2power_ui_h", 0, E_BKP1_FILE_TYPE, }, { E2_POWER_UIL_ADDR, E_HW_SYS_PARA_TYPE, "e2power_ui_l", 0, E_BKP1_FILE_TYPE, }, { E2_0DBFLAGH_ADDR, E_HW_SYS_PARA_TYPE, "odb_flg_h", 0, E_BKP1_FILE_TYPE, }, { E2_0DBFLAGL_ADDR, E_HW_SYS_PARA_TYPE, "odb_flg_l", 0, E_BKP1_FILE_TYPE, }, { BAK_EEPROM_POWER_UIH_ADDR, E_HW_SYS_PARA_TYPE, "bak_power_ui_h", 0, E_BKP1_FILE_TYPE, }, { BAK_EEPROM_POWER_UIL_ADDR, E_HW_SYS_PARA_TYPE, "bak_power_ui_l", 0, E_BKP1_FILE_TYPE, }, { BAK_EEPROM_0DBFLAGH_ADDR, E_HW_SYS_PARA_TYPE, "bak_odb_flg_h", 0, E_BKP1_FILE_TYPE, }, { BAK_EEPROM_0DBFLAGL_ADDR, E_HW_SYS_PARA_TYPE, "bak_odb_flg_l", 0, E_BKP1_FILE_TYPE, }, { BAK_E2_POWER_UIH_ADDR, E_HW_SYS_PARA_TYPE, "bak_e2power_ui_h", 0, E_BKP1_FILE_TYPE, }, { BAK_E2_POWER_UIL_ADDR, E_HW_SYS_PARA_TYPE, "bak_e2power_ui_l", 0, E_BKP1_FILE_TYPE, }, { BAK_E2_0DBFLAGH_ADDR, E_HW_SYS_PARA_TYPE, "bak_e2odb_flg_h", 0, E_BKP1_FILE_TYPE, }, { BAK_E2_0DBFLAGL_ADDR, E_HW_SYS_PARA_TYPE, "bak_e2odb_flg_l", 0, E_BKP1_FILE_TYPE, }, { BAK_EEPROM_CHANNEL_ADDR, E_HW_SYS_PARA_TYPE, "bak_channel", 0, E_BKP1_FILE_TYPE, }, { BAK_EEPROM_RXCHANNEL_ADDR, E_HW_SYS_PARA_TYPE, "bak_rx_channel", 0, E_BKP1_FILE_TYPE, }, { BAK_EEPROM_POWER_UIH_ADDR_M, E_HW_SYS_PARA_TYPE, "bak_power_ui_h_m", 0, E_BKP1_FILE_TYPE, }, { BAK_EEPROM_POWER_UIL_ADDR_M, E_HW_SYS_PARA_TYPE, "bak_power_ui_l_m", 0, E_BKP1_FILE_TYPE, }, { BAK_EEPROM_0DBFLAGH_ADDR_M, E_HW_SYS_PARA_TYPE, "bak_odb_flg_h_m", 0, E_BKP1_FILE_TYPE, }, { BAK_EEPROM_0DBFLAGL_ADDR_M, E_HW_SYS_PARA_TYPE, "bak_odb_flg_l_m", 0, E_BKP1_FILE_TYPE, }, { BAK_E2_POWER_UIH_ADDR_M, E_HW_SYS_PARA_TYPE, "bak_e2power_ui_h_m", 0, E_BKP1_FILE_TYPE, }, { BAK_E2_POWER_UIL_ADDR_M, E_HW_SYS_PARA_TYPE, "bak_e2power_ui_l_m", 0, E_BKP1_FILE_TYPE, }, { BAK_E2_0DBFLAGH_ADDR_M, E_HW_SYS_PARA_TYPE, "bak_e2odb_flg_h_m", 0, E_BKP1_FILE_TYPE, }, { BAK_E2_0DBFLAGL_ADDR_M, E_HW_SYS_PARA_TYPE, "bak_e2odb_flg_l_m", 0, E_BKP1_FILE_TYPE, }, { BAK_EEPROM_CHANNEL_ADDR_M, E_HW_SYS_PARA_TYPE, "bak_channel_m", 0, E_BKP1_FILE_TYPE, }, { BAK_EEPROM_RXCHANNEL_ADDR_M, E_HW_SYS_PARA_TYPE, "bak_rx_channel_m", 0, E_BKP1_FILE_TYPE, }, //end {0, 0, "e", 0, E_NULL_FILE_TYPE}, }; const S_PARA_IO_ELEMENT g_para_e3_map[65535] = { //end {0, 0, "e", 0, E_NULL_FILE_TYPE}, }; #endif //map #if 0 static uint8 get_e1_para_from_file(uint16 para_id,const S_PARA_IO_ELEMENT *pmap, uint16 map_ele_num, char *pfile) { uint16 i; uint32 u32val; char sname[30]={0}; //const S_PARA_IO_ELEMENT *pmap = &g_para_e1_map[0]; for(i=0;ipara_id == para_id){ if(pmap->para_type == E_HW_SYS_PARA_TYPE){ u32val = (uint32)ini_getl(STR_HW_SYS_PARA_TYPE, pmap->para_name, DEF_REG_PARA, F_EXC_CFG_PARA_FILE); } else if(pmap->para_type == E_LCD_SYS_PARA_TYPE){ u32val = (uint32)ini_getl(STR_LCD_SYS_PARA_TYPE, pmap->para_name, DEF_REG_PARA, F_EXC_CFG_PARA_FILE); } else{ u32val = (uint32)ini_getl(STR_HW_SYS_PARA_TYPE, pmap->para_name, DEF_REG_PARA, F_EXC_CFG_PARA_FILE); } return (uint8)u32val; } i++; pmap = &g_para_e1_map[i]; } sprintf(sname,"reg%d",para_id); u32val = (uint32)ini_getl(STR_BLK_SYS_PARA_TYPE, sname, DEF_REG_PARA, F_EXC_CFG_PARA_FILE); printf("Note.e1_map para not match for read.\n\n"); } static uint8 get_e2_para_from_file(uint16 para_id) { uint16 i; uint32 u32val; char sname[30]={0}; const S_PARA_IO_ELEMENT *pmap = &g_para_e2_map[0]; for(i=0;ipara_id == para_id){ if(pmap->para_type == E_HW_SYS_PARA_TYPE){ u32val = (uint32)ini_getl(STR_HW_SYS_PARA_TYPE, pmap->para_name, DEF_REG_PARA, F_EXC_CFG_PARA_BKP1_FILE); } else if(pmap->para_type == E_LCD_SYS_PARA_TYPE){ u32val = (uint32)ini_getl(STR_LCD_SYS_PARA_TYPE, pmap->para_name, DEF_REG_PARA, F_EXC_CFG_PARA_BKP1_FILE); } else{ u32val = (uint32)ini_getl(STR_HW_SYS_PARA_TYPE, pmap->para_name, DEF_REG_PARA, F_EXC_CFG_PARA_BKP1_FILE); } return (uint8)u32val; } i++; pmap = &g_para_e2_map[i]; } sprintf(sname,"reg%d",para_id); u32val = (uint32)ini_getl(STR_BLK_SYS_PARA_TYPE, sname, DEF_REG_PARA, F_EXC_CFG_PARA_FILE); printf("Err.e2_map para not match for read.\n\n"); } static uint8 get_e3_para_from_file(uint16 para_id) { uint16 i; uint32 u32val; char sname[30]={0}; const S_PARA_IO_ELEMENT *pmap = &g_para_e3_map[0]; for(i=0;ipara_id == para_id){ if(pmap->para_type == E_HW_SYS_PARA_TYPE){ u32val = (uint32)ini_getl(STR_HW_SYS_PARA_TYPE, pmap->para_name, DEF_REG_PARA, F_EXC_CFG_PARA_BKP2_FILE); } else if(pmap->para_type == E_LCD_SYS_PARA_TYPE){ u32val = (uint32)ini_getl(STR_LCD_SYS_PARA_TYPE, pmap->para_name, DEF_REG_PARA, F_EXC_CFG_PARA_BKP2_FILE); } else{ u32val = (uint32)ini_getl(STR_HW_SYS_PARA_TYPE, pmap->para_name, DEF_REG_PARA, F_EXC_CFG_PARA_BKP2_FILE); } return (uint8)u32val; } i++; pmap = &g_para_e3_map[i]; } sprintf(sname,"reg%d",para_id); u32val = (uint32)ini_getl(STR_BLK_SYS_PARA_TYPE, sname, DEF_REG_PARA, F_EXC_CFG_PARA_FILE); printf("Err.e3_map para not match for read.\n\n"); } #endif static uint8 get_e_para_from_file(uint16 para_id,const S_PARA_IO_ELEMENT *pe_map, uint16 map_ele_num, char *pfile) { uint32 u32val = 0; char sname[30] = {0}; sprintf(sname, "reg%d", para_id); u32val = (uint32)ini_getl(STR_BLK_SYS_PARA_TYPE, sname, DEF_REG_PARA, F_EXC_CFG_PARA_FILE); return (uint8)u32val; } static uint8 get_e_para_from_file_v2(uint16 para_id, uint8 default_val, char *pfile) { uint32 u32val = 0; char sname[30] = {0}; sprintf(sname, "reg%d", para_id); u32val = (uint32)ini_getl(STR_BLK_SYS_PARA_TYPE, sname, default_val, F_EXC_CFG_PARA_FILE); return (uint8)u32val; } uint8 get_para_from_e_map(uint16 para_id, uint8 chip) { uint32 data = 0; if(chip==E2_CHIP_1){ data = get_e_para_from_file(para_id, NULL, 0, F_EXC_CFG_PARA_FILE); } else if(chip==E2_CHIP_2){ data = get_e_para_from_file(para_id, NULL, 0, F_EXC_CFG_PARA_BKP1_FILE); } else if(chip==E2_CHIP_3){ data = get_e_para_from_file(para_id, NULL, 0, F_EXC_CFG_PARA_BKP2_FILE); } else{ log_printf(LOG_DEBUG,I_NOUSED,"chip num not match for read.\n\n"); } return data; } uint8 get_para_from_e_map_v2(uint16 para_id, uint8 default_val, uint8 chip) { uint32 data = 0; if(chip==E2_CHIP_1){ data = get_e_para_from_file_v2(para_id, default_val, F_EXC_CFG_PARA_FILE); } else if(chip==E2_CHIP_2){ data = get_e_para_from_file_v2(para_id, default_val, F_EXC_CFG_PARA_BKP1_FILE); } else if(chip==E2_CHIP_3){ data = get_e_para_from_file_v2(para_id, default_val, F_EXC_CFG_PARA_BKP2_FILE); } else{ log_printf(LOG_DEBUG,I_NOUSED,"chip num not match for read.\n\n"); } return data; } static int set_e_para_to_file(uint16 para_id, uint8 para_val, const S_PARA_IO_ELEMENT *pe_map, uint16 map_ele_num, char *pfile) { uint16 i; uint32 u32val; int ret=0; char sname[30]={0}; sprintf(sname,"reg%d",para_id); ret = ini_putl(STR_BLK_SYS_PARA_TYPE, sname, para_val, pfile); if(ret!=1){ log_printf(LOG_ERR,I_NOUSED,"e_map para write failed.\n\n"); } return ret; } int set_para_to_e_map(uint16 para_id, uint8 para_val, uint8 chip) { int ret=0; if(chip==E2_CHIP_1){ ret = set_e_para_to_file(para_id, para_val, NULL, 0, F_EXC_CFG_PARA_FILE); } else if(chip==E2_CHIP_2){ ret = set_e_para_to_file(para_id, para_val, NULL, 0, F_EXC_CFG_PARA_BKP1_FILE); } else if(chip==E2_CHIP_3){ ret = set_e_para_to_file(para_id, para_val, NULL, 0, F_EXC_CFG_PARA_BKP2_FILE); } else{ log_printf(LOG_ERR,I_NOUSED,"chip num not match for write.\n\n"); } return ret; }