/** * \file talise_config.c * \brief Contains Talise configuration settings for the Talise API * * Copyright 2015-2017 Analog Devices Inc. * Released under the AD9378-AD9379 API license, for more information see the "LICENSE.txt" file in this zip file. * * The top level structure taliseDevice_t talDevice uses keyword * extern to allow the application layer main() to have visibility * to these settings. * * This file may not be fully complete for the end user application and * may need to updated for AGC, GPIO, and DAC full scale settings. * To create a full initialisation routine, the user should also refer to the * Iron Python initialisation routine generated by the GUI, and also the Talise User Guide. * */ //#include "talise_types.h" //#include "talise_config_1.h" //#include "talise_error.h" //#include "talise_agc.h" #ifdef ADI_ZYNQ_PLATFORM #include "zynq_platform.h" #endif #include "talise_config.h" #if 1//_HJX_CONFIG_ modify static int16_t txFirCoefs[80] = {0, 0, 0, 0, 0, 0, 1, 0, -3, 1, 8, -2, -20, 5, 43, -10, -85, 19, 158, -34, -272, 61, 463, -62, -702, 71, 1044, -36, -1482, -64, 2044, 302, -2770, -803, 3786, 1895, -5503, -4768, 10723, 27650, 27650, 10723, -4768, -5503, 1895, 3786, -803, -2770, 302, 2044, -64, -1482, -36, 1044, 71, -702, -62, 463, 61, -272, -34, 158, 19, -85, -10, 43, 5, -20, -2, 8, 1, -3, 0, 1, 0, 0, 0, 0, 0, 0}; static int16_t rxFirCoefs[72] = {0, 0, -1, -2, -4, -2, 5, 17, 27, 21, -12, -67, -114, -105, -2, 181, 354, 375, 133, -350, -858, -1043, -606, 462, 1737, 2456, 1880, -215, -3172, -5492, -5359, -1489, 6092, 15765, 24755, 30169, 30169, 24755, 15765, 6092, -1489, -5359, -5492, -3172, -215, 1880, 2456, 1737, 462, -606, -1043, -858, -350, 133, 375, 354, 181, -2, -105, -114, -67, -12, 21, 27, 17, 5, -2, -4, -2, -1, 0, 0}; static int16_t obsrxFirCoefs[72] = {-3, 10, 15, 8, -18, -41, -29, 29, 86, 76, -29, -154, -166, 1, 239, 316, 83, -328, -541, -260, 393, 856, 581, -393, -1287, -1145, 236, 1855, 2111, 196, -2816, -4260, -1648, 5281, 13824, 19693, 19693, 13824, 5281, -1648, -4260, -2816, 196, 2111, 1855, 236, -1145, -1287, -393, 581, 856, 393, -260, -541, -328, 83, 316, 239, 1, -166, -154, -29, 76, 86, 29, -29, -41, -18, 8, 15, 10, -3}; /* PR06-2: TES 120M obsRx 72抽头(相干) */ #ifdef ADI_ZYNQ_PLATFORM /** < Insert Customer Platform HAL State Container here>*/ /* * Platform Layer SPI settings - this structure is specific to ADI's platform layer code. * User should replace with their own structure or settings for their hardware */ zynqSpiSettings_t spiDev1 = { .chipSelectIndex = 1, .writeBitPolarity = 0, .longInstructionWord = 1, .CPHA = 0, .CPOL = 0, .mode = 0, .spiClkFreq_Hz = 25000000 }; /* * Platform Layer settings - this structure is specific to ADI's platform layer code. * User should replace with their own structure or settings for their hardware * The structure is held in taliseDevice_t below as a void pointer, allowing * the customer to pass any information for their specific hardware down to the * hardware layer code. */ zynqAdiDev_t talDevHalInfo = { .devIndex = 1, .spiSettings = &spiDev1, .spiErrCode = 0, .timerErrCode = 0, .gpioErrCode = 0, .logLevel = ADIHAL_LOG_ALL }; #endif /** * TalDevice a structure used by the Talise API to hold the platform hardware * structure information, as well as an internal Talise API state container * (devStateInfo) of runtime information used by the API. **/ //--------------------------------------- #define SCRAMBLE_USR 0 //--------------------------------------- static taliseInit_t talInit = {//ref_from 7g 2lan start /* SPI settings */ .spiSettings = { .MSBFirst = 1, /* 1 = MSBFirst, 0 = LSBFirst */ .enSpiStreaming = 0, /* Not implemented in ADIs platform layer. SW feature to improve SPI throughput */ .autoIncAddrUp = 1, /* Not implemented in ADIs platform layer. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr=addr-1 */ .fourWireMode = 1, /* 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode */ .cmosPadDrvStrength = TAL_CMOSPAD_DRV_2X /* Drive strength of CMOS pads when used as outputs (SDIO, SDO, GP_INTERRUPT, GPIO 1, GPIO 0) */ }, /* Rx settings */ .rx = { .rxProfile = { .rxFir = { .gain_dB = -6, /* filter gain */ .numFirCoefs = 72, /* number of coefficients in the FIR filter */ .coefs = &rxFirCoefs[0] }, .rxFirDecimation = 4, /* Rx FIR decimation (1,2,4) - PR06-2: 4 for 60M out */ .rxDec5Decimation = 4, /* Decimation of Dec5 or Dec4 filter (5,4) */ .rhb1Decimation = 2, /* RX Half band 1 decimation (1 or 2) */ .rxOutputRate_kHz = 60000, /* Rx IQ data rate in kHz - PR06-2: 120->60M */ .rfBandwidth_Hz = 30000000, /* The Rx RF passband bandwidth for the profile - PR06-2: 60->30M */ .rxBbf3dBCorner_kHz = 100000, /* Rx BBF 3dB corner in kHz */ .rxAdcProfile = {272, 150, 181, 90, 1280, 366, 1256, 27, 1228, 17, 701, 39, 48, 45, 27, 161, 0, 0, 0, 0, 40, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905}, /* pointer to custom ADC profile */ .rxDdcMode = TAL_RXDDC_BYPASS, /* Rx DDC mode */ .rxNcoShifterCfg = { .bandAInputBandWidth_kHz = 0, .bandAInputCenterFreq_kHz = 0, .bandANco1Freq_kHz = 0, .bandANco2Freq_kHz = 0, .bandBInputBandWidth_kHz = 0, .bandBInputCenterFreq_kHz = 0, .bandBNco1Freq_kHz = 0, .bandBNco2Freq_kHz = 0 } }, .framerSel = TAL_FRAMER_A, /* Rx JESD204b framer configuration */ .rxGainCtrl = { .gainMode = TAL_MGC, /* taliserxGainMode_t gainMode */ .rx1GainIndex = 210, /* PR06-2: 降增益去饱和(255满量程削顶); 电缆TX信号强 */ .rx2GainIndex = 255, /* uint8_t rx2GainIndex */ .rx1MaxGainIndex = 255, /* uint8_t rx1MaxGainIndex */ .rx1MinGainIndex = 195, /* uint8_t rx1MinGainIndex (gain table hard floor) */ .rx2MaxGainIndex = 255, /* uint8_t rx2MaxGainIndex */ .rx2MinGainIndex = 195 /* uint8_t rx2MinGainIndex */ }, .rxChannels = TAL_RX1, /* PR06-2 统一M=2: 1通道RX1(匹配TES profile Rx_OR60 + DTMB). RX1 I/Q 从 o_fb tdata[31:0] 提取 */ }, /* Tx settings */ .tx = { .txProfile = { .dacDiv = 1, /* The divider used to generate the DAC clock */ .txFir = { .gain_dB = 0, /* filter gain */ .numFirCoefs = 80, /* number of coefficients in the FIR filter - PR06-2: 20->80 (TES 120M) */ .coefs = &txFirCoefs[0] }, .txFirInterpolation = 2, /* The Tx digital FIR filter interpolation (1,2,4) - PR06-2: 1->2 for 120M in */ .thb1Interpolation = 2, /* Tx Halfband1 filter interpolation (1,2) */ .thb2Interpolation = 2, /* Tx Halfband2 filter interpolation (1,2)*/ .thb3Interpolation = 2, /* Tx Halfband3 filter interpolation (1,2)*/ .txInt5Interpolation = 1, /* Tx Int5 filter interpolation (1,5) */ .txInputRate_kHz = 120000, /* Primary Signal BW - PR06-2: 240->120M */ .primarySigBandwidth_Hz = 40000000, /* The Rx RF passband bandwidth for the profile - PR06-2: 60->40M */ .rfBandwidth_Hz = 80000000, /* The Tx RF passband bandwidth for the profile - PR06-2: 120->80M */ .txDac3dBCorner_kHz = 200000, /* The DAC filter 3dB corner in kHz */ .txBbf3dBCorner_kHz = 100000, /* The BBF 3dB corner in kHz */ .loopBackAdcProfile = {269, 149, 181, 90, 1280, 378, 1258, 28, 1235, 17, 710, 39, 48, 45, 27, 163, 0, 0, 0, 0, 41, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905} }, .deframerSel = TAL_DEFRAMER_A, /* Talise JESD204b deframer config for the Tx data path */ .txChannels = TAL_TX1, /* The desired Tx channels to enable during initialization */ .txAttenStepSize = TAL_TXATTEN_0P05_DB, /* Tx Attenuation step size */ .tx1Atten_mdB = 0, /* PR06-2 修复②: TX满功率(同260702), 强化ORx环回观测 */ .tx2Atten_mdB = 0, /* Initial Tx2 Attenuation */ .disTxDataIfPllUnlock = TAL_TXDIS_TX_RAMP_DOWN_TO_ZERO /* Options to disable the transmit data when the RFPLL unlocks. */ }, /* ObsRx settings */ .obsRx = { .orxProfile = { .rxFir = { .gain_dB = 0, /* PR06-2 修复③: obsRx FIR gain 0(同260702), 补回6dB数字增益 */ .numFirCoefs = 72, /* PR06-2: TES 120M obsRx 72抽头 */ .coefs = &obsrxFirCoefs[0] }, .rxFirDecimation = 2, /* Rx FIR decimation (1,2,4) */ .rxDec5Decimation = 4, /* Decimation of Dec5 or Dec4 filter (5,4) */ .rhb1Decimation = 2, /* PR06-2: HB1 dec2 (120M out, 2.4G GT) */ .orxOutputRate_kHz = 120000, /* PR06-2: ORx 120M (2.4G GT) */ .rfBandwidth_Hz = 60000000, /* The Rx RF passband bandwidth for the profile */ .rxBbf3dBCorner_kHz = 225000, /* Rx BBF 3dB corner in kHz */ .orxLowPassAdcProfile = {272, 150, 181, 90, 1280, 366, 1256, 27, 1228, 17, 701, 39, 48, 45, 27, 161, 0, 0, 0, 0, 40, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905}, .orxBandPassAdcProfile = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, .orxDdcMode = TAL_ORXDDC_DISABLED, /* ORx DDC mode */ .orxMergeFilter = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, .orxGainCtrl = { .gainMode = TAL_MGC, .orx1GainIndex = 255, .orx2GainIndex = 255, .orx1MaxGainIndex = 255, .orx1MinGainIndex = 195, .orx2MaxGainIndex = 255, .orx2MinGainIndex = 195 }, .framerSel = TAL_FRAMER_B, /* ObsRx JESD204b framer configuration */ .obsRxChannelsEnable = TAL_ORX1, /* PR06-2 ORx模式(golden): ORx1 观测 TX */ .obsRxLoSource = TAL_OBSLO_RF_PLL /* The ORx mixers can use the TX_PLL */ }, /* Digital Clock Settings */ .clocks = { .deviceClock_kHz = 120000, /* CLKPLL and device reference clock frequency in kHz */ .clkPllVcoFreq_kHz = 9600000, /* CLKPLL VCO frequency in kHz */ .clkPllHsDiv = TAL_HSDIV_2P5, /* CLKPLL high speed clock divider */ .rfPllUseExternalLo = 0, /* 1= Use external LO for RF PLL, 0 = use internal LO generation for RF PLL */ .rfPllPhaseSyncMode = TAL_RFPLLMCS_NOSYNC /* RFPLL MCS (Phase sync) mode */ }, /* JESD204B settings */ .jesd204Settings = { /* Framer A settings */ .framerA = { .bankId = 1, /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15) */ .deviceId = 0, /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */ .lane0Id = 0, /* JESD204B Configuration starting Lane ID. If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */ .M = 2, /* PR06-2 统一M=2(匹配TES profile Rx_OR60 + FB核C_DEFAULT_F=2 + DTMB). o_fb tdata[15:0]=RX1_I,[31:16]=RX1_Q */ .K = 32, /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */ .F = 4, /* PR06-2 ORx模式(DTMB): framerA M=2/1lane(0x04) -> F=4, 让位给framerB */ .Np = 16, /* Np (converter sample resolution) */ .scramble = SCRAMBLE_USR, /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */ .externalSysref = 0, /* 0=use internal SYSREF, 1= use external SYSREF (SMOD: NO external SYSREF wired) */ .serializerLanesEnabled = 0x04, /* PR06-2 ORx-only: framerA/RX1 到 lane2(未接线, 关闭), 让出 SERDOUT0/1 给 framerB/ORx */ .serializerLaneCrossbar = 0xE4, /* serializerLaneCrossbar */ .lmfcOffset = 31, /* lmfcOffset - LMFC offset value for deterministic latency setting */ .newSysrefOnRelink = 0, /* newSysrefOnRelink */ .syncbInSelect = 0, /* syncbInSelect; */ .overSample = 0, /* 1=overSample, 0=bitRepeat */ .syncbInLvdsMode = 1, .syncbInLvdsPnInvert = 0, .enableManualLaneXbar = 0 /* 0=auto, 1=manual */ }, /* Framer B settings */ .framerB = { .bankId = 0, /* golden ORx */ .deviceId = 0, /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */ .lane0Id = 0, /* JESD204B Configuration starting Lane ID. If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */ .M = 2, /* PR06-2 ORx-only: ORx M=2 (o_fb tdata[15:0]=ORx1_I,[31:16]=ORx1_Q) */ .K = 32, /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */ .F = 2, /* PR06-2 ORx-only: F=2 (M=2/2lane, 120M) */ .Np = 16, /* Np (converter sample resolution) */ .scramble = SCRAMBLE_USR, /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */ .externalSysref = 0, /* 0=use internal SYSREF (SMOD: NO external SYSREF wired) */ .serializerLanesEnabled = 0x03, /* PR06-2 ORx-only: framerB/ORx 用 SERDOUT0/1(2 lane, 120M) */ .serializerLaneCrossbar = 0xE4, /* serializerLaneCrossbar */ .lmfcOffset = 31, /* lmfcOffset - LMFC offset value for deterministic latency setting */ .newSysrefOnRelink = 0, /* newSysrefOnRelink */ .syncbInSelect = 1, /* golden ORx: syncbInSelect=1 */ .overSample = 0, /* 1=overSample, 0=bitRepeat */ .syncbInLvdsMode = 1, .syncbInLvdsPnInvert = 0, .enableManualLaneXbar = 0 /* 0=auto, 1=manual */ }, /* Deframer A settings */ .deframerA = { .bankId = 0, /* bankId extension to Device ID (Valid 0..15) */ .deviceId = 0, /* deviceId link identification number. (Valid 0..255) */ .lane0Id = 0, /* lane0Id Lane0 ID. (Valid 0..31) */ .M = 2, /* M number of DACss (0, 2, or 4) - 2 DACs per transmit chain */ .K = 32, /* K #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */ .scramble = SCRAMBLE_USR, /* scramble scrambling off if scramble= 0 */ .externalSysref = 0, /* 0=use internal SYSREF (SMOD: NO external SYSREF wired) */ .deserializerLanesEnabled = 0x03, /* deserializerLanesEnabled bit per lane, [0] = Lane0 enabled */ .deserializerLaneCrossbar = 0xE4, /* deserializerLaneCrossbar */ .lmfcOffset = 17, /* lmfcOffset LMFC offset value to adjust deterministic latency */ .newSysrefOnRelink = 0, /* newSysrefOnRelink */ .syncbOutSelect = 0, /* SYNCBOUT0/1 select */ .Np = 16, /* Np (converter sample resolution) */ .syncbOutLvdsMode = 1, .syncbOutLvdsPnInvert = 0, .syncbOutCmosSlewRate = 0, .syncbOutCmosDriveLevel = 0, .enableManualLaneXbar = 0 /* 0=auto, 1=manual */ }, /* Deframer B settings */ .deframerB = { .bankId = 0, /* bankId extension to Device ID (Valid 0..15) */ .deviceId = 0, /* deviceId link identification number. (Valid 0..255) */ .lane0Id = 0, /* lane0Id Lane0 ID. (Valid 0..31) */ .M = 0, /* M number of DACss (0, 2, or 4) - 2 DACs per transmit chain */ .K = 32, /* K #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */ .scramble = SCRAMBLE_USR, /* scramble scrambling off if scramble= 0 */ .externalSysref = 1, /* externalSysref 0= use internal SYSREF, 1= external SYSREF */ .deserializerLanesEnabled = 0x00, /* deserializerLanesEnabled bit per lane, [0] = Lane0 enabled */ .deserializerLaneCrossbar = 0xE4, /* deserializerLaneCrossbar */ .lmfcOffset = 0, /* lmfcOffset LMFC offset value to adjust deterministic latency */ .newSysrefOnRelink = 0, /* newSysrefOnRelink */ .syncbOutSelect = 1, /* SYNCBOUT0/1 select */ .Np = 16, /* Np (converter sample resolution) */ .syncbOutLvdsMode = 1, .syncbOutLvdsPnInvert = 0, .syncbOutCmosSlewRate = 0, .syncbOutCmosDriveLevel = 0, .enableManualLaneXbar = 0 /* 0=auto, 1=manual */ }, .serAmplitude = 15, /* Serializer amplitude setting. Default = 15. Range is 0..15 */ .serPreEmphasis = 1, /* Serializer pre-emphasis setting. Default = 1 Range is 0..4 */ .serInvertLanePolarity = 0, /* Serializer Lane PN inversion select. Default = 0. Where, bit[0] = 1 will invert lane [0], bit[1] = 1 will invert lane 1, etc. */ .desInvertLanePolarity = 0, /* Deserializer Lane PN inversion select. bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc */ .desEqSetting = 1, /* Deserializer Equalizer setting. Applied to all deserializer lanes. Range is 0..4 */ .sysrefLvdsMode = 1, /* Use LVDS inputs on Talise for SYSREF */ .sysrefLvdsPnInvert = 0 /*0= Do not PN invert SYSREF */ } }; #endif //ref_from 7g 2lan end //Only needs to be called if user wants to setup AGC parameters static taliseAgcCfg_t rxAgcCtrl = { 4, 255, 195, 255, 195, 30720, /* AGC gain update time in us (125us-250us - based on IQ data rate - set for 125us @ 245.76 Mhz) */ 10, 10, 16, 0, 1, 0, 0, 0, 1, 31, 246, 4, 1, /*!<1- bit field to enable the multiple time constants in AGC loop for fast attack and fast recovery to max gain. */ /* agcPower */ { 1, /*!<1-bit field, enables the Rx power measurement block. */ 1, /*!<1-bit field, allows using Rx PFIR for power measurement. */ 0, /*!<1-bit field, allows to use the output of the second digital offset block in the Rx datapath for power measurement. */ 9, /*!*/ #endif #else .devHalInfo = &chipSelectIndex, #endif /* devStateInfo is maintained internal to the Talise API, just create the memory */ .devStateInfo = {0} }; taliseDeviceInfo taliseDeviceInfo1 = { .ptalDevice = &talDevice, .ptalInit = &talInit };