240 lines
6.0 KiB
C
Executable File
240 lines
6.0 KiB
C
Executable File
#ifndef _DPD_PROC_H_
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#define _DPD_PROC_H_
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#include "type.h"
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#define DPD_LOG_ENABLE 1
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#define DPD_LOG_FILE "/aw/anywave/dpd_log/log"
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#define FPGA_ADDR_DPD_LOG_TRIG 0x15
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//----Write Only--------------
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//ok
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#define FPGA_ADDR_DPD_CTRL1 0x20
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#define FPGA_ADDR_DPD_CTRL2 0x21
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#define FPGA_ADDR_DPD_CTRL3 0x22
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//ok
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#define FPGA_ADDR_DPD_IQB_UPD 0x23
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#define FPGA_ADDR_DPD_CFG_STEP 0x24
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//wpp
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#define FPGA_ADDR_WPP_EN_CLR 0x0d
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#define FPGA_ADDR_WPP_TH_L 0x0e
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#define FPGA_ADDR_WPP_TH_H 0x0f
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#define MASK_WPP_ENABLE (1)
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#define MASK_WPP_CLR (1<<1)
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//#define FPGA_ADDR_DPD_SYNCOFFSET ??
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#define FPGA_ADDR_DPD_TEST_L 0x02
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#define FPGA_ADDR_DPD_TEST_H 0x03
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//----Read Only--------------
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#define FPGA_ADDR_DPD_STATUS1 0x01
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//---------------------------
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#define MASK_RFAGC_DOWN_LIMIT (1<<1)
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#define MASK_RFAGC_UP_LIMIT (1<<2)
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#define SPI_BLK_LEN 35//Byte
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enum{
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E_RFAGC_NORMAL=0,
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E_RFAGC_DOWN_LIMIT,
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E_RFAGC_UP_LIMIT,
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}E_AGC_ERR_CODE;
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/*
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E_RFAGC_POWER_LOW,
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E_RFAGC_POWER_HIGH,
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*/
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//ok
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#define MASK_DPD_ERR (0x0001)
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#define MASK_DPD_PWRHIGH (0x0001<<1)
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#define MASK_DPD_PWRLOW (0x0001<<2)
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#define MASK_DPD_DAGC_TOOHIGH (0x0001<<3)
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#define MASK_DPD_DAGC_TOOLOW (0x0001<<4)
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#define MASK_DPD_ERR_ABORT (0x0001<<5)
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#define MASK_DPD_TRX_SYNC_OK (0x0001<<6)
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#define MASK_DPD_SAT_FLG (0x0001<<7)
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//ok
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#define DPD_CTRL1_DPD_START (0x0001)
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#define DPD_CTRL1_DPD_ALLCLR (0x0001<<1)
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#define DPD_CTRL1_ALL_BYPS (0x0001<<2)
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#define DPD_CTRL2_LIN_UPDATE (0x0001)
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#define DPD_CTRL2_NONLIN_UPDATE (0x0001<<1)
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#define DPD_CTRL2_SET_NONLIN_UDP_MOD(x) (((x)&0x03)<<2) /*01 : POLY; 10: CRST*/
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#define DPD_CTRL2_AMP_CHK (0x0001<<4)
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#define DPD_CTRL2_PRL_UPDATE (0x0001<<5)
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#define DPD_CTRL2_RXEQ_UPDATE (0x0001<<6)
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#define DPD_CTRL2_POLYESTI_UPDATE (0x0001<<7)
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//ok
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#define INTER_DISTORTION_SW_MAX (7)
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//ok
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#define DPD_CTRL3_FAGC_UPDATE (0x0001)
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#define DPD_CTRL3_FAGC_SLOWDN (0x0001<<1)
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#define DPD_CTRL3_DAGC_UPDATE (0x0001<<2)
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#define DPD_CTRL3_DAGC_SLOWDN (0x0001<<3)
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#define DPD_CTRL3_DCRM_UPDATE (0x0001<<4)
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#define DPD_CTRL3_ROT_UPDATE (0x0001<<5)
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#define DPD_CTRL3_SYNC_UPDATE (0x0001<<6)
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#define DPD_CTRL3_SYNC_RESTART (0x0001<<7)
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//ok
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#define DPD_IQB_UPDATE (0x0001)
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#define DPD_IQB_BP_MASK (0x0001<<1)
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//#define DPD_IQB_SYNC_MASK (0x0001<<2)
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#define DPD_SYNC_MODE_MASK (0x0001<<2)
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#define DPD_RF_SEL_BEFORE (0x0001<<3)
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#define DPD_SET_100M (0x00)
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#define DPD_SET_25M (0x01)
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#define SET_DPDFAGC_REFPWR(x) ((x))
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#define DPD_SET_CRST_ADDR_STRUCT_2 ((0x01)<<17)
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#define DPD_SET_ERR_TH(x) (((x)&0xffff))
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#define DPD_SET_ERR_CNT_TH(x) (((x)&0xff)<<16)
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#define DPD_SET_DGAIN(x) (((x)&0xffff)<<2)
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#define DPD_SET_FIX_DLY(x) (0x8000 & ((x)&0x7ff))
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#define DPD_SET_CRST_REFAD(x) ((x)[0] | ((x)[1]<<4) | ((x)[2]<<8) | ((x)[3]<<12) | ((x)[4]<<16) | ((x)[5]<<20))
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#define DPD_MAX_TX_AMP_SAT 65535
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//#define TX_FREQ_IN_HZ 2550000000
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#define DPD_SEG 5
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#define MASK_DPD_DATA_AREA0_MODE ((1)&0xff)
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#define MASK_DPD_DATA_AREA1_MODE ((1<<1)&0xff)
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#define MASK_DPD_DATA_AREA2_MODE ((1<<2)&0xff)
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#define MASK_DPD_DATA_AREA3_MODE ((1<<3)&0xff)
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//#define MASK_TO_FPGA_WRITE_ENABLE ((1))
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#define MASK_TO_SPI_WR_RD_ENABLE (1)
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#define MASK_TO_FPGA_REFRESH_DATA (1<<1)
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#define MASK_TO_FPGA_CHECK_CLEAR (1<<2)
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enum{E_CHECK_FOR_RAED=0, E_CHECK_FOR_WIRTE=1};
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typedef struct{
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u32 area_fpga_w_check;
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u32 area_fpga_r_check;
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u32 area_imx_w_check;
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u32 area_imx_r_check;
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}S_CHECK_SUM;
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//--------------------------------------------
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/*Add Bit Ctrl*/
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typedef struct{
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uint8 iqb_upd:1;
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uint8 iqb_bp:1;
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uint8 sync_mode:1; /* !! sync_mode 与 re_sel 相反 */
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uint8 rf_sel:1; /* !! sync_mode 与 re_sel 相反 */
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}S_DPD_REG23;
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typedef union
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{
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S_DPD_REG23 dpd_bt;
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uint8 u8val;
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}U_DPDCTL_REG23;
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#define TSNR_FIX 3.5*100
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enum{E_READ=0,E_WRITE=1};
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typedef enum
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{
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DPD_STATE_OK=0,
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DPD_STATE_ERR=0x10,
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DPD_STATE_POWER_HIGH,
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DPD_STATE_POWER_LOW,
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DPD_STATE_POWER_TOO_HIGH,
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DPD_STATE_POWER_TOO_LOW,
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DPD_STATE_ERR_OVER_RANGE,
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DPD_STATE_SYNC_OK,
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DPD_READ_CKECK_ERR,
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DPD_WRITE_CHECK_ERR,
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DPD_SYNC_TIMEOUT,
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DPD_CHECK_WPP_ERR_EXIT_HOLD,
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//...
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DPD_IDLE_ERR=0x30,
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DPD_PROC_EXIT = 0x99,
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DPD_UPDATING,
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DPD_SAVE_DATA = 0xAA,
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DPD_LOAD_DATA = 0xBB,
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DPD_STATUS_UPDATING = 0xff
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}E_DPD_STATE;
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typedef enum{
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E_DPD_NSAVE_NFLITER=0x00,//0x00
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E_DPD_NSAVE_FLITER =0x01,//0x01
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E_DPD_SAVE_NFLITER =0x10,//0x10
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E_DPD_SAVE_FLITER =0x11,//0x11
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}E_CTL_DPD;//cttb_para.wh_para.ctl_dpd
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//
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typedef enum
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{
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E_LOAD_TO_MCU,
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E_LOAD_TO_FPGA,
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}E_DPD_CURVE_PROC;
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typedef enum
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{
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E_DPD_AREA0=0,
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E_DPD_AREA1,
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E_DPD_AREA2,
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E_DPD_AREA3,
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E_DPD_AREA_FIRST_4K,
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}E_DPD_CURVE_AREA;
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typedef struct
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{
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uint32 tx_data_iq_i;
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uint32 rx_data_iq_i;
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uint16 ob_wpp_max_i;
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uint16 txaveamp_i;
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uint16 txpow_cur_i;
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uint16 rx_dgain_i;
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uint16 rx_fgain_cw_i;
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}S_DPD_LOG_TYPE;
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void refresh_update_dpd(void *parg,void *parv);
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int dpd_curve_proc(uint8 proc_mode);
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void dpd_exit(void);
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void dpd_set_clr(void);
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uint8 get_fpga_dpd_check(void);
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void dpd_boot_run_init(void);
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extern void set_dpd_unit_area_auto_inc(uint8 inc_flg);
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extern void set_tsnr_update_flg(uint8 up_flg);
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extern int update_tsnr_uimd_limd(uint8 rst_flg,uint8* p_phase);
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extern uint8 get_tsnr_update_flg(void);
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extern void remote_set_dpd_clr(void);
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extern uint8 conv_adpc_err_output(uint8 raw_dpd_err);
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extern void clear_dpd_data_file(void);
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extern void set_ab_switch(E_AB_SEL ab_val);
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extern u32 read_fpga_area_u32_check_sum(u8 check_type);
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extern void clear_check_sum(S_CHECK_SUM *parea_check);
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extern void calc_area_u32_check_sum(u32 *pcheck, u8 *pbuf, u32 len);
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extern void calc_area_check_sum(u8 *pcheck, u8 *pbuf, u32 len);
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#endif
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