146 lines
4.3 KiB
C
Executable File
146 lines
4.3 KiB
C
Executable File
#ifndef __FPGA_H_
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#define __FPGA_H_
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#include "type.h"
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#include "lcd_task.h"
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#define I2C_REG_ADDRES (0xE0)
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#define FPGA_UPGRADE_I2C_REG_ADDRES (0xE0)
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#define RW_ADPC_SAVE 0 //保存ADPC数据 读FPGA,写E2/FLASH
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#define RW_ADPC_LOAD 1 //加载ADPC数据 读E
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//新平台ADPC曲线配置 线性区还是只有一条,非线性区有多条
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#define FPGA_ADPC_DATA_NUM 7
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//每条曲线非线性大概16k,线性400多字节
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#define FPGA_ADPC_CURRENT_NONLINER_SIZE 16 //当前实际的非线性区大小(KB)
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#define FPGA_ADPC_NONLINER_DATA_ADDRESS (0)
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#define FPGA_ADPC_NONLINER_DATA_SIZE (16*1024)
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#define E2_FPGA_ADPC_NONLINER_DATA_ADDRESS (FPGA_ADPC_NONLINER_DATA_SIZE*7)
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#if 1//@MK_MTB_TSOIP
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typedef enum{IP2TS_SEL_IP1=1,IP2TS_SEL_IP2=2,IP2TS_SEL_IP_AUTO}en_IP2TS_SEL;
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typedef union
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{
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struct
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{
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unsigned char port :1;//0:asi 1:ip
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unsigned char ret :1;
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unsigned char asi_sel:2;//00:asi1 01:asi2 other:auto
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}bitFiled;
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unsigned char asi_s;
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}UN_ASI_SEL;
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typedef enum
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{
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FPGA_IP_ADDR1 = 0X01,
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FPGA_IP_ADDR2 = 0X02,
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FPGA_IP_ADDR3 = 0X03,
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FPGA_IP_ADDR4 = 0X04, //单播与组播IP地址复用 收端
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FPGA_REC_PORT_HIGH = 0X05,
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FPGA_REC_PORT_LOW = 0X06,
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FPGA_BROAD_TYPE = 0X07, //单/组播
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FPGA_TS_PACKET_LEN = 0X08, //对外播放时的TS包长
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FPGA_TS_PACKET_TYPE = 0X09, //PACK_UDP 0 PACK_RTP 1
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FPGA_HW_VER = 0X0A, //VER
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FPGA_TS_FEC = 0X0b, //收端只读
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FPGA_TS_ROW = 0X0c,
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FPGA_TS_COL = 0X0d,
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FPGA_DELAY_H = 0X0E,
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FPGA_DELAY_L = 0X0F,
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FPGA_LED_STATUS = 0X10, //bit0: ts err bit1:ts out bit2:ip in bit3: MCU的MAC未响应FPGA发来的包(1,错误)
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//bit4: ip err(网线没连,收不到网络包)
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FPGA_VER_YY = 0X11,
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FPGA_VER_MM = 0X12,
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FPGA_VER_DD = 0X13,
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FPGA_IP_PK_NUM_H = 0X14,
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FPGA_IP_PK_NUM_L = 0X15,
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FPGA_IP_CTIME_H = 0X16,
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FPGA_IP_CTIME_M = 0X17,
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FPGA_IP_CTIME_L = 0X18, //用于计算IP输入码率
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//rate = (pk_num*188*8)/(ctime*12.5*1e-9)bit/s
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// FPGA_ASI_RATE_HH = 0X19,
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// FPGA_ASI_RATE_HL = 0X1A,
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// FPGA_ASI_RATE_LH = 0X1B,
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// FPGA_ASI_RATE_LL = 0X1C,//asi输入码率 bps
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FPGA_TSIO_STATE = 0X19,//获取到ip12的选择和锁定状态 //h20190221
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FPGA_PHY_RST = 0X1F,
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FPGA_IP_DEST1 = 0X20,
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FPGA_IP_DEST2 = 0X21,
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FPGA_IP_DEST3 = 0X22,
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FPGA_IP_DEST4 = 0X23, //ip流目标地址
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FPGA_MAC_SOURCE1 = 0X24,
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FPGA_MAC_SOURCE2 = 0X25,
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FPGA_MAC_SOURCE3 = 0X26,
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FPGA_MAC_SOURCE4 = 0X27,
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FPGA_MAC_SOURCE5 = 0X28,
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FPGA_MAC_SOURCE6 = 0X29,
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FPGA_MAC_DEST1 = 0X2A,
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FPGA_MAC_DEST2 = 0X2B,
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FPGA_MAC_DEST3 = 0X2C,
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FPGA_MAC_DEST4 = 0X2D,
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FPGA_MAC_DEST5 = 0X2E,
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FPGA_MAC_DEST6 = 0X2F,
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FPGA_PHY_TYPE = 0X30, //0:100M 1:GB 2:AUTO
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FPGA_DEST_PORT_HIGH = 0X31,
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FPGA_DEST_PORT_LOW = 0X32,
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FPGA_RTP_UDP = 0X33, //还未用
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FPGA_DEST_LCL_ADDR1 = 0X34,
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FPGA_DEST_LCL_ADDR2 = 0X35,
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FPGA_DEST_LCL_ADDR3 = 0X36,
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FPGA_DEST_LCL_ADDR4 = 0X37, //固定向FPGA配置本地IP地址,作为发端时,FPGA必须要用该值
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FPGA_IP12_SELECT = 0X38, //选择IP1或IP2作为输入(该参数由激励器端接收到，并向IP端的FPGA设置) //h20190221
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FPGA_SFN_MFN_SELECT = 0x39,
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}E_FPGA_IP2TS_PARA_ADDRESS;
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extern uint8 send_ip12sel_tsoip(uint8 ip_sel);
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extern void fpga_save_dpd_para(S_DPD_PARA *ppara);
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extern void fpga_save_config_tsoip(int tsoip_index,S_TSOIP_CONFIG_PARA *ppara);
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extern void fpga_save_dest_mac(void);
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extern uint32 internal_set_base_delay(uint32 delay);
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#endif//@MK_MTB_TSOIP
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void fpga_save_power(S_WE_PARA *pwe,S_RF_PARA *prf);
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void fpga_set_rf_output(uint8 rf);
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void fpga_boot_rf_hold_begin(void);
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void fpga_boot_rf_hold_release(void);
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void erase_adpc_data(void);
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void config_fpga_para(void);
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#if 1//@ALD_UP
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void fpga_save_wl(S_WL_PARA *ppara);
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void fpga_save_dest_mac(void);
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void fpga_save_config_tsoip(int tsoip_index,S_TSOIP_CONFIG_PARA *ppara);
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void boot_reset_for_test(void);
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void boot_cfg_fagc_update();
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#endif
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#endif
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