70 lines
3.0 KiB
C
70 lines
3.0 KiB
C
/**
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******************************************************************************
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* @file stm32f4x7_eth_bsp.h
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* @author MCD Application Team
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* @version V1.0.0
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* @date 31-October-2011
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* @brief Header for stm32f4x7_eth_bsp.c file.
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******************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F4x7_ETH_BSP_H
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#define __STM32F4x7_ETH_BSP_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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//#include "stm324xg_eval.h"
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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#define DP83848_PHY_ADDRESS 0x01 /* Relative to STM324xG-EVAL Board */
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/* Specific defines for EXTI line, used to manage Ethernet link status */
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#define ETH_LINK_EXTI_LINE EXTI_Line10
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#define ETH_LINK_EXTI_PORT_SOURCE EXTI_PortSourceGPIOG
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#define ETH_LINK_EXTI_PIN_SOURCE EXTI_PinSource10
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#define ETH_LINK_EXTI_IRQn EXTI15_10_IRQn
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/* PB14 */
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#define ETH_LINK_PIN GPIO_Pin_10
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#define ETH_LINK_GPIO_PORT GPIOG
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#define ETH_LINK_GPIO_CLK RCC_AHB1Periph_GPIOG
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/* PHY registers */
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#define PHY_MICR 0x11 /* MII Interrupt Control Register */
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#define PHY_MICR_INT_EN ((uint16_t)0x0002) /* PHY Enable interrupts */
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#define PHY_MICR_INT_OE ((uint16_t)0x0001) /* PHY Enable output interrupt events */
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#define PHY_MISR 0x12 /* MII Interrupt Status and Misc. Control Register */
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#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /* Enable Interrupt on change of link status */
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#define PHY_LINK_STATUS ((uint16_t)0x2000) /* PHY link status interrupt mask */
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions ------------------------------------------------------- */
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void ETH_BSP_Config(void);
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uint32_t Eth_Link_PHYITConfig(uint16_t PHYAddress);
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void Eth_Link_EXTIConfig(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __STM32F4x7_ETH_BSP_H */
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/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
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