614 lines
21 KiB
C
614 lines
21 KiB
C
/* **************************************************** */
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/*!
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@file MN_DMD_Driver.h
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@brief Panasonic Demodulator Driver
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@author R.Mori
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@date 2011/6/30
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@param
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(c) Panasonic
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*/
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/* **************************************************** */
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#ifndef MN_DMD_DRIVER_H
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#define MN_DMD_DRIVER_H
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//#ifdef __cplusplus
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//extern "C" {
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//#endif
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/* **************************************************** */
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/* types */
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/* **************************************************** */
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#include "MN_DMD_types.h"
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/* **************************************************** */
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/* Defines */
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/* **************************************************** */
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#define DMD_INFORMATION_MAX 512
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#define DMD_INFO_VALUE_MAX 32
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/* DEMOD type setting */
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//< DEMOD_TYPE >
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#define DMD_TYPE_MN88471 (1) //same as Chipid
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#define DMD_TYPE_MN88472 (2) //same as Chipid
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#define DMD_TYPE_MN88473 (3) //same as Chipid
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//< TUNER_I2C_MODE >
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#define TUNER_CONTROL_BY_SOC (1)
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#define TUNER_CONTROL_BY_DEMOD (2)
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/* Tuner I2C controlled by Demod, Demod's communication method */
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//< DEMOD_CONTROL_TUNER_I2C_MODE >
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#define TCB_I2C_FORMAT_REPEAT_MODE (1)// default, SoC need write bytes to certain register of demod, to communicate with Tuner indirectly
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#define TCB_I2C_FORMAT_BYPASS_MODE (2)// only valid for MN88473. demod is like door, open or close, when set it open, SoC can communicate with Tuner directly.
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/* Tuner type setting */
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//< TUNER_TYPE>
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#define MXL603 (1)
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#define SI2148 (2)
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#define NMI120 (3)
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#define NXP18250B (4)
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#define RDA5880P (5)
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#define MXL301 (6)
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#define NXP18273 (7)
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/* --- XTAL Freq. of DMD--- [Need adjust DMD register for different XTAL and IF]*/
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//<XTAL_FREQ>
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#define DMD_XTAL20480KHZ_IF5MHZ 1
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#define DMD_XTAL24000KHZ_IF5MHZ 2
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#define DMD_XTAL20500KHZ_IF5MHZ 3
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#define DMD_XTAL25000KHZ_IF5MHZ 4 //20131220, added CONFIG for MN88473
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/* **************************************************** */
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/* DMD Enums */
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/* **************************************************** */
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/*! SYSTEM Enum */
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typedef enum _DMD_SYSTEM_t{
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DMD_E_ISDBT=0,
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DMD_E_ISDBS,
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DMD_E_DVBT,
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DMD_E_DVBT2,
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DMD_E_DVBC,
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DMD_E_DVBC2,
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DMD_E_ATSC,
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DMD_E_QAMB_64QAM,
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DMD_E_QAMB_256QAM,
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DMD_E_QAMC_64QAM,
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DMD_E_QAMC_256QAM,
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DMD_E_ISDBT_BRAZIL,
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DMD_E_ANALOG,
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DMD_E_NTSC_M_BTSC,
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DMD_E_PAL_M_BTSC,
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DMD_E_PAL_N_BTSC,
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DMD_E_PAL_B_G_NICAM,
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DMD_E_PAL_I_NiCAM,
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DMD_E_PAL_D_NiCAM,
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DMD_E_PAL_B_G_A2,
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DMD_E_SECAM_L_NiCAM,
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DMD_E_SECAM_L1_NiCAM,
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DMD_E_SECAM_D_K_A2,
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DMD_E_SECAM_BG_NICAM,
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DMD_E_END_OF_SYSTEM,
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DMD_E_NOT_DEFINED
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} DMD_SYSTEM_t;
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/* RF Frequency Unit */
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typedef enum _DMD_FREQ_UNIT_t
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{
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DMD_E_MHZ,
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DMD_E_KHZ,
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DMD_E_HZ
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} DMD_FREQ_UNIT_t;
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/*! Lock Status */
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typedef enum _DMD_LOCK_STATUS_t{
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DMD_E_LOCKED = 0,
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DMD_E_LOCK_NOSIGNAL,
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DMD_E_LOCK_NOSYNC,
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DMD_E_LOCK_ERROR
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} DMD_LOCK_STATUS_t;
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/*! Return Value for API Functions */
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typedef enum _DMD_ERROR_t{
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DMD_E_OK = 0,
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DMD_E_ERROR = 1
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} DMD_ERROR_t;
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/*! BAND WIDTH */
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typedef enum _DMD_BANDWIDTH_t{
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DMD_E_BW_NOT_SPECIFIED,
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DMD_E_BW_6MHZ,
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DMD_E_BW_7MHZ,
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DMD_E_BW_8MHZ,
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DMD_E_BW_5MHZ,
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DMD_E_BW_1_7MHZ,
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DMD_E_BW_END_OF_BW
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} DMD_BANDWIDTH_t;
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/* '11/08/29 : OKAMOTO Select TS output. */
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typedef enum _DMD_TSOUT{
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DMD_E_TSOUT_PARALLEL_FIXED_CLOCK = 0,
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//DMD_E_TSOUT_PARALLEL_VARIABLE_CLOCK,
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DMD_E_TSOUT_SERIAL_VARIABLE_CLOCK
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} DMD_TSOUT;
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typedef enum _DMD_ECHO_PERFORMANCE_SET{
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DMD_E_ENHANCE_MINUS_ECHO_DELAY_DEFAULT = 0, //field test pass result
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DMD_E_ENHANCE_MINUS_ECHO_DELAY_NO_SIDEEFFECT, //Lab test. enhance MINUS echo dalay performance, no side effect
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DMD_E_ENHANCE_MINUS_ECHO_DELAY_HAS_SIDEEFFECT //Lab test. enhance MINUS echo dalay performance, has side effect on CCI(NTSC interface)
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} DMD_ECHO_PERFORMANCE_SET;
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/* **************************************************** */
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/* DMD Structures */
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/* **************************************************** */
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/*! DMD Parameter Sturcture */
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#if 0
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DMD_PARAMETER{
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DMD_u32_t devid; //!<DeviceID
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DMD_SYSTEM_t system; //!<Broadcast System
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DMD_u32_t freq; //!<RF Frequency
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DMD_FREQ_UNIT_t funit; //!<RF Frequency unit
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DMD_BANDWIDTH_t bw; //!<Band width
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DMD_u32_t ddradr; //!<DDR memory address
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DMD_u32_t info[DMD_INFORMATION_MAX]; //!<Demodulator Information
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/* '11/08/29 : OKAMOTO Select TS output. */
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DMD_TSOUT ts_out;
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DMD_ECHO_PERFORMANCE_SET echo_set; //troy.wangyx, 120801, to enhance "Single static echo MINUS delay"'s performance,
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} ;
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#endif
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typedef struct {
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DMD_u32_t devid; //!<DeviceID
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DMD_SYSTEM_t system; //!<Broadcast System
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DMD_u32_t freq; //!<RF Frequency
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DMD_FREQ_UNIT_t funit; //!<RF Frequency unit
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DMD_BANDWIDTH_t bw; //!<Band width
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DMD_u32_t ddradr; //!<DDR memory address
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DMD_u32_t info[DMD_INFORMATION_MAX]; //!<Demodulator Information
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/* '11/08/29 : OKAMOTO Select TS output. */
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DMD_TSOUT ts_out;
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DMD_ECHO_PERFORMANCE_SET echo_set; //troy.wangyx, 120801, to enhance "Single static echo MINUS delay"'s performance,
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} DMD_PARAMETER;
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/* **************************************************** */
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/* Public Functions */
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/* **************************************************** */
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/* API&LSI control Functions */
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/* these function is defined by MN_DMD_Driver.c */
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extern DMD_u32_t DMD_open ( DMD_PARAMETER* param);
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extern DMD_u32_t DMD_set_devid ( DMD_PARAMETER* param , DMD_u32_t id);
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//extern DMD_u32_t DMD_init ( DMD_u32_t freq);
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DMD_u32_t DMD_init ( DMD_u32_t freq);
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extern DMD_u32_t DMD_set_system ( DMD_PARAMETER* param );
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extern DMD_u32_t DMD_tune ( DMD_PARAMETER* param);
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extern DMD_u32_t DMD_scan ( DMD_PARAMETER* param);
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extern DMD_u32_t DMD_reset ( DMD_PARAMETER* param);
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extern DMD_u32_t DMD_term ( DMD_PARAMETER* param);
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extern DMD_u32_t DMD_get_info ( DMD_PARAMETER* param , DMD_u32_t id );
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extern DMD_u32_t DMD_set_info ( DMD_PARAMETER* param , DMD_u32_t id , DMD_u32_t val);
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extern DMD_u32_t DMD_close ( DMD_PARAMETER* param);
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/* Floating Functions */
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// To use , define DMD_FLOATING_FUNCTION
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extern DMD_float_t DMD_get_ber(void);
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extern DMD_float_t DMD_get_per(void);
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extern DMD_float_t DMD_get_cnr(void);
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//extern DMD_u32_t DMD_get_lock(void);
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DMD_u32_t DMD_get_lock(void);
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/* Get Infomation String */
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extern DMD_text_t DMD_info_title( DMD_SYSTEM_t sys , DMD_u32_t info_id );
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extern DMD_text_t DMD_info_value( DMD_SYSTEM_t sys , DMD_u32_t info_id , DMD_u32_t value);
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extern DMD_text_t DMD_value_text( DMD_PARAMETER* param , DMD_u32_t id );
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/* **************************************************** */
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/* DMD Information */
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/* **************************************************** */
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/*! common information enum */
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typedef enum _DMD_INFO_t{ DMD_E_INFO_ALL =0 ,
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DMD_E_INFO_REGREV =1 ,
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DMD_E_INFO_PSEQREV =2 ,
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DMD_E_INFO_SYSTEM =3 ,
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DMD_E_INFO_LOCK =4 ,
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DMD_E_INFO_AGC =5 ,
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DMD_E_INFO_BERRNUM =6 ,
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DMD_E_INFO_BITNUM =7 ,
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DMD_E_INFO_CNR_INT =8 ,
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DMD_E_INFO_CNR_DEC =9 ,
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DMD_E_INFO_PERRNUM =10 ,
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DMD_E_INFO_PACKETNUM =11 ,
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DMD_E_INFO_STATUS =12 ,
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DMD_E_INFO_ERRORFREE = 13,
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DMD_E_INFO_COMMON_END_OF_INFORMATION
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}DMD_INFO_t;
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/*! DVBT information enum */
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typedef enum _DMD_INFO_DVBT_t{ DMD_E_INFO_DVBT_ALL =0 ,
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DMD_E_INFO_DVBT_REGREV =1 ,
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DMD_E_INFO_DVBT_PSEQRV =2 ,
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DMD_E_INFO_DVBT_SYSTEM =3 ,
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DMD_E_INFO_DVBT_LOCK =4 ,
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DMD_E_INFO_DVBT_AGC =5 ,
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DMD_E_INFO_DVBT_BERRNUM =6 ,
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DMD_E_INFO_DVBT_BITNUM =7 ,
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DMD_E_INFO_DVBT_CNR_INT =8 ,
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DMD_E_INFO_DVBT_CNR_DEC =9 ,
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DMD_E_INFO_DVBT_PERRNUM =10 ,
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DMD_E_INFO_DVBT_PACKETNUM =11 ,
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DMD_E_INFO_DVBT_STATUS = 12,
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DMD_E_INFO_DVBT_ERRORFREE ,
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DMD_E_INFO_DVBT_SQI ,
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DMD_E_INFO_DVBT_HIERARCHY_SELECT ,
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DMD_E_INFO_DVBT_TPS_ALL ,
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DMD_E_INFO_DVBT_MODE ,
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DMD_E_INFO_DVBT_GI ,
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DMD_E_INFO_DVBT_LENGTH_INDICATOR ,
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DMD_E_INFO_DVBT_CONSTELLATION ,
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DMD_E_INFO_DVBT_HIERARCHY ,
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DMD_E_INFO_DVBT_HP_CODERATE ,
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DMD_E_INFO_DVBT_LP_CODERATE ,
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DMD_E_INFO_DVBT_CELLID ,
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DMD_E_INFO_DVBT_END_OF_INFORMATION
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} DMD_INFO_DVBT_t;
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/*! DVBT2 information enum */
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typedef enum _DMD_INFO_DVBT2_t{ DMD_E_INFO_DVBT2_ALL =0 ,
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DMD_E_INFO_DVBT2_REGREV =1 ,
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DMD_E_INFO_DVBT2_PSEQRV =2 ,
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DMD_E_INFO_DVBT2_SYSTEM =3 ,
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DMD_E_INFO_DVBT2_LOCK =4 ,
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DMD_E_INFO_DVBT2_AGC =5 ,
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DMD_E_INFO_DVBT2_BERRNUM =6 ,
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DMD_E_INFO_DVBT2_BITNUM =7 ,
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DMD_E_INFO_DVBT2_CNR_INT =8 ,
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DMD_E_INFO_DVBT2_CNR_DEC =9 ,
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DMD_E_INFO_DVBT2_PERRNUM =10 ,
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DMD_E_INFO_DVBT2_PACKETNUM =11 ,
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DMD_E_INFO_DVBT2_STATUS =12,
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DMD_E_INFO_DVBT2_ERRORFREE,
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DMD_E_INFO_DVBT2_SQI,
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DMD_E_INFO_DVBT2_MODE,
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DMD_E_INFO_DVBT2_GI,
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DMD_E_INFO_DVBT2_BERRNUM_C,
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DMD_E_INFO_DVBT2_BITNUM_C,
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DMD_E_INFO_DVBT2_SELECTED_PLP,
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DMD_E_INFO_DVBT2_L1_ALL,
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DMD_E_INFO_DVBT2_TYPE,
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DMD_E_INFO_DVBT2_BW_EXT,
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DMD_E_INFO_DVBT2_S1,
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DMD_E_INFO_DVBT2_S2,
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DMD_E_INFO_DVBT2_PAPR,
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DMD_E_INFO_DVBT2_L1_MOD,
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DMD_E_INFO_DVBT2_L1_COD,
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DMD_E_INFO_DVBT2_L1_FEC_TYPE,
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DMD_E_INFO_DVBT2_L1_POST_SIZE,
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DMD_E_INFO_DVBT2_L1_POST_INFO_SIZE,
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DMD_E_INFO_DVBT2_PILOT_PATTERN,
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DMD_E_INFO_DVBT2_TX_ID_AVAILABILITY,
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DMD_E_INFO_DVBT2_CELL_ID,
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DMD_E_INFO_DVBT2_NETWORK_ID,
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DMD_E_INFO_DVBT2_T2_SYSTEM_ID,
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DMD_E_INFO_DVBT2_NUM_T2_FRAMES,
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DMD_E_INFO_DVBT2_NUM_DATA_SYMBOLS,
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DMD_E_INFO_DVBT2_REGEN_FLAG,
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DMD_E_INFO_DVBT2_L1_POST_EXTENSION,
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DMD_E_INFO_DVBT2_NUM_RF,
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DMD_E_INFO_DVBT2_CURRENT_RF_IDX,
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DMD_E_INFO_DVBT2_SUB_SLICES_PER_FRAME,
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DMD_E_INFO_DVBT2_SUB_SLICE_INTERVAL,
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DMD_E_INFO_DVBT2_NUM_PLP,
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DMD_E_INFO_DVBT2_NUM_AUX,
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DMD_E_INFO_DVBT2_PLP_MODE,
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DMD_E_INFO_DVBT2_FEF_TYPE,
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DMD_E_INFO_DVBT2_FEF_LENGTH,
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DMD_E_INFO_DVBT2_FEF_INTERVAL,
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DMD_E_INFO_DVBT2_DAT_PLP_ID,
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DMD_E_INFO_DVBT2_DAT_PLP_TYPE,
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DMD_E_INFO_DVBT2_DAT_PLP_PAYLOAD_TYPE,
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DMD_E_INFO_DVBT2_DAT_PLP_GROUP_ID,
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DMD_E_INFO_DVBT2_DAT_PLP_COD,
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DMD_E_INFO_DVBT2_DAT_PLP_MOD,
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DMD_E_INFO_DVBT2_DAT_PLP_ROTATION,
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DMD_E_INFO_DVBT2_DAT_PLP_FEC_TYPE,
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DMD_E_INFO_DVBT2_DAT_PLP_NUM_BLOCKS_MAX,
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DMD_E_INFO_DVBT2_DAT_PLP_FRAME_INTEVAL,
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DMD_E_INFO_DVBT2_DAT_PLP_TIME_IL_LENGTH,
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DMD_E_INFO_DVBT2_DAT_PLP_TIME_IL_TYPE,
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DMD_E_INFO_DVBT2_DAT_FF_FLAG,
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DMD_E_INFO_DVBT2_COM_PLP_ID,
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DMD_E_INFO_DVBT2_COM_PLP_TYPE,
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DMD_E_INFO_DVBT2_COM_PLP_PAYLOAD_TYPE,
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DMD_E_INFO_DVBT2_COM_PLP_GROUP_ID,
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DMD_E_INFO_DVBT2_COM_PLP_COD,
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DMD_E_INFO_DVBT2_COM_PLP_MOD,
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DMD_E_INFO_DVBT2_COM_PLP_ROTATION,
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DMD_E_INFO_DVBT2_COM_PLP_FEC_TYPE,
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DMD_E_INFO_DVBT2_COM_PLP_NUM_BLOCKS_MAX,
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DMD_E_INFO_DVBT2_COM_PLP_FRAME_INTEVAL,
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DMD_E_INFO_DVBT2_COM_PLP_TIME_IL_LENGTH,
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DMD_E_INFO_DVBT2_COM_PLP_TIME_IL_TYPE,
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DMD_E_INFO_DVBT2_COM_FF_FLAG,
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DMD_E_INFO_DVBT2_FRAME_IDX,
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DMD_E_INFO_DVBT2_TYPE_2_START,
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DMD_E_INFO_DVBT2_L1_CHANGE_COUNTER,
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DMD_E_INFO_DVBT2_START_RF_IDX,
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DMD_E_INFO_DVBT2_DAT_FIRST_RF_IDX,
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DMD_E_INFO_DVBT2_DAT_PLP_START,
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DMD_E_INFO_DVBT2_DAT_PLP_NUM_BLOCKS,
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DMD_E_INFO_DVBT2_COM_FIRST_RF_IDX,
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DMD_E_INFO_DVBT2_COM_PLP_START,
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DMD_E_INFO_DVBT2_COM_PLP_NUM_BLOCKS,
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DMD_E_INFO_DVBT2_STATIC_FLAG,
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DMD_E_INFO_DVBT2_STATIC_PADDING_FLAG,
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DMD_E_INFO_DVBT2_IN_BAND_A_FLAG,
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DMD_E_INFO_DVBT2_IN_BAND_B_FLAG,
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DMD_E_INFO_DVBT2_END_OF_INFORMATION
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} DMD_INFO_DVBT2_t;
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/*! DVBC information enum */
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typedef enum { DMD_E_INFO_DVBC_ALL =0 ,
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DMD_E_INFO_DVBC_REGREV =1 ,
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DMD_E_INFO_DVBC_PSEQRV =2 ,
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DMD_E_INFO_DVBC_SYSTEM =3 ,
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DMD_E_INFO_DVBC_LOCK =4 ,
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DMD_E_INFO_DVBC_AGC =5 ,
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DMD_E_INFO_DVBC_BERRNUM =6 ,
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DMD_E_INFO_DVBC_BITNUM =7 ,
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DMD_E_INFO_DVBC_CNR_INT =8 ,
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DMD_E_INFO_DVBC_CNR_DEC =9 ,
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DMD_E_INFO_DVBC_PERRNUM =10 ,
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DMD_E_INFO_DVBC_PACKETNUM =11 ,
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DMD_E_INFO_DVBC_STATUS =12 ,
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DMD_E_INFO_DVBC_ERRORFREE = 13,
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DMD_E_INFO_DVBC_END_OF_INFORMATION
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} DMD_INFO_DVBC_t;
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/*! ISDBT information enum */
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typedef enum { DMD_E_INFO_ISDBT_ALL =0 ,
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DMD_E_INFO_ISDBT_REGREV =1 ,
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DMD_E_INFO_ISDBT_PSEQRV =2 ,
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DMD_E_INFO_ISDBT_SYSTEM =3 ,
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DMD_E_INFO_ISDBT_LOCK =4 ,
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DMD_E_INFO_ISDBT_AGC =5 ,
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DMD_E_INFO_ISDBT_BERRNUM =6 ,
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DMD_E_INFO_ISDBT_BITNUM =7 ,
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DMD_E_INFO_ISDBT_CNR_INT =8 ,
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DMD_E_INFO_ISDBT_CNR_DEC =9 ,
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DMD_E_INFO_ISDBT_PERRNUM =10 ,
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DMD_E_INFO_ISDBT_PACKETNUM =11 ,
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|
DMD_E_INFO_ISDBT_STATUS =12 ,
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|
DMD_E_INFO_ISDBT_ERRORFREE = 13,
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|
DMD_E_INFO_ISDBT_BERRNUM_A ,
|
|
DMD_E_INFO_ISDBT_BITNUM_A ,
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|
DMD_E_INFO_ISDBT_BERRNUM_B ,
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|
DMD_E_INFO_ISDBT_BITNUM_B ,
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|
DMD_E_INFO_ISDBT_BERRNUM_C ,
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|
DMD_E_INFO_ISDBT_BITNUM_C ,
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|
DMD_E_INFO_ISDBT_ERRORFREE_A ,
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|
DMD_E_INFO_ISDBT_ERRORFREE_B ,
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|
DMD_E_INFO_ISDBT_ERRORFREE_C ,
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|
DMD_E_INFO_ISDBT_MODE ,
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|
DMD_E_INFO_ISDBT_GI ,
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|
DMD_E_INFO_ISDBT_SYS_TMCC ,
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|
DMD_E_INFO_ISDBT_COUNTDOWN ,
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|
DMD_E_INFO_ISDBT_EMGFLG ,
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|
DMD_E_INFO_ISDBT_PART ,
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|
DMD_E_INFO_ISDBT_MAPA ,
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|
DMD_E_INFO_ISDBT_CRA ,
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|
DMD_E_INFO_ISDBT_INTA ,
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|
DMD_E_INFO_ISDBT_SEGA ,
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|
DMD_E_INFO_ISDBT_MAPB ,
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|
DMD_E_INFO_ISDBT_CRB ,
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|
DMD_E_INFO_ISDBT_INTB ,
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|
DMD_E_INFO_ISDBT_SEGB ,
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|
DMD_E_INFO_ISDBT_MAPC ,
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|
DMD_E_INFO_ISDBT_CRC ,
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|
DMD_E_INFO_ISDBT_INTC ,
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|
DMD_E_INFO_ISDBT_SEGC ,
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|
DMD_E_INFO_ISDBT_PHCOR ,
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|
DMD_E_INFO_ISDBT_END_OF_INFORMATION
|
|
} DMD_INFO_ISDBT_t;
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|
/*! ISDBS information enum */
|
|
typedef enum { DMD_E_INFO_ISDBS_ALL =0 ,
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|
DMD_E_INFO_ISDBS_REGREV =1 ,
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|
DMD_E_INFO_ISDBS_PSEQRV =2 ,
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|
DMD_E_INFO_ISDBS_SYSTEM =3 ,
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|
DMD_E_INFO_ISDBS_LOCK =4 ,
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|
DMD_E_INFO_ISDBS_AGC =5 ,
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|
DMD_E_INFO_ISDBS_BERRNUM =6 ,
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|
DMD_E_INFO_ISDBS_BITNUM =7 ,
|
|
DMD_E_INFO_ISDBS_CNR_INT =8 ,
|
|
DMD_E_INFO_ISDBS_CNR_DEC =9 ,
|
|
DMD_E_INFO_ISDBS_PERRNUM =10 ,
|
|
DMD_E_INFO_ISDBS_PACKETNUM =11 ,
|
|
DMD_E_INFO_ISDBS_STATUS =12 ,
|
|
DMD_E_INFO_ISDBS_ERRORFREE = 13,
|
|
DMD_E_INFO_ISDBS_BERRNUM_1 ,
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|
DMD_E_INFO_ISDBS_BITNUM_1 ,
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|
DMD_E_INFO_ISDBS_BERRNUM_2 ,
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|
DMD_E_INFO_ISDBS_BITNUM_2 ,
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|
DMD_E_INFO_ISDBS_BERRNUM_3 ,
|
|
DMD_E_INFO_ISDBS_BITNUM_3 ,
|
|
DMD_E_INFO_ISDBS_ERRORFREE_0 ,
|
|
DMD_E_INFO_ISDBS_ERRORFREE_1 ,
|
|
DMD_E_INFO_ISDBS_ERRORFREE_2 ,
|
|
DMD_E_INFO_ISDBS_ERRORFREE_3 ,
|
|
DMD_E_INFO_ISDBS_ERRORFREE_T ,
|
|
DMD_E_INFO_ISDBS_TSNO ,
|
|
DMD_E_INFO_ISDBS_TSID ,
|
|
DMD_E_INFO_ISDBS_MOD ,
|
|
DMD_E_INFO_ISDBS_EMGSW ,
|
|
DMD_E_INFO_ISDBS_UPLINK ,
|
|
DMD_E_INFO_ISDBS_EXON ,
|
|
DMD_E_INFO_ISDBS_CHANGE ,
|
|
DMD_E_INFO_ISDBS_MOD0 ,
|
|
DMD_E_INFO_ISDBS_SLOT0 ,
|
|
DMD_E_INFO_ISDBS_MOD1 ,
|
|
DMD_E_INFO_ISDBS_SLOT1 ,
|
|
DMD_E_INFO_ISDBS_MOD2 ,
|
|
DMD_E_INFO_ISDBS_SLOT2 ,
|
|
DMD_E_INFO_ISDBS_MOD3 ,
|
|
DMD_E_INFO_ISDBS_SLOT3 ,
|
|
DMD_E_INFO_ISDBS_TSID0 ,
|
|
DMD_E_INFO_ISDBS_TSID1 ,
|
|
DMD_E_INFO_ISDBS_TSID2 ,
|
|
DMD_E_INFO_ISDBS_TSID3 ,
|
|
DMD_E_INFO_ISDBS_TSID4 ,
|
|
DMD_E_INFO_ISDBS_TSID5 ,
|
|
DMD_E_INFO_ISDBS_TSID6 ,
|
|
DMD_E_INFO_ISDBS_TSID7 ,
|
|
DMD_E_INFO_ISDBS_TSNO01 ,
|
|
DMD_E_INFO_ISDBS_TSNO02 ,
|
|
DMD_E_INFO_ISDBS_TSNO03 ,
|
|
DMD_E_INFO_ISDBS_TSNO04 ,
|
|
DMD_E_INFO_ISDBS_TSNO05 ,
|
|
DMD_E_INFO_ISDBS_TSNO06 ,
|
|
DMD_E_INFO_ISDBS_TSNO07 ,
|
|
DMD_E_INFO_ISDBS_TSNO08 ,
|
|
DMD_E_INFO_ISDBS_TSNO09 ,
|
|
DMD_E_INFO_ISDBS_TSNO10 ,
|
|
DMD_E_INFO_ISDBS_TSNO11 ,
|
|
DMD_E_INFO_ISDBS_TSNO12 ,
|
|
DMD_E_INFO_ISDBS_TSNO13 ,
|
|
DMD_E_INFO_ISDBS_TSNO14 ,
|
|
DMD_E_INFO_ISDBS_TSNO15 ,
|
|
DMD_E_INFO_ISDBS_TSNO16 ,
|
|
DMD_E_INFO_ISDBS_TSNO17 ,
|
|
DMD_E_INFO_ISDBS_TSNO18 ,
|
|
DMD_E_INFO_ISDBS_TSNO19 ,
|
|
DMD_E_INFO_ISDBS_TSNO20 ,
|
|
DMD_E_INFO_ISDBS_TSNO21 ,
|
|
DMD_E_INFO_ISDBS_TSNO22 ,
|
|
DMD_E_INFO_ISDBS_TSNO23 ,
|
|
DMD_E_INFO_ISDBS_TSNO24 ,
|
|
DMD_E_INFO_ISDBS_TSNO25 ,
|
|
DMD_E_INFO_ISDBS_TSNO26 ,
|
|
DMD_E_INFO_ISDBS_TSNO27 ,
|
|
DMD_E_INFO_ISDBS_TSNO28 ,
|
|
DMD_E_INFO_ISDBS_TSNO29 ,
|
|
DMD_E_INFO_ISDBS_TSNO30 ,
|
|
DMD_E_INFO_ISDBS_TSNO31 ,
|
|
DMD_E_INFO_ISDBS_TSNO32 ,
|
|
DMD_E_INFO_ISDBS_TSNO33 ,
|
|
DMD_E_INFO_ISDBS_TSNO34 ,
|
|
DMD_E_INFO_ISDBS_TSNO35 ,
|
|
DMD_E_INFO_ISDBS_TSNO36 ,
|
|
DMD_E_INFO_ISDBS_TSNO37 ,
|
|
DMD_E_INFO_ISDBS_TSNO38 ,
|
|
DMD_E_INFO_ISDBS_TSNO39 ,
|
|
DMD_E_INFO_ISDBS_TSNO40 ,
|
|
DMD_E_INFO_ISDBS_TSNO41 ,
|
|
DMD_E_INFO_ISDBS_TSNO42 ,
|
|
DMD_E_INFO_ISDBS_TSNO43 ,
|
|
DMD_E_INFO_ISDBS_TSNO44 ,
|
|
DMD_E_INFO_ISDBS_TSNO45 ,
|
|
DMD_E_INFO_ISDBS_TSNO46 ,
|
|
DMD_E_INFO_ISDBS_TSNO47 ,
|
|
DMD_E_INFO_ISDBS_TSNO48 ,
|
|
DMD_E_INFO_ISDBS_END_OF_INFORMATION
|
|
} DMD_INFO_ISDBS_t;
|
|
|
|
/*! ATSC information enum */
|
|
typedef enum { DMD_E_INFO_ATSC_ALL =0 ,
|
|
DMD_E_INFO_ATSC_REGREV =1 ,
|
|
DMD_E_INFO_ATSC_PSEQRV =2 ,
|
|
DMD_E_INFO_ATSC_SYSTEM =3 ,
|
|
DMD_E_INFO_ATSC_LOCK =4 ,
|
|
DMD_E_INFO_ATSC_AGC =5 ,
|
|
DMD_E_INFO_ATSC_BERRNUM =6 ,
|
|
DMD_E_INFO_ATSC_BITNUM =7 ,
|
|
DMD_E_INFO_ATSC_CNR_INT =8 ,
|
|
DMD_E_INFO_ATSC_CNR_DEC =9 ,
|
|
DMD_E_INFO_ATSC_PERRNUM =10 ,
|
|
DMD_E_INFO_ATSC_PACKETNUM =11 ,
|
|
DMD_E_INFO_ATSC_STATUS =12 ,
|
|
DMD_E_INFO_ATSC_ERRORFREE = 13,
|
|
DMD_E_INFO_ATSC_END_OF_INFORMATION
|
|
} DMD_INFO_ATSC_t;
|
|
/*! QAM information enum */
|
|
typedef enum { DMD_E_INFO_QAM_ALL =0 ,
|
|
DMD_E_INFO_QAM_REGREV =1 ,
|
|
DMD_E_INFO_QAM_PSEQRV =2 ,
|
|
DMD_E_INFO_QAM_SYSTEM =3 ,
|
|
DMD_E_INFO_QAM_LOCK =4 ,
|
|
DMD_E_INFO_QAM_AGC =5 ,
|
|
DMD_E_INFO_QAM_BERRNUM =6 ,
|
|
DMD_E_INFO_QAM_BITNUM =7 ,
|
|
DMD_E_INFO_QAM_CNR_INT =8 ,
|
|
DMD_E_INFO_QAM_CNR_DEC =9 ,
|
|
DMD_E_INFO_QAM_PERRNUM =10 ,
|
|
DMD_E_INFO_QAM_PACKETNUM =11 ,
|
|
DMD_E_INFO_QAM_STATUS =12 ,
|
|
DMD_E_INFO_QAM_ERRORFREE = 13,
|
|
DMD_E_INFO_QAM_END_OF_INFORMATION
|
|
} DMD_INFO_QAM_t;
|
|
/*! ANALOG information enum */
|
|
typedef enum { DMD_E_INFO_ANALOG_ALL =0 ,
|
|
DMD_E_INFO_ANALOG_REGREV =1 ,
|
|
DMD_E_INFO_ANALOG_PSEQRV =2 ,
|
|
DMD_E_INFO_ANALOG_SYSTEM =3 ,
|
|
DMD_E_INFO_ANALOG_LOCK =4 ,
|
|
DMD_E_INFO_ANALOG_AGC =5 ,
|
|
DMD_E_INFO_ANALOG_BERRNUM =6 ,
|
|
DMD_E_INFO_ANALOG_BITNUM =7 ,
|
|
DMD_E_INFO_ANALOG_CNR_INT =8 ,
|
|
DMD_E_INFO_ANALOG_CNR_DEC =9 ,
|
|
DMD_E_INFO_ANALOG_PERRNUM =10 ,
|
|
DMD_E_INFO_ANALOG_PACKETNUM =11 ,
|
|
DMD_E_INFO_ANALOG_STATUS =12 ,
|
|
DMD_E_INFO_ANALOG_ERRORFREE = 13,
|
|
DMD_E_INFO_ANALOG_END_OF_INFORMATION
|
|
} DMD_INFO_ANALOG_t;
|
|
|
|
/*! enumulator for DVBT/DVBT2 information */
|
|
//common
|
|
typedef enum{ DMD_E_ERRORFREE_ERROR=0, DMD_E_ERRORFREE_ERRORFREE } DMD_ERRORFREE_t;
|
|
//DVBT
|
|
typedef enum{ DMD_E_DVBT_HIER_SEL_LP=0, DMD_E_DVBT_HIER_SEL_HP } DMD_DVBT_HIER_SEL_t;
|
|
typedef enum{ DMD_E_DVBT_TPS_OBTAIN_NG=0, DMD_E_DVBT_TPS_OBTAIN_OK } DMD_DVBT_TPS_OBTAIN_t;
|
|
typedef enum{ DMD_E_DVBT_MODE_2K=0, DMD_E_DVBT_MODE_8K, DMD_E_DVBT_MODE_4K , DMD_E_DVBT_MODE_NOT_DEFINED } DMD_DVBT_MODE_t;
|
|
typedef enum{ DMD_E_DVBT_GI_1_32=0, DMD_E_DVBT_GI_1_16, DMD_E_DVBT_GI_1_8, DMD_E_DVBT_GI_1_4 , DMD_E_DVBT_GI_NOT_DEFINED } DMD_DVBT_GI_t;
|
|
typedef enum{ DMD_E_DVBT_CONST_QPSK=0, DMD_E_DVBT_CONST_16QAM, DMD_E_DVBT_CONST_64QAM } DMD_DVBT_CONST_t;
|
|
typedef enum{ DMD_E_DVBT_HIERARCHY_NO=0, DMD_E_DVBT_HIERARCHY_ALPHA_1, DMD_E_DVBT_HIERARCHY_ALPHA_2, DMD_E_DVBT_HIERARCHY_ALPHA_4 } DMD_DVBT_HIERARCHY_t;
|
|
typedef enum{ DMD_E_DVBT_CR_1_2=0, DMD_E_DVBT_CR_2_3, DMD_E_DVBT_CR_3_4, DMD_E_DVBT_CR_5_6, DMD_E_DVBT_CR_7_8 } DMD_DVBT_CR_t;
|
|
//DVBT2
|
|
typedef enum{ DMD_E_DVBT2_MODE_1K=0, DMD_E_DVBT2_MODE_2K, DMD_E_DVBT2_MODE_4K, DMD_E_DVBT2_MODE_8K, DMD_E_DVBT2_MODE_16K, DMD_E_DVBT2_MODE_32K } DMD_DVBT2_MODE_t;
|
|
typedef enum{ DMD_E_DVBT2_GI_1_32=0, DMD_E_DVBT2_GI_1_16, DMD_E_DVBT2_GI_1_8, DMD_E_DVBT2_GI_1_4, DMD_E_DVBT2_GI_1_128, DMD_E_DVBT2_GI_19_128, DMD_E_DVBT2_GI_19_256, } DMD_DVBT2_GI_t;
|
|
typedef enum{ DMD_E_DVBT2_TYPE_TS=0, DMD_E_DVBT2_TYPE_GS, DMD_E_DVBT2_TYPE_TS_GS } DMD_DVBT2_TYPE_t;
|
|
typedef enum{ DMD_E_DVBT2_PAPR_NO=0, DMD_E_DVBT2_PAPR_ACE, DMD_E_DVBT2_PAPR_TR, DMD_E_DVBT2_PAPR_ACE_TR } DMD_DVBT2_PAPR_t;
|
|
typedef enum{ DMD_E_DVBT2_L1_MOD_BPSK=0, DMD_E_DVBT2_L1_MOD_QPSK, DMD_E_DVBT2_L1_MOD_16QAM, DMD_E_DVBT2_L1_MOD_64QAM } DMD_DVBT2_L1_MOD_t;
|
|
typedef enum{ DMD_E_DVBT2_CR_1_2=0, DMD_E_DVBT2_CR_3_5, DMD_E_DVBT2_CR_2_3, DMD_E_DVBT2_CR_3_4, DMD_E_DVBT2_CR_4_5, DMD_E_DVBT2_CR_5_6 } DMD_DVBT2_CR_t;
|
|
typedef enum{ DMD_E_DVBT2_FEC_TYPE_16K=0, DMD_E_DVBT2_FEC_TYPE_64K } DMD_DVBT2_FEC_TYPE_t;
|
|
typedef enum{ DMD_E_DVBT2_PP_1=0, DMD_E_DVBT2_PP_2, DMD_E_DVBT2_PP_3, DMD_E_DVBT2_PP_4, DMD_E_DVBT2_PP_5, DMD_E_DVBT2_PP_6, DMD_E_DVBT2_PP_7, DMD_E_DVBT2_PP_8 } DMD_DVBT2_PP_t;
|
|
typedef enum{ DMD_E_DVBT2_PLP_MODE_NO=0, DMD_E_DVBT2_PLP_MODE_NORM, DMD_E_DVBT2_PLP_MODE_HEM } DMD_DVBT2_PLP_MODE_t;
|
|
typedef enum{ DMD_E_DVBT2_PLP_TYPE_COM=0, DMD_E_DVBT2_PLP_TYPE_DAT1, DMD_E_DVBT2_PLP_TYPE_DAT2 } DMD_DVBT2_PLP_TYPE_t;
|
|
typedef enum{ DMD_E_DVBT2_PLP_PAYLOAD_GFPS=0, DMD_E_DVBT2_PLP_PAYLOAD_GCS, DMD_E_DVBT2_PLP_PAYLOAD_GSE, DMD_E_DVBT2_PLP_PAYLOAD_TS } DMD_DVBT2_PLP_PAYLOAD_t;
|
|
typedef enum{ DMD_E_DVBT2_PLP_MOD_QPSK=0, DMD_E_DVBT2_PLP_MOD_16QAM, DMD_E_DVBT2_PLP_MOD_64QAM, DMD_E_DVBT2_PLP_MOD_256QAM } DMD_DVBT2_PLP_MOD_t;
|
|
//ISDBT
|
|
typedef enum{ DMD_E_ISDBT_MODE1=0, DMD_E_ISDBT_MODE2, DMD_E_ISDBT_MODE3 } DMD_ISDBT_MODE_t;
|
|
typedef enum{ DMD_E_ISDBT_GI_1_32=0, DMD_E_ISDBT_GI_1_16,DMD_E_ISDBT_GI_1_8, DMD_E_ISDBT_GI_1_4 } DMD_ISDBT_GI_t;
|
|
typedef enum{ DMD_E_ISDBT_SYS_ISDB_T=0,DMD_E_ISDBT_SYS_ISDBT_SB } DMD_ISDBT_SYS_t;
|
|
typedef enum{ DMD_E_ISDBT_PART_NO_PART=0, DMD_E_ISDBT_PART_PART } DMD_ISDBT_PART_t;
|
|
typedef enum{ DMD_E_ISDBT_CONST_DQPSK=0, DMD_E_ISDBT_CONST_QPSK, DMD_E_ISDBT_CONST_16QAM ,DMD_E_ISDBT_CONST_64QAM } DMD_ISDBT_CONST_t;
|
|
typedef enum{ DMD_E_ISDBT_CR_1_2=0, DMD_E_ISDBT_CR_2_3, DMD_E_ISDBT_CR_3_4, DMD_E_ISDBT_CR_5_6, DMD_E_ISDBT_CR_7_8 } DMD_ISDBT_CR_t;
|
|
//ISDBS
|
|
typedef enum{ DMD_E_ISDB_S_MOD_BPSK_1_2=0,
|
|
DMD_E_ISDB_S_MOD_QPSK_1_2,
|
|
DMD_E_ISDB_S_MOD_QPSK_2_3,
|
|
DMD_E_ISDB_S_MOD_QPSK_3_4,
|
|
DMD_E_ISDB_S_MOD_QPSK_5_6,
|
|
DMD_E_ISDB_S_MOD_QPSK_7_8,
|
|
DMD_E_ISDB_S_MOD_8PSK_2_3 } DMD_ISDBS_MOD_t;
|
|
|
|
//#ifdef __cplusplus
|
|
//}
|
|
//#endif
|
|
|
|
#endif
|