244 lines
8.0 KiB
C
Executable File
244 lines
8.0 KiB
C
Executable File
|
|
#ifndef _ADRV9009_CONFIG_H_
|
|
#define _ADRV9009_CONFIG_H_
|
|
//#include "../type.h"
|
|
|
|
|
|
|
|
typedef enum{
|
|
ADRV9009_0=0,
|
|
ADRV9009_1
|
|
}ADRV9009_NUM;
|
|
|
|
|
|
typedef struct{
|
|
u32 reg00;
|
|
u32 reg01;
|
|
u32 reg0C;
|
|
u32 reg18;
|
|
|
|
u32 cpri_rec_cl_lost;
|
|
u32 ad9528_status_ld;
|
|
|
|
// // reg addr 0x00
|
|
// u8 summary_alarm; // bit4
|
|
// u8 status_code; // bit3-0
|
|
// // reg addr 0x01
|
|
// u8 latched_ver_loacl_LOF; // bit15
|
|
// u8 latched_ver_loacl_LOS; // bit14
|
|
// u8 latched_ver_loacl_RAI; // bit13
|
|
// u8 latched_ver_remote_LOF; // bit12
|
|
// u8 latched_ver_remote_LOS; // bit11
|
|
// u8 latched_ver_remote_SAP; // bit10
|
|
// u8 latched_ver_remote_RAI; // bit9
|
|
// u8 latched_ver_remote_rst; // bit8
|
|
// u8 core_type; // bit7 1-core is a master port, 0 -- core is a slave port
|
|
// u8 core_genered; // bit6 1-core has been generated using a hardware evaluation license
|
|
// u8 local_LOF; // bit1
|
|
// u8 local_LOS; // bit0
|
|
// // reg addr 0x0C Current Line Speed Register
|
|
// u16 speed_index; // bit15
|
|
// // reg addr 0x18 General Debug Register
|
|
}ST_REG_STATUS;
|
|
|
|
|
|
|
|
//---------------------------------------------------------------------------------------
|
|
|
|
#if 1//something may not used
|
|
#define AXI_ADDR_VERSION1 0x86
|
|
#define AXI_ADDR_DPD_CTRL1 0x110
|
|
#define AXI_ADDR_DPD_CTRL2 0x111
|
|
#define AXI_ADDR_DPD_CTRL3 0x112
|
|
#define AXI_ADDR_CFR_CTRL1 0x113
|
|
#define AXI_ADDR_CFR_CTRL2 0x114
|
|
#define AXI_ADDR_SIG_SHIFT 0x115
|
|
#define AXI_ADDR_DPD_FIXDLY 0x116
|
|
#define AXI_ADDR_DPD_AGCPWR 0x117
|
|
#define AXI_ADDR_DPD_TEST 0x118
|
|
#define AXI_ADDR_FBROUTE 0x11A
|
|
#define AXI_ADDR_ERR_CHECK 0x11B
|
|
#define AXI_ADDR_AMP_SAT 0x11C
|
|
#define AXI_ADDR_BW_MODE 0x12D
|
|
#define AXI_ADDR_CRST_TAP_MAP 0x11D
|
|
#define AXI_ADDR_CRST_ADREF_TAP0 0x11E
|
|
#define AXI_ADDR_CRST_ADREF_TAP1 0x11F
|
|
#define AXI_ADDR_CRST_ADREF_TAP2 0x120
|
|
#define AXI_ADDR_CRST_ADREF_TAP3 0x121
|
|
#define AXI_ADDR_CRST_ADREF_TAP4 0x122
|
|
#define AXI_ADDR_CRST_ADREF_TAP5 0x123
|
|
#define AXI_ADDR_CRST_ADREF_TAP6 0x124
|
|
#define AXI_ADDR_CRST_ADREF_TAP7 0x125
|
|
#define AXI_ADDR_CRST_ADREF_TAP8 0x126
|
|
#define AXI_ADDR_CRST_ADREF_TAP9 0x127
|
|
#define AXI_ADDR_CRST_ADREF_TAP10 0x128
|
|
#define AXI_ADDR_CRST_ADREF_TAP11 0x129
|
|
#define AXI_ADDR_CRST_ADREF_TAP12 0x130
|
|
#define AXI_ADDR_CRST_ADREF_TAP13 0x131
|
|
#define AXI_ADDR_CRST_ADREF_TAP14 0x132
|
|
|
|
#define AXI_ADDR_DPD_STATUS1 0x200
|
|
#define AXI_ADDR_DPD_AGCCWORD 0x201
|
|
#define AXI_ADDR_DPD_SYNCOFFSET 0x202
|
|
|
|
/*#define MASK_DPD_ERR (0x0001)
|
|
#define MASK_DPD_PWRHIGH (0x0001<<1)
|
|
#define MASK_DPD_PWRLOW (0x0001<<2)
|
|
#define MASK_DPD_ERR_ABORT (0x0001<<3)
|
|
#define MASK_DPD_TRX_SYNC_OK (0x0001<<4)
|
|
#define MASK_DPD_DAGC_TOOHIGH (0x0001<<5)
|
|
#define MASK_DPD_DAGC_TOOLOW (0x0001<<6)
|
|
|
|
#define DPD_CTRL1_DPD_START (0x0001)
|
|
#define DPD_CTRL1_DPD_ALLCLR (0x0001<<1)
|
|
#define DPD_CTRL1_ALL_BYPS (0x0001<<2)
|
|
|
|
#define DPD_CTRL2_LIN_UPDATE (0x0001)
|
|
#define DPD_CTRL2_NONLIN_UPDATE (0x0001<<1)
|
|
#define DPD_CTRL2_SET_NONLIN_UDP_MOD(x) (((x)&0x07)<<2) //01 : POLY; 10: CRST, 100 SELF
|
|
#define DPD_CTRL2_AMP_CHK (0x0001<<4)
|
|
*/
|
|
#define DPD_CTRL3_FAGC_UPDATE (0x0001)
|
|
#define DPD_CTRL3_FAGC_SLOWDN (0x0001<<1)
|
|
#define DPD_CTRL3_DAGC_UPDATE (0x0001<<2)
|
|
#define DPD_CTRL3_DAGC_SLOWDN (0x0001<<3)
|
|
#define DPD_CTRL3_DCRM_UPDATE (0x0001<<4)
|
|
#define DPD_CTRL3_ROT_UPDATE (0x0001<<5)
|
|
#define DPD_CTRL3_SYNC_UPDATE (0x0001<<6)
|
|
#define DPD_CTRL3_SYNC_RESTART (0x0001<<7)
|
|
#define DPD_CTRL3_IQB_UPDATE (0x0001<<8)
|
|
|
|
#define DPD_SET_100M (0x00)
|
|
#define DPD_SET_25M (0x01)
|
|
|
|
#define SET_DPDFAGC_REFPWR(x) ((x))
|
|
#define DPD_SET_CRST_ADDR_STRUCT_2 ((0x01)<<17)
|
|
#define DPD_SET_ERR_TH(x) (((x)&0xffff))
|
|
#define DPD_SET_ERR_CNT_TH(x) (((x)&0xff)<<16)
|
|
#define DPD_SET_DGAIN(x) (((x)&0xffff)<<2)
|
|
#define DPD_SET_FIX_DLY(x) (0x8000 & ((x)&0x7ff))
|
|
#define DPD_SET_CRST_REFAD(x) ((x)[0] | ((x)[1]<<4) | ((x)[2]<<8) | ((x)[3]<<12) | ((x)[4]<<16) | ((x)[5]<<20))
|
|
|
|
#define DPD_MAX_TX_AMP_SAT 65535
|
|
//#define TX_FREQ_IN_HZ 2595000000
|
|
|
|
//#define TX_FREQ_IN_HZ 3550000000 //3550000000 //h210809 2595000000 => 3550000000
|
|
//#define TX_FREQ_IN_HZ (2595000000*1.024) //3550000000 //h210809 2595000000 => 3550000000
|
|
//#define TX_FREQ_IN_HZ (3550000000*1.024) //3550000000 //h210809 2595000000 => 3550000000
|
|
//#define TX_FREQ_IN_HZ (698000000*1.024) //3550000000 //h210809 2595000000 => 3550000000
|
|
//#define TX_FREQ_IN_HZ (2595000000*1.024) //3550000000 //h210809 2595000000 => 3550000000
|
|
//#define TX_FREQ_IN_HZ (698000000*1.024) //3550000000 //h210809 2595000000 => 3550000000
|
|
|
|
#define TX_FREQ_IN_HZ (300000000) //3550000000 //h210809 2595000000 => 3550000000
|
|
|
|
#define D_SET_ATT 8000
|
|
// note index msg
|
|
enum
|
|
{
|
|
NOTE_M_DPD_STEP = 1,
|
|
NOTE_E_TX_POWER_TOO_MUCH,
|
|
NOTE_FEEDBACK_POWER_LOW,
|
|
NOTE_FEEDBACK_POWER_HIGH,
|
|
NOTE_DPD_ABORT_DUE_TO_LARGE_ERR,
|
|
NOTE_DPD_ABORT_DUE_TO_DAGC_INPUT_LOW,
|
|
NOTE_DPD_ABORT_DUE_TO_DAGC_INPUT_HIGH,
|
|
NOTE_TXRX_SYNC_OK,
|
|
NOTE_TXRX_SYNC_FAILED,
|
|
NOTE_STEP_FINISHED_DO_NEXT_STEP,
|
|
NOTE_STEP_DONE,
|
|
NOTE_STEP_SUCCESS,
|
|
NOTE_PROCESS_ABORT,
|
|
NOTE_END
|
|
};
|
|
|
|
#if 1
|
|
//area1
|
|
#define A1_ADDR_TAP_START 0
|
|
#define A1_ADDR_TAP_STOP 14
|
|
|
|
#define A1_ADDR_SUB_TAP_START 4
|
|
#define A1_ADDR_SUB_TAP_STOP 4
|
|
|
|
#define A1_ADDR_CRST_START 0
|
|
#define A1_ADDR_CRST_STOP 511
|
|
|
|
#define A1_ADDR_WORD_START 1 //����
|
|
#define A1_ADDR_WORD_STOP 0
|
|
|
|
#define A1_TOTAL_LEN ((A1_ADDR_TAP_STOP-A1_ADDR_TAP_START+1)*(A1_ADDR_SUB_TAP_STOP-A1_ADDR_SUB_TAP_START+1)*(A1_ADDR_CRST_STOP-A1_ADDR_CRST_START+1)*(A1_ADDR_WORD_START-A1_ADDR_WORD_STOP+1))
|
|
|
|
//area2
|
|
#define A2_ADDR_TAP_START 4
|
|
#define A2_ADDR_TAP_STOP 10
|
|
|
|
#define A2_ADDR_SUB_TAP_START 2
|
|
#define A2_ADDR_SUB_TAP_STOP 3
|
|
|
|
#define A2_ADDR_CRST_START 0
|
|
#define A2_ADDR_CRST_STOP 1023
|
|
|
|
#define A2_ADDR_WORD_START 3 //����
|
|
#define A2_ADDR_WORD_STOP 0
|
|
|
|
#define A2_TOTAL_LEN ((A2_ADDR_TAP_STOP-A2_ADDR_TAP_START+1)*(A2_ADDR_SUB_TAP_STOP-A2_ADDR_SUB_TAP_START+1)*(A2_ADDR_CRST_STOP-A2_ADDR_CRST_START+1)*(A2_ADDR_WORD_START-A2_ADDR_WORD_STOP+1))
|
|
|
|
//area3
|
|
#define A3_ADDR_TAP_START 4
|
|
#define A3_ADDR_TAP_STOP 10
|
|
|
|
#define A3_ADDR_SUB_TAP_START 0
|
|
#define A3_ADDR_SUB_TAP_STOP 1
|
|
|
|
#define A3_ADDR_CRST_START 0
|
|
#define A3_ADDR_CRST_STOP 1023
|
|
|
|
#define A3_ADDR_WORD_START 4 //����
|
|
#define A3_ADDR_WORD_STOP 0
|
|
|
|
#define A3_TOTAL_LEN ((A3_ADDR_TAP_STOP-A3_ADDR_TAP_START+1)*(A3_ADDR_SUB_TAP_STOP-A3_ADDR_SUB_TAP_START+1)*(A3_ADDR_CRST_STOP-A3_ADDR_CRST_START+1)*(A3_ADDR_WORD_START-A3_ADDR_WORD_STOP+1))
|
|
|
|
|
|
//area4
|
|
#define A4_ADDR_TAP_START 15
|
|
#define A4_ADDR_TAP_STOP 15
|
|
|
|
#define A4_ADDR_SUB_TAP_START 0
|
|
#define A4_ADDR_SUB_TAP_STOP 6
|
|
|
|
#define A4_ADDR_CRST_START 0
|
|
#define A4_ADDR_CRST_STOP 31
|
|
|
|
#define A4_TOTAL_LEN ((A4_ADDR_TAP_STOP-A4_ADDR_TAP_START+1)*(A4_ADDR_SUB_TAP_STOP-A4_ADDR_SUB_TAP_START+1)*(A4_ADDR_CRST_STOP-A4_ADDR_CRST_START+1))
|
|
|
|
#define AREA_TATAL_LEN (A1_TOTAL_LEN+A2_TOTAL_LEN+A3_TOTAL_LEN+A4_TOTAL_LEN)
|
|
#endif
|
|
|
|
|
|
//static int g_dpd_up_flg=E_DPD_IDLE;
|
|
|
|
#define MASK_SPI_EN_SPI1_ENABLE (0x1<<0)
|
|
#define MASK_SPI_EN_SPI2_ENABLE (0x1<<1)
|
|
#define MASK_SPI_EN_EXT_SPI_ENABLE (0x1<<2)
|
|
#define MASK_SPI_EN_MCU_SPI1_ENABLE (0x1<<3)
|
|
|
|
|
|
#endif
|
|
//---------------------------------------------------------------------------------------
|
|
|
|
int adrv9009_cfg(int which_9009);
|
|
int adrv9009_orx_gain_thr();
|
|
void adrv9009_orx_gain_stop(void);
|
|
int Adrv9009_Ext_LOL_Cal_1(int which_9009);
|
|
int Adrv9009_Ext_LOL_Cal_2(int which_9009);
|
|
extern void * status_monitor_thr (void * args);
|
|
extern void read_fpga_version(char *pVer);
|
|
|
|
|
|
extern void adrv9009_init(void);
|
|
extern void chang_freq(uint8 radio_ctl, int freq_changed);
|
|
extern void chang_cw(int cw);
|
|
|
|
|
|
#endif
|
|
|