sync: WIN-BOWEI 2026-08-10 硬编码审计:两个 flow driver 的工程根改读 skills_env.md

- run_fpga_local.py: FPGA_FLOW_ROOT 写死 E:\LangGraph_Design\fpga-goldenref-flow
  -> _env_lookup(FPGA_GOLDENREF_ROOT),未配置时给出明确提示。
- run_imx6_flow.py: DEFAULT_PROJECT 写死 -> _env_lookup(FPGA_IMX6_FLOW_ROOT),
  --project-dir 为空时报错而不是拿错路径继续。
与 sim-rtl-flow / zynq-imx6-flow 已有写法一致。

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
This commit is contained in:
bowei
2026-08-19 12:50:44 +08:00
co-authored by Claude Opus 5
parent e07cfaa6d1
commit 0b5583a5c0
3 changed files with 59 additions and 2 deletions
+29 -1
View File
@@ -18,14 +18,42 @@ removed). CLI + exit codes:
Exit codes: 0 complete · 1 error · 2 interrupted (human action needed) Exit codes: 0 complete · 1 error · 2 interrupted (human action needed)
""" """
import os import os
import re
import sys import sys
import json import json
import uuid import uuid
import argparse import argparse
import sqlite3 import sqlite3
def _env_lookup(key, default=None):
"""Read KEY from the OS environment, else from a ``KEY = value`` line in
~/skills_env.md. Machine-local paths are never hardcoded in a skill; see
the same helper in fpga_flash/scripts/vivado_env.py."""
value = os.environ.get(key)
if value:
return value
path = os.path.join(os.path.expanduser("~"), "skills_env.md")
try:
with open(path, encoding="utf-8") as handle:
for line in handle:
match = re.match(rf"\s*{re.escape(key)}\s*=\s*(.+?)\s*(?:#.*)?$", line)
if match:
found = match.group(1).strip()
if found and not found.startswith("<"):
return found
except OSError:
pass
return default
# Drive the graph in-process: import the app package. # Drive the graph in-process: import the app package.
FPGA_FLOW_ROOT = r"E:\LangGraph_Design\fpga-goldenref-flow" FPGA_FLOW_ROOT = _env_lookup("FPGA_GOLDENREF_ROOT")
if not FPGA_FLOW_ROOT:
raise SystemExit(
"fpga-goldenref-flow 工作流仓库路径未配置:请在 ~/skills_env.md 增加\n"
" FPGA_GOLDENREF_ROOT = <fpga-goldenref-flow 检出目录>"
)
if FPGA_FLOW_ROOT not in sys.path: if FPGA_FLOW_ROOT not in sys.path:
sys.path.insert(0, FPGA_FLOW_ROOT) sys.path.insert(0, FPGA_FLOW_ROOT)
+30 -1
View File
@@ -19,6 +19,7 @@ from __future__ import annotations
import argparse import argparse
import json import json
import os import os
import re
import sys import sys
from pathlib import Path from pathlib import Path
@@ -27,7 +28,30 @@ try:
except Exception: except Exception:
pass pass
DEFAULT_PROJECT = r"E:\LangGraph_Design\FPGA-imx6-flow"
def _env_lookup(key: str, default: str | None = None) -> str | None:
"""Read KEY from the OS environment, else from a ``KEY = value`` line in
~/skills_env.md. Machine-local paths are never hardcoded in a skill; see
the same helper in fpga_flash/scripts/vivado_env.py."""
value = os.environ.get(key)
if value:
return value
path = os.path.join(os.path.expanduser("~"), "skills_env.md")
try:
with open(path, encoding="utf-8") as handle:
for line in handle:
match = re.match(rf"\s*{re.escape(key)}\s*=\s*(.+?)\s*(?:#.*)?$", line)
if match:
found = match.group(1).strip()
if found and not found.startswith("<"):
return found
except OSError:
pass
return default
# The fpga-imx6-flow checkout: FPGA_IMX6_FLOW_ROOT in ~/skills_env.md.
DEFAULT_PROJECT = _env_lookup("FPGA_IMX6_FLOW_ROOT", "")
def _emit(obj: dict, code: int) -> None: def _emit(obj: dict, code: int) -> None:
@@ -57,6 +81,11 @@ def main() -> None:
ap.add_argument("--max-hw-retry", type=int, default=3) ap.add_argument("--max-hw-retry", type=int, default=3)
args = ap.parse_args() args = ap.parse_args()
if not args.project_dir:
_emit({"status": "error",
"error": "fpga-imx6-flow 工作流仓库路径未配置:在 ~/skills_env.md 增加 "
"FPGA_IMX6_FLOW_ROOT = <检出目录>,或用 --project-dir 显式指定"}, 1)
project = Path(args.project_dir) project = Path(args.project_dir)
if not (project / "app" / "main_graph.py").exists(): if not (project / "app" / "main_graph.py").exists():
_emit({"status": "error", _emit({"status": "error",