boweiandClaude Opus 5 0b5583a5c0 sync: WIN-BOWEI 2026-08-10 硬编码审计：两个 flow driver 的工程根改读 skills_env.md ...

- run_fpga_local.py: FPGA_FLOW_ROOT 写死 E:\LangGraph_Design\fpga-goldenref-flow
  -> _env_lookup(FPGA_GOLDENREF_ROOT)，未配置时给出明确提示。
- run_imx6_flow.py: DEFAULT_PROJECT 写死 -> _env_lookup(FPGA_IMX6_FLOW_ROOT)，
  --project-dir 为空时报错而不是拿错路径继续。
与 sim-rtl-flow / zynq-imx6-flow 已有写法一致。

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>

2026-08-19 12:50:44 +08:00

.system/plugin-creator

更新了部分skill

2026-06-22 16:40:24 +08:00

fft-analyse

Portabilize hardcoded C:\Users\bowei paths across skill docs

2026-07-20 20:35:43 +08:00

fpga_flash

sync: WIN-BOWEI 2026-08-10 fpga_flash 增 Zynq BOOT.bin/QSPI 脚本，rtl-ip-replace 与 sim-rtl-flow 更新

2026-08-19 12:50:44 +08:00

fpga_update

vivado: resolve install path from ~/skills_env.md instead of hardcoding D:\Xilinx

2026-07-20 07:48:04 -05:00

fpga-goldenref-flow

sync: WIN-BOWEI 2026-08-10 硬编码审计：两个 flow driver 的工程根改读 skills_env.md

2026-08-19 12:50:44 +08:00

fpga-imx6-flow

sync: WIN-BOWEI 2026-08-10 硬编码审计：两个 flow driver 的工程根改读 skills_env.md

2026-08-19 12:50:44 +08:00

langgraph-plan-review

sync: SHANGHAI-U9 2026-07-27

2026-07-27 01:08:42 +08:00

langgraph-vivado-install

Portabilize hardcoded C:\Users\bowei paths across skill docs

2026-07-20 20:35:43 +08:00

rtl-ip-replace

sync: WIN-BOWEI 2026-08-10 fpga_flash 增 Zynq BOOT.bin/QSPI 脚本，rtl-ip-replace 与 sim-rtl-flow 更新

2026-08-19 12:50:44 +08:00

sim-rtl-flow

sync: WIN-BOWEI 2026-08-10 fpga_flash 增 Zynq BOOT.bin/QSPI 脚本，rtl-ip-replace 与 sim-rtl-flow 更新

2026-08-19 12:50:44 +08:00

simulink_rtl_dev

sync: SHANGHAI-U9 2026-07-27 三个 Simulink→RTL skill 转系统级 + 新增 simulink-rtl-redev

2026-07-27 10:39:53 +08:00

simulink-rtl-redev

sync: SHANGHAI-U9 2026-07-27 三个 Simulink→RTL skill 转系统级 + 新增 simulink-rtl-redev

2026-07-27 10:39:53 +08:00

smod_atsc_dev

imx6: document VM bootstrap, stop hardcoding the cross-compile VM's IP

2026-07-20 08:11:51 -05:00

tools-sync

sync: SHANGHAI-U9 2026-07-27 修复 MCP 双向同步向 Claude 注册失败

2026-07-27 01:15:27 +08:00

vivado-prj-create

vivado: resolve install path from ~/skills_env.md instead of hardcoding D:\Xilinx

2026-07-20 07:48:04 -05:00

vivado-sim

sync: HP_BOWEI 2026-07-27 vivado-sim 去掉写死的 Vivado 盘符路径

2026-07-27 13:56:51 +08:00

zynq-imx6-flow

sync: SHANGHAI-U9 2026-07-27

2026-07-27 01:08:42 +08:00

.gitattributes

Initial commit

2026-05-09 01:12:34 -05:00

.gitignore

gitignore: ignore local-only skill dirs at directory level

2026-07-20 07:22:11 -05:00

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