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2026-05-09 01:12:34 -05:00
commit 61b4731d06
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+{
+  "eval_id": 1,
+  "eval_name": "axis-fifo-handshake-sim",
+  "prompt": "我有一个 AXI-Stream FIFO 模块，接口如下：input clk, input rst_n, input [7:0] s_tdata, input s_tvalid, output s_tready, output [7:0] m_tdata, output m_tvalid, input m_tready, output [3:0] fill_count。请帮我生成 testbench，模拟正常的 tvalid/tready 握手时序，用批处理模式在 Vivado 中运行仿真。",
+  "assertions": []
+}
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+// AXI-Stream FIFO 模块（测试用，深度4）
+module axis_fifo #(
+    parameter DATA_WIDTH = 8,
+    parameter DEPTH      = 4
+)(
+    input  wire                   clk,
+    input  wire                   rst_n,
+    // 从机（写入）端口
+    input  wire [DATA_WIDTH-1:0]  s_tdata,
+    input  wire                   s_tvalid,
+    output wire                   s_tready,
+    // 主机（读出）端口
+    output wire [DATA_WIDTH-1:0]  m_tdata,
+    output wire                   m_tvalid,
+    input  wire                   m_tready
+);
+
+    reg [DATA_WIDTH-1:0] mem [0:DEPTH-1];
+    reg [$clog2(DEPTH):0] wr_ptr, rd_ptr, count;
+
+    assign s_tready = (count < DEPTH);
+    assign m_tvalid = (count > 0);
+    assign m_tdata  = mem[rd_ptr[$clog2(DEPTH)-1:0]];
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            wr_ptr <= 0; rd_ptr <= 0; count <= 0;
+        end else begin
+            if (s_tvalid && s_tready) begin
+                mem[wr_ptr[$clog2(DEPTH)-1:0]] <= s_tdata;
+                wr_ptr <= wr_ptr + 1;
+                count  <= count + 1;
+            end
+            if (m_tvalid && m_tready) begin
+                rd_ptr <= rd_ptr + 1;
+                count  <= count - 1;
+            end
+            // 同时读写（count 保持不变已在上面分开处理，这里修正）
+            if (s_tvalid && s_tready && m_tvalid && m_tready) begin
+                count <= count; // 读写同时，count 不变
+            end
+        end
+    end
+
+endmodule
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+# Vivado 批处理仿真脚本 - AXI-Stream FIFO 测试
+# 测试用例2：用户口头描述接口，生成握手时序激励，批处理模式运行
+
+# 创建仿真工程
+create_project -force sim_proj ./sim_proj -part xc7a200tfbg676-2
+set_property simulator_language Verilog [current_project]
+
+# 添加源文件（被测模块）
+add_files -norecurse ./axis_fifo.v
+
+# 添加仿真文件（testbench）
+add_files -fileset sim_1 -norecurse ./tb_axis_fifo.v
+
+# 设置顶层模块为 testbench
+set_property top tb_axis_fifo [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+
+# 设置仿真运行时间（握手时序需要足够时间）
+set_property -name {xsim.simulate.runtime} -value {2000ns} -objects [get_filesets sim_1]
+
+# 运行仿真（批处理模式，不启动 GUI）
+launch_simulation
+run all
+close_sim
+
+exit
@@ -0,0 +1,118 @@
+`timescale 1ns/1ps
+
+module tb_axis_fifo;
+
+// ---- 参数 ----
+parameter CLK_PERIOD = 10;  // 100 MHz 时钟，周期 10ns
+
+// ---- 信号声明 ----
+reg         clk;
+reg         rst_n;
+
+// AXI-Stream 写端口（Master -> FIFO）
+reg  [7:0]  s_tdata;
+reg         s_tvalid;
+wire        s_tready;
+
+// AXI-Stream 读端口（FIFO -> Slave）
+wire [7:0]  m_tdata;
+wire        m_tvalid;
+reg         m_tready;
+
+// ---- 被测模块例化 ----
+axis_fifo uut (
+    .clk      (clk),
+    .rst_n    (rst_n),
+    .s_tdata  (s_tdata),
+    .s_tvalid (s_tvalid),
+    .s_tready (s_tready),
+    .m_tdata  (m_tdata),
+    .m_tvalid (m_tvalid),
+    .m_tready (m_tready)
+);
+
+// ---- 时钟生成 ----
+initial clk = 0;
+always #(CLK_PERIOD/2) clk = ~clk;
+
+// ---- 任务：发送一个 AXI-Stream 数据包 ----
+task axis_write;
+    input [7:0] data;
+    begin
+        s_tdata  = data;
+        s_tvalid = 1;
+        // 等待 tready 握手完成
+        @(posedge clk);
+        while (!s_tready) @(posedge clk);
+        s_tvalid = 0;
+    end
+endtask
+
+// ---- 任务：读一个 AXI-Stream 数据包 ----
+task axis_read;
+    begin
+        m_tready = 1;
+        // 等待 tvalid 握手完成
+        @(posedge clk);
+        while (!m_tvalid) @(posedge clk);
+        m_tready = 0;
+    end
+endtask
+
+// ---- VCD 波形记录 ----
+initial begin
+    $dumpfile("tb_axis_fifo.vcd");
+    $dumpvars(0, tb_axis_fifo);
+end
+
+// ---- 复位与激励 ----
+initial begin
+    // 初始化所有信号
+    s_tdata  = 8'h00;
+    s_tvalid = 0;
+    m_tready = 0;
+
+    // 复位序列
+    rst_n = 0;
+    repeat(5) @(posedge clk);
+    rst_n = 1;
+    repeat(2) @(posedge clk);
+
+    // 测试1：连续写入 4 个数据
+    $display("[%0t] 开始测试：连续写入4个数据", $time);
+    axis_write(8'hAA);
+    axis_write(8'hBB);
+    axis_write(8'hCC);
+    axis_write(8'hDD);
+    repeat(2) @(posedge clk);
+
+    // 测试2：连续读出 4 个数据
+    $display("[%0t] 开始读出数据", $time);
+    axis_read();
+    axis_read();
+    axis_read();
+    axis_read();
+    repeat(2) @(posedge clk);
+
+    // 测试3：写入同时读出（背压测试）
+    $display("[%0t] 背压测试：写入同时读出", $time);
+    fork
+        begin
+            axis_write(8'h11);
+            axis_write(8'h22);
+            axis_write(8'h33);
+        end
+        begin
+            repeat(3) @(posedge clk);
+            m_tready = 1;
+            repeat(10) @(posedge clk);
+            m_tready = 0;
+        end
+    join
+
+    repeat(10) @(posedge clk);
+    $display("[%0t] 仿真完成", $time);
+    $finish;
+end
+
+endmodule