45 lines
1.5 KiB
Verilog
45 lines
1.5 KiB
Verilog
// AXI-Stream FIFO 模块（测试用，深度4）
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module axis_fifo #(
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parameter DATA_WIDTH = 8,
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parameter DEPTH = 4
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)(
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input wire clk,
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input wire rst_n,
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// 从机（写入）端口
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input wire [DATA_WIDTH-1:0] s_tdata,
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input wire s_tvalid,
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output wire s_tready,
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// 主机（读出）端口
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output wire [DATA_WIDTH-1:0] m_tdata,
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output wire m_tvalid,
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input wire m_tready
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);
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reg [DATA_WIDTH-1:0] mem [0:DEPTH-1];
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reg [$clog2(DEPTH):0] wr_ptr, rd_ptr, count;
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assign s_tready = (count < DEPTH);
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assign m_tvalid = (count > 0);
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assign m_tdata = mem[rd_ptr[$clog2(DEPTH)-1:0]];
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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wr_ptr <= 0; rd_ptr <= 0; count <= 0;
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end else begin
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if (s_tvalid && s_tready) begin
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mem[wr_ptr[$clog2(DEPTH)-1:0]] <= s_tdata;
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wr_ptr <= wr_ptr + 1;
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count <= count + 1;
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end
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if (m_tvalid && m_tready) begin
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rd_ptr <= rd_ptr + 1;
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count <= count - 1;
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end
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// 同时读写（count 保持不变已在上面分开处理，这里修正）
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if (s_tvalid && s_tready && m_tvalid && m_tready) begin
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count <= count; // 读写同时，count 不变
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end
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end
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end
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endmodule |