Initial commit

vivado-sim-workspace/iteration-1/eval-counter/with_skill/outputs/counter8.v

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+// 8位计数器模块
+module counter8 (
+    input  wire        clk,     // 系统时钟
+    input  wire        rst_n,   // 低有效复位
+    input  wire        en,      // 使能信号
+    output reg  [7:0]  count,   // 计数输出
+    output wire        overflow // 溢出标志（count == 8'hFF）
+);
+
+assign overflow = (count == 8'hFF) & en;
+
+always @(posedge clk or negedge rst_n) begin
+    if (!rst_n)
+        count <= 8'h00;
+    else if (en)
+        count <= count + 1'b1;
+end
+
+endmodule