sync: WIN-BOWEI 2026-08-10 fpga_flash 增 Zynq BOOT.bin/QSPI 脚本，rtl-ip-replace 与 sim-rtl-flow 更新

- fpga_flash: 新增 build_zynq_boot.py / program_zynq_qspi.py（bootgen + program_flash，
  含备份、SHA-256/容量/marker 守卫）；vivado_env.py 增 resolve_sdk_dir（SDK_ROOT/SDK_PATH）；
  SKILL.md 补 Zynq 烧写流程，示例去掉写死的 D:\Xilinx\SDK\2018.1，改由 skills_env.md 解析。
- rtl-ip-replace: gen_ip.tcl / namespace_ip.py 更新。
- sim-rtl-flow: SKILL.md 与 run_sim_rtl_flow.py 更新。

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>

fpga_flash/scripts/vivado_env.py

@@ -56,3 +56,23 @@ def resolve_vivado_exe(cli_value=None):
     if exe:
         return exe
     return os.path.join(resolve_vivado_dir(), "bin", "vivado.bat")
+
+
+def resolve_sdk_dir(cli_value=None):
+    """Xilinx SDK install ROOT (the dir containing bin/bootgen.bat).
+
+    Precedence matches the Vivado resolver: explicit CLI value, SDK_ROOT,
+    SDK_PATH, then the same keys in ~/skills_env.md.
+    """
+    if cli_value:
+        return cli_value
+    root = env_lookup("SDK_ROOT")
+    if root:
+        return root
+    exe = env_lookup("SDK_PATH")
+    if exe:
+        return os.path.dirname(os.path.dirname(exe))
+    sys.exit(
+        "Xilinx SDK path not configured. Add `SDK_ROOT = <install root>` to "
+        "~/skills_env.md, set it as an env var, or pass --sdk-dir."
+    )