bowei/skills-win
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
32 Commits 1 Branch 0 Tags
e07cfaa6d1bf979826999621b51238c5dbe05277
T
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
boweiandClaude Opus 5 e07cfaa6d1 sync: WIN-BOWEI 2026-08-10 fpga_flash 增 Zynq BOOT.bin/QSPI 脚本，rtl-ip-replace 与 sim-rtl-flow 更新 
- fpga_flash: 新增 build_zynq_boot.py / program_zynq_qspi.py（bootgen + program_flash，
  含备份、SHA-256/容量/marker 守卫）；vivado_env.py 增 resolve_sdk_dir（SDK_ROOT/SDK_PATH）；
  SKILL.md 补 Zynq 烧写流程，示例去掉写死的 D:\Xilinx\SDK\2018.1，改由 skills_env.md 解析。
- rtl-ip-replace: gen_ip.tcl / namespace_ip.py 更新。
- sim-rtl-flow: SKILL.md 与 run_sim_rtl_flow.py 更新。

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
2026-08-19 12:50:44 +08:00
.system/plugin-creator
更新了部分skill
2026-06-22 16:40:24 +08:00
fft-analyse
Portabilize hardcoded C:\Users\bowei paths across skill docs
2026-07-20 20:35:43 +08:00
fpga_flash
sync: WIN-BOWEI 2026-08-10 fpga_flash 增 Zynq BOOT.bin/QSPI 脚本，rtl-ip-replace 与 sim-rtl-flow 更新
2026-08-19 12:50:44 +08:00
fpga_update
vivado: resolve install path from ~/skills_env.md instead of hardcoding D:\Xilinx
2026-07-20 07:48:04 -05:00
fpga-goldenref-flow
Portabilize hardcoded C:\Users\bowei paths across skill docs
2026-07-20 20:35:43 +08:00
fpga-imx6-flow
imx6: document VM bootstrap, stop hardcoding the cross-compile VM's IP
2026-07-20 08:11:51 -05:00
langgraph-plan-review
sync: SHANGHAI-U9 2026-07-27
2026-07-27 01:08:42 +08:00
langgraph-vivado-install
Portabilize hardcoded C:\Users\bowei paths across skill docs
2026-07-20 20:35:43 +08:00
rtl-ip-replace
sync: WIN-BOWEI 2026-08-10 fpga_flash 增 Zynq BOOT.bin/QSPI 脚本，rtl-ip-replace 与 sim-rtl-flow 更新
2026-08-19 12:50:44 +08:00
sim-rtl-flow
sync: WIN-BOWEI 2026-08-10 fpga_flash 增 Zynq BOOT.bin/QSPI 脚本，rtl-ip-replace 与 sim-rtl-flow 更新
2026-08-19 12:50:44 +08:00
simulink_rtl_dev
sync: SHANGHAI-U9 2026-07-27 三个 Simulink→RTL skill 转系统级 + 新增 simulink-rtl-redev
2026-07-27 10:39:53 +08:00
simulink-rtl-redev
sync: SHANGHAI-U9 2026-07-27 三个 Simulink→RTL skill 转系统级 + 新增 simulink-rtl-redev
2026-07-27 10:39:53 +08:00
smod_atsc_dev
imx6: document VM bootstrap, stop hardcoding the cross-compile VM's IP
2026-07-20 08:11:51 -05:00
tools-sync
sync: SHANGHAI-U9 2026-07-27 修复 MCP 双向同步向 Claude 注册失败
2026-07-27 01:15:27 +08:00
vivado-prj-create
vivado: resolve install path from ~/skills_env.md instead of hardcoding D:\Xilinx
2026-07-20 07:48:04 -05:00
vivado-sim
sync: HP_BOWEI 2026-07-27 vivado-sim 去掉写死的 Vivado 盘符路径
2026-07-27 13:56:51 +08:00
zynq-imx6-flow
sync: SHANGHAI-U9 2026-07-27
2026-07-27 01:08:42 +08:00
.gitattributes
Initial commit
2026-05-09 01:12:34 -05:00
.gitignore
gitignore: ignore local-only skill dirs at directory level
2026-07-20 07:22:11 -05:00
S
Description
No description provided
9 MiB
Languages
Python 64.1%
Tcl 20.2%
PowerShell 10.1%
MATLAB 2.5%
Shell 2.4%
Other 0.7%