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sync: WIN-BOWEI 2026-08-10 fpga_flash 增 Zynq BOOT.bin/QSPI 脚本，rtl-ip-replace 与 sim-rtl-flow 更新

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- fpga_flash: 新增 build_zynq_boot.py / program_zynq_qspi.py（bootgen + program_flash，
  含备份、SHA-256/容量/marker 守卫）；vivado_env.py 增 resolve_sdk_dir（SDK_ROOT/SDK_PATH）；
  SKILL.md 补 Zynq 烧写流程，示例去掉写死的 D:\Xilinx\SDK\2018.1，改由 skills_env.md 解析。
- rtl-ip-replace: gen_ip.tcl / namespace_ip.py 更新。
- sim-rtl-flow: SKILL.md 与 run_sim_rtl_flow.py 更新。

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
This commit is contained in:
bowei
2026-08-19 12:50:44 +08:00
co-authored by Claude Opus 5
parent 7a11bac29d
commit e07cfaa6d1
8 changed files with 712 additions and 31 deletions
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rtl-ip-replace/scripts/gen_ip.tcl
+53 -10
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@@ -32,22 +32,58 @@ foreach ip $ips {
}
switch -- $c(type) {
dist_mem_gen {
# mode {rom} (default) -- constant lookup table, asynchronous read.
# mode {dual_port_ram} -- LUTRAM, port A = write + async read (spo),
# port B = async read (dpo), NO output registers. Use this (not
# blk_mem_gen) whenever the generated RAM needs a DEFINED read of
# the pre-write word while the other port writes the same address:
# a block-RAM primitive leaves the opposite port's read data
# undefined on such a collision (PG058), distributed RAM does not.
# The output registers / write-first read-back stay in the RTL
# wrapper so latency and enb gating remain cycle-identical.
set dmode [opt c mode {rom}]
create_ip -name dist_mem_gen -vendor xilinx.com -library ip -version 8.0 \
-module_name $name -dir $ipdir
set_property -dict [list \
CONFIG.memory_type {rom} \
CONFIG.data_width $c(width) \
CONFIG.depth $c(depth) \
CONFIG.coefficient_file $c(coe) \
] [get_ips $name]
if {$dmode eq "dual_port_ram"} {
set_property -dict [list \
CONFIG.memory_type {dual_port_ram} \
CONFIG.data_width $c(width) \
CONFIG.depth $c(depth) \
CONFIG.input_options {non_registered} \
CONFIG.output_options {non_registered} \
CONFIG.dual_port_address {non_registered} \
CONFIG.input_clock_enable {false} \
CONFIG.default_data {0} \
] [get_ips $name]
} else {
set_property -dict [list \
CONFIG.memory_type {rom} \
CONFIG.data_width $c(width) \
CONFIG.depth $c(depth) \
CONFIG.coefficient_file $c(coe) \
] [get_ips $name]
}
}
blk_mem_gen {
# SDP, common clock, READ_FIRST on the write port, no output register,
# ENA/ENB pins -- matches SimpleDualPortRAM_generic semantics exactly.
# mode {sdp_readfirst_commonclk} (default): SDP, common clock,
# READ_FIRST on the write port, no output register, ENA/ENB pins --
# matches SimpleDualPortRAM_generic semantics exactly.
# mode {tdp_writefirst_commonclk}: TRUE dual port, port A
# WRITE_FIRST (write with read-back), port B READ_FIRST.
# CAUTION: a BRAM primitive does NOT define the port-B read data
# when port A writes the same address in the same cycle; only use
# this when the design provably never collides.
set bmode [opt c mode {sdp_readfirst_commonclk}]
set mtype {Simple_Dual_Port_RAM}
set opa {READ_FIRST}
if {$bmode eq "tdp_writefirst_commonclk"} {
set mtype {True_Dual_Port_RAM}
set opa {WRITE_FIRST}
}
create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 \
-module_name $name -dir $ipdir
set_property -dict [list \
CONFIG.Memory_Type {Simple_Dual_Port_RAM} \
CONFIG.Memory_Type $mtype \
CONFIG.Assume_Synchronous_Clk {true} \
CONFIG.Use_Byte_Write_Enable {false} \
CONFIG.Write_Width_A $c(width) \
@@ -55,12 +91,19 @@ foreach ip $ips {
CONFIG.Read_Width_A $c(width) \
CONFIG.Write_Width_B $c(width) \
CONFIG.Read_Width_B $c(width) \
CONFIG.Operating_Mode_A {READ_FIRST} \
CONFIG.Operating_Mode_A $opa \
CONFIG.Enable_A {Use_ENA_Pin} \
CONFIG.Enable_B {Use_ENB_Pin} \
CONFIG.Register_PortB_Output_of_Memory_Primitives {false} \
CONFIG.Register_PortB_Output_of_Memory_Core {false} \
] [get_ips $name]
if {$bmode eq "tdp_writefirst_commonclk"} {
set_property -dict [list \
CONFIG.Operating_Mode_B {READ_FIRST} \
CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
CONFIG.Register_PortA_Output_of_Memory_Core {false} \
] [get_ips $name]
}
}
fifo_generator {
# guided: mode field carries standard|fwft; depth/width from manifest