sync: SHANGHAI-U9 2026-07-27 三个 Simulink→RTL skill 转系统级 + 新增 simulink-rtl-redev
- simulink_rtl_dev / rtl-ip-replace: 从工程级 .claude/skills 迁到用户级并去工程耦合 (模型名/Notes 文档依赖/工程实测基线移出; addpath 与脚本路径改用户级) - rtl-ip-replace/scripts/gen_cmp_tb.py: Vivado 路径不再写死, 改读 VIVADO_PATH / XILINX_VIVADO (兼容 install root / bin / bin\vivado.bat 三种写法), 回落时提示 去设 skills_env.md 的 VIVADO_PATH - simulink-rtl-redev: 新增。原生模型改动后的仿真模型同步规范, 含两个实测过的工具 check_sync.py (三条时序链新鲜度闸门) 与 measure_k.m (时域/频域/包络三估计器互证) - sim-rtl-flow/SKILL.md: 加入 sync_sim:* 步骤, 引用上述三个 skill
This commit is contained in:
bowei
@@ -0,0 +1,208 @@
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function rep = audit_hdl_blocks(target, varargin)
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%AUDIT_HDL_BLOCKS Policy audit of an RTL-bound Simulink subtree (Task12-1).
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%
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% Rule 1: everything under a subsystem that is going to be turned into RTL must
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% be built from Simulink blocks that generate RTL directly -- no embedded
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% MATLAB (m) code.
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% Rule 2: an m-code block is only acceptable if a specific Xilinx IP is named
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% as its replacement AND the swap is proven cycle-true by simulation. Such
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% blocks must be listed in the exemptions file, with evidence.
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%
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% rep = AUDIT_HDL_BLOCKS('model/HdlSubsystem')
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% rep = AUDIT_HDL_BLOCKS(..., 'Exemptions', 'Notes/hdl_mcode_exemptions.json')
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% rep = AUDIT_HDL_BLOCKS(..., 'Out', 'hdl_audit.json')
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%
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% The report (struct + JSON) lists every offending block with the metrics
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% needed to plan its migration: script size, persistent state, loops, ports,
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% and a suggested native-block replacement.
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%
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% Verdict: PASS no m-code in the subtree
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% EXEMPT all m-code blocks are listed as exempted (evidence is
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% checked separately by check_exemptions.py)
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% VIOLATION at least one undocumented m-code block
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p = inputParser;
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p.addParameter('Exemptions', '');
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p.addParameter('Out', '');
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p.parse(varargin{:});
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exFile = p.Results.Exemptions;
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outFile = p.Results.Out;
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parts = strsplit(target, '/');
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model = parts{1};
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if ~bdIsLoaded(model)
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load_system(model);
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end
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opts = {'LookUnderMasks', 'all', 'FollowLinks', 'on'};
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blocks = find_system(target, opts{:}, 'Type', 'Block');
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% ---- classification ------------------------------------------------------
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% VIOLATION: behaviour written in m code (or opaque to HDL Coder)
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% WARN : Stateflow control constructs -- allowed for control only, must be
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% justified; they are not the "embedded m language" this rule targets
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% but they still hide code from review.
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VIOL_SF = {'MATLAB Function', 'Truth Table'};
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WARN_SF = {'Chart', 'State Transition Table'};
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VIOL_BT = {'MATLABSystem', 'S-Function', 'M-S-Function', 'Fcn', 'MATLABFcn'};
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exempt = local_read_exemptions(exFile);
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items = struct('block', {}, 'kind', {}, 'severity', {}, 'lines', {}, ...
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'persistent_state', {}, 'loops', {}, 'n_in', {}, 'n_out', {}, ...
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'suggestion', {}, 'exempt', {}, 'xilinx_ip', {});
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% Stateflow blocks carry an internal ' SFunction ' child; report the owner, not
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% its implementation detail.
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sfOwners = {};
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for k = 1:numel(blocks)
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if strcmp(get_param(blocks{k}, 'BlockType'), 'SubSystem')
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try
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t = get_param(blocks{k}, 'SFBlockType');
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if ~isempty(t) && ~strcmp(t, 'NONE'), sfOwners{end+1} = blocks{k}; end %#ok<AGROW>
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catch
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end
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end
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end
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for k = 1:numel(blocks)
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blk = blocks{k};
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bt = get_param(blk, 'BlockType');
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sfType = '';
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if strcmp(bt, 'SubSystem')
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try, sfType = get_param(blk, 'SFBlockType'); catch, sfType = ''; end
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end
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if isempty(sfType) && any(cellfun(@(o) startsWith(blk, [o '/']), sfOwners))
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continue % inside a Stateflow block already accounted for
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end
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if any(strcmp(sfType, VIOL_SF))
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kind = sfType; sev = 'VIOLATION';
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elseif any(strcmp(sfType, WARN_SF))
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kind = sfType; sev = 'WARN';
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elseif any(strcmp(bt, VIOL_BT))
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kind = bt; sev = 'VIOLATION';
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else
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continue
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end
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[nl, hasPersist, hasLoop, script] = local_script_metrics(blk, kind);
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ph = get_param(blk, 'PortHandles');
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isEx = any(strcmp(blk, {exempt.block}));
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ip = '';
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if isEx
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ip = exempt(strcmp(blk, {exempt.block})).xilinx_ip;
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sev = 'EXEMPT';
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end
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items(end+1) = struct( ...
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'block', blk, 'kind', kind, 'severity', sev, 'lines', nl, ...
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'persistent_state', hasPersist, 'loops', hasLoop, ...
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'n_in', numel(ph.Inport), 'n_out', numel(ph.Outport), ...
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'suggestion', local_suggest(script), 'exempt', isEx, 'xilinx_ip', ip); %#ok<AGROW>
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end
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nViol = sum(strcmp({items.severity}, 'VIOLATION'));
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nWarn = sum(strcmp({items.severity}, 'WARN'));
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nEx = sum(strcmp({items.severity}, 'EXEMPT'));
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if nViol > 0
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verdict = 'VIOLATION';
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elseif nEx > 0
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verdict = 'EXEMPT';
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else
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verdict = 'PASS';
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end
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rep = struct('target', target, 'model', model, ...
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'generated_at', datestr(now, 'yyyy-mm-dd HH:MM:SS'), ...
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'exemptions_file', exFile, 'n_blocks_scanned', numel(blocks), ...
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'n_violation', nViol, 'n_warn', nWarn, 'n_exempt', nEx, ...
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'verdict', verdict, 'items', {items});
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% ---- report --------------------------------------------------------------
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fprintf('\n=== HDL m-code audit: %s ===\n', target);
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fprintf('scanned %d block(s)\n', numel(blocks));
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for k = 1:numel(items)
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it = items(k);
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fprintf(' [%-9s] %-11s %s\n', it.severity, it.kind, it.block);
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fprintf(' %d line(s), persistent=%d, loops=%d, %d in / %d out\n', ...
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it.lines, it.persistent_state, it.loops, it.n_in, it.n_out);
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if ~isempty(it.xilinx_ip)
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fprintf(' exempt -> Xilinx IP: %s\n', it.xilinx_ip);
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elseif ~isempty(it.suggestion)
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fprintf(' suggest: %s\n', it.suggestion);
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end
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end
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fprintf('VERDICT: %s (violation=%d warn=%d exempt=%d)\n\n', verdict, nViol, nWarn, nEx);
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if ~isempty(outFile)
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fid = fopen(outFile, 'w');
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fwrite(fid, jsonencode(rep));
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fclose(fid);
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fprintf('report -> %s\n', outFile);
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end
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end
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% -------------------------------------------------------------------------
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function ex = local_read_exemptions(f)
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ex = struct('block', {}, 'xilinx_ip', {});
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if isempty(f) || ~isfile(f)
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return
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end
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raw = jsondecode(fileread(f));
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if isfield(raw, 'exemptions')
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raw = raw.exemptions;
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end
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if isstruct(raw)
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raw = num2cell(raw);
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end
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for i = 1:numel(raw)
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e = raw{i};
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ip = '';
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if isfield(e, 'xilinx_ip'), ip = e.xilinx_ip; end
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ex(end+1) = struct('block', e.block, 'xilinx_ip', ip); %#ok<AGROW>
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end
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end
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function [nl, hasPersist, hasLoop, script] = local_script_metrics(blk, kind)
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script = '';
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nl = 0; hasPersist = false; hasLoop = false;
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if ~strcmp(kind, 'MATLAB Function')
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return
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end
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try
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c = sfroot().find('-isa', 'Stateflow.EMChart', 'Path', blk);
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if isempty(c), return, end
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script = c(1).Script;
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nl = numel(strsplit(script, newline));
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hasPersist = ~isempty(regexp(script, '\<persistent\>', 'once'));
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hasLoop = ~isempty(regexp(script, '^\s*(for|while)\>', 'once', 'lineanchors'));
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catch
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end
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end
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function s = local_suggest(script)
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%LOCAL_SUGGEST keyword -> native Simulink block hints (see reference/block_substitutions.md)
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s = '';
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if isempty(script), return, end
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hits = {};
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map = { ...
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'\<(sin|cos)\s*\(', 'Sine/Cosine: NCO HDL Optimized or Direct Lookup Table (n-D)'; ...
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'\<atan2?\s*\(', 'atan/atan2: Complex to Magnitude-Angle HDL Optimized (CORDIC)'; ...
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'\<(sqrt|abs)\s*\(', 'sqrt/abs: Sqrt HDL Optimized / Complex to Magnitude-Angle HDL Optimized'; ...
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'\<(filter|conv)\s*\(', 'FIR: Discrete FIR Filter (HDL) -- keeps taps as a block parameter'; ...
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'persistent\s+\w*(buf|mem|ram|dl)', 'sample memory: Simple Dual Port RAM / Delay / Tapped Delay'; ...
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'\<(fft|ifft)\s*\(', 'FFT: FFT HDL Optimized'; ...
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'switch\s+\w*(state|st)\>', 'control FSM: Stateflow Chart (control only, no datapath math)'; ...
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'\<mod\s*\(|\+\s*1\s*;.*count', 'counter: HDL Counter / Counter Free-Running'};
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for i = 1:size(map, 1)
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if ~isempty(regexp(script, map{i,1}, 'once'))
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hits{end+1} = map{i,2}; %#ok<AGROW>
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end
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end
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if isempty(hits)
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s = 'no keyword match -- rebuild from primitives (Delay/Product/Sum/Switch/Lookup Table)';
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else
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s = strjoin(hits, ' | ');
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end
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end
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@@ -0,0 +1,116 @@
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#!/usr/bin/env python3
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"""Gate for rule 2 of Task12-1: an m-code block inside an RTL-bound subtree is
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acceptable ONLY if a specific Xilinx IP is named as its replacement AND the swap
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is proven cycle-true by simulation.
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python check_exemptions.py <hdl_audit.json> [<exemptions.json>]
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Exit code 0 = the subtree may go to makehdl / synthesis:
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every m-code block is either gone, or exempted with (a) a named Xilinx IP and
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(b) an evidence file whose first line is PASS (rtl-ip-replace cmp_result.txt).
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Exit code 1 = blocked, with the reason printed per block.
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Evidence paths are resolved relative to the repo root (the directory containing
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Notes/), or absolutely.
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"""
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import json, os, sys
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REQUIRED = ('block', 'reason', 'xilinx_ip', 'cycle_true_evidence', 'approved_by', 'date')
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def repo_root(start):
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d = os.path.abspath(start)
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while True:
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if os.path.isdir(os.path.join(d, 'Notes')) or os.path.isdir(os.path.join(d, '.git')):
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return d
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nd = os.path.dirname(d)
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if nd == d:
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return os.path.abspath(start)
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d = nd
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def evidence_ok(path, roots):
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tried = []
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for r in ([''] if os.path.isabs(path) else roots):
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p = path if os.path.isabs(path) else os.path.join(r, path)
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tried.append(p)
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if os.path.isfile(p):
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first = open(p, errors='replace').readline().strip()
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if not first.upper().startswith('PASS'):
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return False, f'evidence is not a PASS: "{first}" ({p})'
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return True, first
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return False, 'evidence file not found: ' + ' | '.join(tried)
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def main():
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argv = [a for a in sys.argv[1:] if not a.startswith('--root=')]
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root_opt = [a.split('=', 1)[1] for a in sys.argv[1:] if a.startswith('--root=')]
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if not argv:
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sys.exit(__doc__)
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audit = json.load(open(argv[0], encoding='utf-8-sig'))
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exf = argv[1] if len(argv) > 1 else audit.get('exemptions_file') or ''
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roots = [r for r in (root_opt + [repo_root(os.getcwd()),
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repo_root(os.path.dirname(os.path.abspath(argv[0])) or '.'),
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os.getcwd()]) if r]
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items = audit.get('items') or []
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if isinstance(items, dict):
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items = [items]
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mcode = [i for i in items if i['severity'] in ('VIOLATION', 'EXEMPT')]
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warns = [i for i in items if i['severity'] == 'WARN']
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ex = []
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if exf and os.path.isfile(exf):
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raw = json.load(open(exf, encoding='utf-8-sig'))
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ex = raw.get('exemptions', raw if isinstance(raw, list) else [])
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by_block = {e.get('block'): e for e in ex}
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print(f"target : {audit.get('target')}")
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print(f"root : {roots[0]}")
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print(f"audit : {len(items)} flagged block(s) "
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f"({len(mcode)} m-code, {len(warns)} stateflow-warn)")
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print(f"exempt : {exf or '(none)'}\n")
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problems = []
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for it in mcode:
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blk = it['block']
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e = by_block.get(blk)
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if not e:
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problems.append(f"{blk}\n m-code with no exemption entry -- rebuild it from "
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f"native Simulink blocks, or file an exemption (rule 2).")
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print(f" [BLOCKED ] {blk}")
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continue
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missing = [k for k in REQUIRED if not str(e.get(k, '')).strip()]
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if missing:
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problems.append(f"{blk}\n exemption is incomplete: missing {', '.join(missing)}")
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print(f" [BLOCKED ] {blk} (incomplete exemption)")
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continue
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ok, info = evidence_ok(e['cycle_true_evidence'], roots)
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if not ok:
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problems.append(f"{blk}\n {info}")
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print(f" [BLOCKED ] {blk} ({info})")
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continue
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print(f" [EXEMPT ] {blk}\n IP: {e['xilinx_ip']}\n"
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f" cycle-true: {info} [{e['cycle_true_evidence']}]")
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for it in warns:
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print(f" [WARN ] {it['block']} ({it['kind']}) -- control-only Stateflow is tolerated; "
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f"no datapath arithmetic in it")
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stale = [b for b in by_block if b not in {i['block'] for i in items}]
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for b in stale:
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print(f" [STALE ] exemption for a block that is no longer m-code (or gone): {b}")
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if problems:
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print(f'\nGATE: BLOCKED -- {len(problems)} problem(s)\n')
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for p in problems:
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print(' * ' + p)
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print('\nRule (Task12-1): an RTL-bound subsystem and everything under it must be built '
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'from Simulink blocks that generate RTL directly; embedded m code is allowed only '
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'against a named Xilinx IP, proven cycle-true.')
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sys.exit(1)
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print('\nGATE: PASS -- no undocumented m code in the RTL-bound subtree')
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if __name__ == '__main__':
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main()
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@@ -0,0 +1,64 @@
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function ok = check_hdl_support(target, varargin)
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%CHECK_HDL_SUPPORT HDL Coder compatibility check for an RTL-bound subsystem.
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%
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% ok = CHECK_HDL_SUPPORT('model/HdlSubsystem')
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% ok = CHECK_HDL_SUPPORT(..., 'Out', 'hdl_support.txt')
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%
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% Wraps checkhdl: catches blocks that cannot become RTL at all -- the other
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% half of Task12-1 rule 1 ("must be built from blocks that generate RTL
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% directly"). The m-code policy audit is audit_hdl_blocks.m; run both.
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p = inputParser;
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p.addParameter('Out', '');
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p.parse(varargin{:});
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model = strtok(target, '/');
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if ~bdIsLoaded(model)
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load_system(model);
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end
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txt = '';
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threw = false;
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try
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txt = evalc('checkhdl(target)');
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catch e
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threw = true;
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txt = sprintf('checkhdl threw: %s\n%s', e.identifier, e.message);
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end
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% The summary line is localised ("0 个错误、2 个警告" / "0 errors, 2 warnings"),
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% so count both spellings rather than grepping for the word "error".
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nErr = local_count(txt, {'(\d+)\s*个错误', '(\d+)\s+errors?'});
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nWarn = local_count(txt, {'(\d+)\s*个警告', '(\d+)\s+warnings?'});
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ok = ~threw && nErr == 0;
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rep = regexp(txt, '(?<=file:///)[^''"<>]*_report\.html', 'match', 'once');
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fprintf('=== checkhdl %s : %s (%d error(s), %d warning(s)) ===\n', ...
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target, string(ok), nErr, nWarn);
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if ~isempty(rep)
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fprintf('report: %s\n', strrep(rep, '/', filesep));
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end
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disp(txt);
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if nWarn > 0
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fprintf(['NOTE: warnings are not a pass/fail gate here, but read them -- they are usually\n' ...
|
||||
' "this block will cost you area/latency in RTL" hints.\n']);
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||||
end
|
||||
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if ~isempty(p.Results.Out)
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fid = fopen(p.Results.Out, 'w');
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fwrite(fid, txt);
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fclose(fid);
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fprintf('checkhdl log -> %s\n', p.Results.Out);
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||||
end
|
||||
end
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||||
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||||
function n = local_count(txt, pats)
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n = 0;
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||||
for i = 1:numel(pats)
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t = regexp(txt, pats{i}, 'tokens', 'once');
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if ~isempty(t)
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n = str2double(t{1});
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||||
return
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||||
end
|
||||
end
|
||||
end
|
||||
@@ -0,0 +1,17 @@
|
||||
{
|
||||
"_README": "Rule 2 of Task12-1: m code inside an RTL-bound subtree is only acceptable against a NAMED Xilinx IP, proven cycle-true. Copy this file to Notes/<model>_mcode_exemptions.json and fill it in. Every field is mandatory; check_exemptions.py rejects the entry otherwise.",
|
||||
"model": "dpd_ntn_05",
|
||||
"hdl_target": "dpd_ntn_05/DpdAlign_HDL",
|
||||
"exemptions": [
|
||||
{
|
||||
"block": "dpd_ntn_05/DpdAlign_HDL/RxAlign_HDL/RxAlignCore",
|
||||
"reason": "为什么原生 Simulink 模块搭不出来(必须具体:算法结构/时序/资源,不接受“太麻烦”)",
|
||||
"xilinx_ip": "cordic 6.0 (Arc_Tan) + dist_mem_gen sin/cos ROM + blk_mem_gen SDP",
|
||||
"ip_scope": "IP 覆盖的范围;剩下仍由 m 代码实现的部分要写清楚,它们仍然是欠账",
|
||||
"cycle_true_evidence": "vivado/rtl_ip/dpd_ntn_05/cmp/cmp_result.txt",
|
||||
"evidence_kind": "rtl-ip-replace 双 DUT 逐拍对比(首行须为 PASS)",
|
||||
"approved_by": "bowei",
|
||||
"date": "2026-07-24"
|
||||
}
|
||||
]
|
||||
}
|
||||
@@ -0,0 +1,50 @@
|
||||
function hits = hdl_block_search(varargin)
|
||||
%HDL_BLOCK_SEARCH Find a native, RTL-generatable Simulink block (Task12-1 rule 1).
|
||||
%
|
||||
% hdl_block_search list every block in the HDL Coder library
|
||||
% hdl_block_search('ram') blocks whose name matches a keyword
|
||||
% hdl_block_search('sin','cos') several keywords (OR)
|
||||
%
|
||||
% Source of truth is the HDL Coder block library (hdlsllib) plus the HDL
|
||||
% Optimized blocks of DSP HDL / Wireless HDL / Vision HDL: anything in there
|
||||
% generates RTL directly, so it is a legal building block. Anything NOT in
|
||||
% there needs checkhdl before you rely on it.
|
||||
|
||||
% Sub-libraries are listed individually: the top-level DSP HDL library holds
|
||||
% links, which find_system will not walk into.
|
||||
libs = {'hdlsllib', ... % HDL Coder baseline set
|
||||
'dsphdlfiltering2', 'dsphdlmathfun2', ... % FIR/CIC/LMS/Biquad, CORDIC
|
||||
'dsphdlxfrm2', 'dsphdlsigops2', 'dsphdlsrcs2', ...% FFT/IFFT, Farrow/NCO/resample
|
||||
'whdllib', 'visionhdllib'};
|
||||
hits = {};
|
||||
for i = 1:numel(libs)
|
||||
try
|
||||
load_system(libs{i});
|
||||
catch
|
||||
continue
|
||||
end
|
||||
blks = find_system(libs{i}, 'SearchDepth', 5, 'Type', 'Block');
|
||||
for k = 1:numel(blks)
|
||||
nm = strrep(get_param(blks{k}, 'Name'), newline, ' ');
|
||||
if isempty(varargin) || any(cellfun(@(p) ~isempty(regexpi(nm, p, 'once')), varargin))
|
||||
hits{end+1, 1} = nm; %#ok<AGROW>
|
||||
hits{end, 2} = blks{k}; %#ok<AGROW>
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
if isempty(hits)
|
||||
fprintf(['no HDL library block matches %s\n' ...
|
||||
'-> if you cannot build it from these blocks, rule 2 applies: name the Xilinx IP\n' ...
|
||||
' that will implement it, prove the swap cycle-true, and file the exemption.\n'], ...
|
||||
strjoin(varargin, ', '));
|
||||
return
|
||||
end
|
||||
|
||||
[~, ia] = unique(hits(:, 1));
|
||||
hits = hits(sort(ia), :);
|
||||
fprintf('%d HDL-generatable block(s):\n', size(hits, 1));
|
||||
for k = 1:size(hits, 1)
|
||||
fprintf(' %-42s %s\n', hits{k, 1}, hits{k, 2});
|
||||
end
|
||||
end
|
||||
Reference in New Issue
Block a user