597 lines
26 KiB
Tcl
597 lines
26 KiB
Tcl
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################################################################
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# This is a generated script based on design: design_1
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#
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# Though there are limitations about the generated script,
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# the main purpose of this utility is to make learning
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# IP Integrator Tcl commands easier.
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################################################################
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namespace eval _tcl {
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proc get_script_folder {} {
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set script_path [file normalize [info script]]
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set script_folder [file dirname $script_path]
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return $script_folder
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}
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}
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variable script_folder
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set script_folder [_tcl::get_script_folder]
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################################################################
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# Check if script is running in correct Vivado version.
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################################################################
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set scripts_vivado_version 2018.1
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set current_vivado_version [version -short]
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if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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puts ""
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catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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return 1
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}
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################################################################
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# START
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################################################################
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# To test this script, run the following commands from Vivado Tcl console:
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# source design_1_script.tcl
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# If there is no project opened, this script will create a
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# project, but make sure you do not have an existing project
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# <./myproj/project_1.xpr> in the current working folder.
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set list_projs [get_projects -quiet]
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if { $list_projs eq "" } {
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create_project project_1 myproj -part xc7z035ffg676-2
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}
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# CHANGE DESIGN NAME HERE
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variable design_name
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set design_name design_1
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# If you do not already have an existing IP Integrator design open,
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# you can create a design using the following command:
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# create_bd_design $design_name
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# Creating design if needed
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set errMsg ""
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set nRet 0
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set cur_design [current_bd_design -quiet]
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set list_cells [get_bd_cells -quiet]
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if { ${design_name} eq "" } {
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# USE CASES:
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# 1) Design_name not set
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set errMsg "Please set the variable <design_name> to a non-empty value."
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set nRet 1
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} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
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# USE CASES:
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# 2): Current design opened AND is empty AND names same.
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# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
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# 4): Current design opened AND is empty AND names diff; design_name exists in project.
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if { $cur_design ne $design_name } {
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common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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set design_name [get_property NAME $cur_design]
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}
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common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
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} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
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# USE CASES:
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# 5) Current design opened AND has components AND same names.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 1
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} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
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# USE CASES:
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# 6) Current opened design, has components, but diff names, design_name exists in project.
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# 7) No opened design, design_name exists in project.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 2
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} else {
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# USE CASES:
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# 8) No opened design, design_name not in project.
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# 9) Current opened design, has components, but diff names, design_name not in project.
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common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
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create_bd_design $design_name
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common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
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current_bd_design $design_name
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}
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common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
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if { $nRet != 0 } {
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catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
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return $nRet
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}
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set bCheckIPsPassed 1
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##################################################################
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# CHECK IPs
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##################################################################
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set bCheckIPs 1
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if { $bCheckIPs == 1 } {
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set list_check_ips "\
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xilinx.com:ip:axi_bram_ctrl:4.0\
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xilinx.com:ip:smartconnect:1.0\
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xilinx.com:ip:processing_system7:5.5\
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xilinx.com:ip:proc_sys_reset:5.0\
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"
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set list_ips_missing ""
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common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
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foreach ip_vlnv $list_check_ips {
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set ip_obj [get_ipdefs -all $ip_vlnv]
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if { $ip_obj eq "" } {
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lappend list_ips_missing $ip_vlnv
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}
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}
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if { $list_ips_missing ne "" } {
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catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
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set bCheckIPsPassed 0
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}
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}
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if { $bCheckIPsPassed != 1 } {
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common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
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return 3
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}
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##################################################################
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# DESIGN PROCs
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##################################################################
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# Procedure to create entire design; Provide argument to make
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# procedure reusable. If parentCell is "", will use root.
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proc create_root_design { parentCell } {
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variable script_folder
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variable design_name
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if { $parentCell eq "" } {
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set parentCell [get_bd_cells /]
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}
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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}
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# Save current instance; Restore later
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set oldCurInst [current_bd_instance .]
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# Set parent object as current
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current_bd_instance $parentObj
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# Create interface ports
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set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
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set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
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set REG_INF [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:bram_rtl:1.0 REG_INF ]
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set_property -dict [ list \
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CONFIG.MASTER_TYPE {BRAM_CTRL} \
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CONFIG.READ_WRITE_MODE {READ_WRITE} \
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] $REG_INF
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set REG_INF1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:bram_rtl:1.0 REG_INF1 ]
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set_property -dict [ list \
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CONFIG.MASTER_TYPE {BRAM_CTRL} \
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CONFIG.READ_WRITE_MODE {READ_WRITE} \
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] $REG_INF1
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set SPI0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:spi_rtl:1.0 SPI0 ]
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set SPI1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:spi_rtl:1.0 SPI1 ]
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# Create ports
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set FCLK_CLK0 [ create_bd_port -dir O -type clk FCLK_CLK0 ]
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set FCLK_RESET0_N [ create_bd_port -dir O -from 0 -to 0 -type rst FCLK_RESET0_N ]
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set GPIO_EMIO_gpio_i [ create_bd_port -dir I -from 63 -to 0 GPIO_EMIO_gpio_i ]
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set GPIO_EMIO_gpio_o [ create_bd_port -dir O -from 63 -to 0 GPIO_EMIO_gpio_o ]
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set GPIO_EMIO_gpio_t [ create_bd_port -dir O -from 63 -to 0 GPIO_EMIO_gpio_t ]
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# Create instance: axi_bram_ctrl_0, and set properties
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set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.0 axi_bram_ctrl_0 ]
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set_property -dict [ list \
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CONFIG.SINGLE_PORT_BRAM {1} \
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] $axi_bram_ctrl_0
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# Create instance: axi_bram_ctrl_1, and set properties
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set axi_bram_ctrl_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.0 axi_bram_ctrl_1 ]
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set_property -dict [ list \
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CONFIG.SINGLE_PORT_BRAM {1} \
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] $axi_bram_ctrl_1
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# Create instance: axi_smc, and set properties
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set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ]
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set_property -dict [ list \
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CONFIG.NUM_MI {2} \
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CONFIG.NUM_SI {1} \
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] $axi_smc
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# Create instance: processing_system7_0, and set properties
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set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
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set_property -dict [ list \
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CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
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CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
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CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
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CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {50.000000} \
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CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
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CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
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CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {100.000000} \
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CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {166.666672} \
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CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
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CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
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CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
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CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
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CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
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CONFIG.PCW_CLK0_FREQ {50000000} \
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CONFIG.PCW_CLK1_FREQ {10000000} \
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CONFIG.PCW_CLK2_FREQ {10000000} \
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CONFIG.PCW_CLK3_FREQ {10000000} \
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CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
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CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
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CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
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CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
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CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
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CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
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CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {4} \
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CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
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CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
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CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
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CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
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CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
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CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
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CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
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CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
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CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
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CONFIG.PCW_ENET0_RESET_ENABLE {0} \
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CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
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CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
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CONFIG.PCW_ENET1_RESET_ENABLE {0} \
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CONFIG.PCW_ENET_RESET_ENABLE {0} \
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CONFIG.PCW_EN_CLK0_PORT {1} \
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CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \
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CONFIG.PCW_EN_EMIO_GPIO {1} \
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CONFIG.PCW_EN_EMIO_SDIO1 {0} \
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CONFIG.PCW_EN_EMIO_SPI0 {1} \
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CONFIG.PCW_EN_EMIO_SPI1 {1} \
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CONFIG.PCW_EN_EMIO_UART0 {0} \
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CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \
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CONFIG.PCW_EN_ENET0 {1} \
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CONFIG.PCW_EN_QSPI {1} \
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CONFIG.PCW_EN_RST0_PORT {1} \
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CONFIG.PCW_EN_SDIO0 {0} \
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CONFIG.PCW_EN_SDIO1 {1} \
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CONFIG.PCW_EN_SPI0 {1} \
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CONFIG.PCW_EN_SPI1 {1} \
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CONFIG.PCW_EN_UART0 {1} \
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CONFIG.PCW_EN_UART1 {1} \
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CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
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CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {4} \
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CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
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CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
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CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
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CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
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CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
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CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
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CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \
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CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {50} \
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CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
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CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
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CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
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CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
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CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \
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CONFIG.PCW_GPIO_EMIO_GPIO_IO {64} \
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CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \
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CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
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CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
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CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
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CONFIG.PCW_IRQ_F2P_INTR {0} \
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CONFIG.PCW_MIO_14_DIRECTION {in} \
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CONFIG.PCW_MIO_14_IOTYPE {<Select>} \
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CONFIG.PCW_MIO_14_PULLUP {enabled} \
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CONFIG.PCW_MIO_14_SLEW {slow} \
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CONFIG.PCW_MIO_15_DIRECTION {out} \
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CONFIG.PCW_MIO_15_IOTYPE {<Select>} \
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CONFIG.PCW_MIO_15_PULLUP {enabled} \
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CONFIG.PCW_MIO_15_SLEW {slow} \
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CONFIG.PCW_MIO_16_DIRECTION {out} \
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CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_16_PULLUP {enabled} \
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CONFIG.PCW_MIO_16_SLEW {fast} \
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CONFIG.PCW_MIO_17_DIRECTION {out} \
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CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_17_PULLUP {enabled} \
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CONFIG.PCW_MIO_17_SLEW {fast} \
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CONFIG.PCW_MIO_18_DIRECTION {out} \
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CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_18_PULLUP {enabled} \
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CONFIG.PCW_MIO_18_SLEW {fast} \
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CONFIG.PCW_MIO_19_DIRECTION {out} \
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CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_19_PULLUP {enabled} \
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CONFIG.PCW_MIO_19_SLEW {fast} \
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CONFIG.PCW_MIO_1_DIRECTION {out} \
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CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_1_PULLUP {enabled} \
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CONFIG.PCW_MIO_1_SLEW {slow} \
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CONFIG.PCW_MIO_20_DIRECTION {out} \
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CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_20_PULLUP {enabled} \
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CONFIG.PCW_MIO_20_SLEW {fast} \
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CONFIG.PCW_MIO_21_DIRECTION {out} \
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CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_21_PULLUP {enabled} \
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CONFIG.PCW_MIO_21_SLEW {fast} \
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CONFIG.PCW_MIO_22_DIRECTION {in} \
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CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_22_PULLUP {enabled} \
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CONFIG.PCW_MIO_22_SLEW {fast} \
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CONFIG.PCW_MIO_23_DIRECTION {in} \
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CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_23_PULLUP {enabled} \
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CONFIG.PCW_MIO_23_SLEW {fast} \
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CONFIG.PCW_MIO_24_DIRECTION {in} \
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CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_24_PULLUP {enabled} \
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CONFIG.PCW_MIO_24_SLEW {fast} \
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CONFIG.PCW_MIO_25_DIRECTION {in} \
|
|
CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_25_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_25_SLEW {fast} \
|
|
CONFIG.PCW_MIO_26_DIRECTION {in} \
|
|
CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_26_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_26_SLEW {fast} \
|
|
CONFIG.PCW_MIO_27_DIRECTION {in} \
|
|
CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_27_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_27_SLEW {fast} \
|
|
CONFIG.PCW_MIO_2_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_2_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_2_SLEW {slow} \
|
|
CONFIG.PCW_MIO_3_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_3_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_3_SLEW {slow} \
|
|
CONFIG.PCW_MIO_40_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_40_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_40_SLEW {slow} \
|
|
CONFIG.PCW_MIO_41_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_41_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_41_SLEW {slow} \
|
|
CONFIG.PCW_MIO_42_DIRECTION {in} \
|
|
CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_42_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_42_SLEW {slow} \
|
|
CONFIG.PCW_MIO_43_DIRECTION {out} \
|
|
CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_43_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_43_SLEW {slow} \
|
|
CONFIG.PCW_MIO_44_DIRECTION {out} \
|
|
CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_44_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_44_SLEW {slow} \
|
|
CONFIG.PCW_MIO_45_DIRECTION {in} \
|
|
CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_45_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_45_SLEW {slow} \
|
|
CONFIG.PCW_MIO_46_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_46_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_46_SLEW {slow} \
|
|
CONFIG.PCW_MIO_47_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_47_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_47_SLEW {slow} \
|
|
CONFIG.PCW_MIO_48_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_48_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_48_SLEW {slow} \
|
|
CONFIG.PCW_MIO_49_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_49_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_49_SLEW {slow} \
|
|
CONFIG.PCW_MIO_4_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_4_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_4_SLEW {slow} \
|
|
CONFIG.PCW_MIO_50_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_50_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_50_SLEW {slow} \
|
|
CONFIG.PCW_MIO_51_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_51_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_51_SLEW {slow} \
|
|
CONFIG.PCW_MIO_52_DIRECTION {out} \
|
|
CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_52_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_52_SLEW {fast} \
|
|
CONFIG.PCW_MIO_53_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_53_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_53_SLEW {fast} \
|
|
CONFIG.PCW_MIO_5_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_5_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_5_SLEW {slow} \
|
|
CONFIG.PCW_MIO_6_DIRECTION {out} \
|
|
CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_6_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_6_SLEW {slow} \
|
|
CONFIG.PCW_MIO_TREE_PERIPHERALS {unassigned#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#unassigned#Quad SPI Flash#Quad SPI Flash#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 0#UART 0#UART 1#UART 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#Enet 0#Enet 0} \
|
|
CONFIG.PCW_MIO_TREE_SIGNALS {unassigned#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#unassigned#qspi0_io[3]/HOLD_B#qspi0_sclk#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#rx#tx#tx#rx#data[0]#cmd#clk#data[1]#data[2]#data[3]#mdc#mdio} \
|
|
CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
|
|
CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
|
|
CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
|
|
CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
|
|
CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
|
|
CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
|
|
CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
|
|
CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
|
|
CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
|
|
CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
|
|
CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
|
|
CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {0} \
|
|
CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
|
|
CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
|
|
CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
|
|
CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
|
|
CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \
|
|
CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
|
|
CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
|
|
CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
|
|
CONFIG.PCW_SD0_GRP_CD_ENABLE {0} \
|
|
CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
|
|
CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
|
|
CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0} \
|
|
CONFIG.PCW_SD0_SD0_IO {<Select>} \
|
|
CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \
|
|
CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \
|
|
CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \
|
|
CONFIG.PCW_SD1_PERIPHERAL_ENABLE {1} \
|
|
CONFIG.PCW_SD1_SD1_IO {MIO 46 .. 51} \
|
|
CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {10} \
|
|
CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {100} \
|
|
CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
|
|
CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x2} \
|
|
CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
|
|
CONFIG.PCW_SPI0_GRP_SS0_ENABLE {1} \
|
|
CONFIG.PCW_SPI0_GRP_SS0_IO {EMIO} \
|
|
CONFIG.PCW_SPI0_GRP_SS1_ENABLE {1} \
|
|
CONFIG.PCW_SPI0_GRP_SS1_IO {EMIO} \
|
|
CONFIG.PCW_SPI0_GRP_SS2_ENABLE {1} \
|
|
CONFIG.PCW_SPI0_GRP_SS2_IO {EMIO} \
|
|
CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1} \
|
|
CONFIG.PCW_SPI0_SPI0_IO {EMIO} \
|
|
CONFIG.PCW_SPI1_GRP_SS0_ENABLE {1} \
|
|
CONFIG.PCW_SPI1_GRP_SS0_IO {EMIO} \
|
|
CONFIG.PCW_SPI1_GRP_SS1_ENABLE {1} \
|
|
CONFIG.PCW_SPI1_GRP_SS1_IO {EMIO} \
|
|
CONFIG.PCW_SPI1_GRP_SS2_ENABLE {1} \
|
|
CONFIG.PCW_SPI1_GRP_SS2_IO {EMIO} \
|
|
CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} \
|
|
CONFIG.PCW_SPI1_SPI1_IO {EMIO} \
|
|
CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {6} \
|
|
CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \
|
|
CONFIG.PCW_SPI_PERIPHERAL_VALID {1} \
|
|
CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
|
|
CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
|
|
CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
|
|
CONFIG.PCW_UART0_UART0_IO {MIO 42 .. 43} \
|
|
CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
|
|
CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
|
|
CONFIG.PCW_UART1_UART1_IO {MIO 44 .. 45} \
|
|
CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
|
|
CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
|
|
CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
|
|
CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {266.666687} \
|
|
CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
|
|
CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \
|
|
CONFIG.PCW_UIPARAM_DDR_CL {7} \
|
|
CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
|
|
CONFIG.PCW_UIPARAM_DDR_CWL {6} \
|
|
CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
|
|
CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
|
|
CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
|
|
CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {266.6666666} \
|
|
CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-15E} \
|
|
CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
|
|
CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
|
|
CONFIG.PCW_UIPARAM_DDR_T_FAW {45.0} \
|
|
CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {36.0} \
|
|
CONFIG.PCW_UIPARAM_DDR_T_RC {49.5} \
|
|
CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
|
|
CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
|
|
CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {1} \
|
|
CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \
|
|
CONFIG.PCW_USE_M_AXI_GP0 {1} \
|
|
CONFIG.PCW_USE_M_AXI_GP1 {0} \
|
|
CONFIG.PCW_USE_S_AXI_HP0 {0} \
|
|
] $processing_system7_0
|
|
|
|
# Create instance: rst_ps7_0_50M, and set properties
|
|
set rst_ps7_0_50M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_50M ]
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_ports REG_INF] [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA]
|
|
connect_bd_intf_net -intf_net axi_bram_ctrl_1_BRAM_PORTA [get_bd_intf_ports REG_INF1] [get_bd_intf_pins axi_bram_ctrl_1/BRAM_PORTA]
|
|
connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] [get_bd_intf_pins axi_smc/M00_AXI]
|
|
connect_bd_intf_net -intf_net axi_smc_M01_AXI [get_bd_intf_pins axi_bram_ctrl_1/S_AXI] [get_bd_intf_pins axi_smc/M01_AXI]
|
|
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
|
|
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
|
|
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins axi_smc/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0]
|
|
connect_bd_intf_net -intf_net processing_system7_0_SPI_0 [get_bd_intf_ports SPI0] [get_bd_intf_pins processing_system7_0/SPI_0]
|
|
connect_bd_intf_net -intf_net processing_system7_0_SPI_1 [get_bd_intf_ports SPI1] [get_bd_intf_pins processing_system7_0/SPI_1]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net GPIO_EMIO_gpio_i_1 [get_bd_ports GPIO_EMIO_gpio_i] [get_bd_pins processing_system7_0/GPIO_I]
|
|
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FCLK_CLK0] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_bram_ctrl_1/s_axi_aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins rst_ps7_0_50M/slowest_sync_clk]
|
|
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_ports FCLK_RESET0_N] [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_50M/ext_reset_in]
|
|
connect_bd_net -net processing_system7_0_GPIO_O [get_bd_ports GPIO_EMIO_gpio_o] [get_bd_pins processing_system7_0/GPIO_O]
|
|
connect_bd_net -net processing_system7_0_GPIO_T [get_bd_ports GPIO_EMIO_gpio_t] [get_bd_pins processing_system7_0/GPIO_T]
|
|
connect_bd_net -net rst_ps7_0_50M_peripheral_aresetn [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_bram_ctrl_1/s_axi_aresetn] [get_bd_pins axi_smc/aresetn] [get_bd_pins rst_ps7_0_50M/peripheral_aresetn]
|
|
|
|
# Create address segments
|
|
create_bd_addr_seg -range 0x00010000 -offset 0x40000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] SEG_axi_bram_ctrl_0_Mem0
|
|
create_bd_addr_seg -range 0x00002000 -offset 0x42000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_bram_ctrl_1/S_AXI/Mem0] SEG_axi_bram_ctrl_1_Mem0
|
|
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
|
|
save_bd_design
|
|
}
|
|
# End of create_root_design()
|
|
|
|
|
|
##################################################################
|
|
# MAIN FLOW
|
|
##################################################################
|
|
|
|
create_root_design ""
|
|
|
|
|