bowei
ea4541ee90
- simulink_rtl_dev / rtl-ip-replace: 从工程级 .claude/skills 迁到用户级并去工程耦合 (模型名/Notes 文档依赖/工程实测基线移出; addpath 与脚本路径改用户级) - rtl-ip-replace/scripts/gen_cmp_tb.py: Vivado 路径不再写死, 改读 VIVADO_PATH / XILINX_VIVADO (兼容 install root / bin / bin\vivado.bat 三种写法), 回落时提示 去设 skills_env.md 的 VIVADO_PATH - simulink-rtl-redev: 新增。原生模型改动后的仿真模型同步规范, 含两个实测过的工具 check_sync.py (三条时序链新鲜度闸门) 与 measure_k.m (时域/频域/包络三估计器互证) - sim-rtl-flow/SKILL.md: 加入 sync_sim:* 步骤, 引用上述三个 skill
39 lines
1.5 KiB
Python
39 lines
1.5 KiB
Python
#!/usr/bin/env python3
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"""Suffix every module in rtl_ip/ with _IP so original and IP-based RTL can
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coexist in one xsim `work` library for the dual-DUT cycle-true comparison.
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- renames `module X` -> `module X_IP` for every module DECLARED in rtl_ip/*.v
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- rewrites instantiations of those modules accordingly (word-boundary match)
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- IP core instances (dist_mem_gen/blk_mem_gen/... names from ip_manifest) are
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left untouched -- they are not declared here.
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Run LAST, after rom_to_ip.py / ram_to_ip.py / any hand edits (CORDIC, FIFO).
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Idempotent: modules already ending in _IP are skipped.
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"""
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import argparse, os, re
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def main():
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ap = argparse.ArgumentParser()
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ap.add_argument('rtl_ip_dir')
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a = ap.parse_args()
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d = os.path.abspath(a.rtl_ip_dir)
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files = [os.path.join(d, f) for f in os.listdir(d) if f.endswith('.v')]
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mods = []
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for p in files:
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for m in re.finditer(r'^\s*module\s+(\w+)', open(p, encoding='utf-8', errors='replace').read(), re.M):
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if not m.group(1).endswith('_IP'):
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mods.append(m.group(1))
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mods = sorted(set(mods), key=len, reverse=True)
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print('modules:', mods)
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for p in files:
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txt = open(p, encoding='utf-8', errors='replace').read()
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for mod in mods:
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txt = re.sub(r'\b%s\b(?!_IP)' % re.escape(mod), mod + '_IP', txt)
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open(p, 'w', encoding='utf-8').write(txt)
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print(f'suffixed {len(mods)} modules across {len(files)} files')
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if __name__ == '__main__':
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main()
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