bowei a36cbfda2a stabilize hjx9009 qspi cache profile

2026-09-15 03:23:25 +08:00

.system/plugin-creator

更新了部分skill

2026-06-22 16:40:24 +08:00

altium-kicad

sync: HP_BOWEI 2026-09-09

2026-09-09 09:51:06 +08:00

bmem

tools-sync: 增加 ls-remote 同步闸门，并记下 gitea 空 pack 故障的排查法

2026-09-02 14:57:50 -05:00

dpd-mig-flow

sync: BOWEI 2026-08-29 新增 dpd-mig-flow / sim-rtl-flow 两个 skill，去硬编码

2026-09-07 16:17:45 +08:00

fft-analyse

Portabilize hardcoded C:\Users\bowei paths across skill docs

2026-07-20 20:35:43 +08:00

fpga_flash

sync: WIN-BOWEI 2026-08-10 fpga_flash 增 Zynq BOOT.bin/QSPI 脚本，rtl-ip-replace 与 sim-rtl-flow 更新

2026-08-19 12:50:44 +08:00

fpga_update

sync: Shanghai-U9 2026-09-03 硬编码审计清掉 0819/0826 挂了两轮的文档类遗留

2026-09-03 02:52:05 +08:00

fpga-goldenref-flow

sync: BOWEI 2026-08-29 新增 dpd-mig-flow / sim-rtl-flow 两个 skill，去硬编码

2026-09-07 16:17:45 +08:00

fpga-imx6-flow

sync: WIN11-BOWEI 2026-09-02 新增 bmem 记忆 skill；imx6-flow/plan-review 文档与脚本更新

2026-09-02 14:53:28 -05:00

langgraph-plan-review

sync: HP_BOWEI 2026-09-09

2026-09-09 09:51:06 +08:00

langgraph-vivado-install

Portabilize hardcoded C:\Users\bowei paths across skill docs

2026-07-20 20:35:43 +08:00

petalinux-qspi

stabilize hjx9009 qspi cache profile

2026-09-15 03:23:25 +08:00

rtl-ip-replace

sync: WIN-BOWEI 2026-08-10 fpga_flash 增 Zynq BOOT.bin/QSPI 脚本，rtl-ip-replace 与 sim-rtl-flow 更新

2026-08-19 12:50:44 +08:00

sim-rtl-flow

sync: BOWEI 2026-08-29 新增 dpd-mig-flow / sim-rtl-flow 两个 skill，去硬编码

2026-09-07 16:17:45 +08:00

simulink_rtl_dev

sync: SHANGHAI-U9 2026-07-27 三个 Simulink→RTL skill 转系统级 + 新增 simulink-rtl-redev

2026-07-27 10:39:53 +08:00

simulink-rtl-redev

sync: SHANGHAI-U9 2026-07-27 三个 Simulink→RTL skill 转系统级 + 新增 simulink-rtl-redev

2026-07-27 10:39:53 +08:00

smod_atsc_dev

sync: Shanghai-U9 2026-09-03 硬编码审计清掉 0819/0826 挂了两轮的文档类遗留

2026-09-03 02:52:05 +08:00

tools-sync

tools-sync: 订正 Codex MCP 消失的归因——与升级无关，且需放在同步最后一步

2026-09-08 05:41:19 +08:00

vivado-prj-create

vivado: resolve install path from ~/skills_env.md instead of hardcoding D:\Xilinx

2026-07-20 07:48:04 -05:00

vivado-sim

sync: HP_BOWEI 2026-07-27 vivado-sim 去掉写死的 Vivado 盘符路径

2026-07-27 13:56:51 +08:00

zynq-imx6-flow

zynq-imx6-flow: analyze 阶段增加频谱仪取证要求

2026-09-02 14:54:09 -05:00

.gitattributes

Initial commit

2026-05-09 01:12:34 -05:00

.gitignore

sync: BOWEI 2026-09-07 tools-sync 改为 junction 模型（registry 双向 ingest + 修复）

2026-09-07 16:22:09 +08:00

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