bowei
ea4541ee90
- simulink_rtl_dev / rtl-ip-replace: 从工程级 .claude/skills 迁到用户级并去工程耦合 (模型名/Notes 文档依赖/工程实测基线移出; addpath 与脚本路径改用户级) - rtl-ip-replace/scripts/gen_cmp_tb.py: Vivado 路径不再写死, 改读 VIVADO_PATH / XILINX_VIVADO (兼容 install root / bin / bin\vivado.bat 三种写法), 回落时提示 去设 skills_env.md 的 VIVADO_PATH - simulink-rtl-redev: 新增。原生模型改动后的仿真模型同步规范, 含两个实测过的工具 check_sync.py (三条时序链新鲜度闸门) 与 measure_k.m (时域/频域/包络三估计器互证) - sim-rtl-flow/SKILL.md: 加入 sync_sim:* 步骤, 引用上述三个 skill
106 lines
4.0 KiB
Python
106 lines
4.0 KiB
Python
#!/usr/bin/env python3
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"""Replace SimpleDualPortRAM_generic (HDL Coder) with blk_mem_gen SDP instances.
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Semantics of the original (must be preserved exactly):
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- single clock, `enb` gates BOTH write and read registration
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- read latency 1 cycle; write/read same address -> read returns OLD data (read-first)
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=> blk_mem_gen: Simple Dual Port, common clock, Port-A write mode READ_FIRST,
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ENA/ENB pins used, NO output register.
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The wrapper keeps the module name/ports/params; a generate-if selects the
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per-(AddrWidth,DataWidth) IP; unlisted combos fall back to the original
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behavioral body (so simulation still works, and synthesis of an unlisted combo
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is loudly visible in the utilization report instead of silently wrong).
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Run AFTER rom_to_ip.py (needs rtl_ip/ copies), BEFORE namespace_ip.py.
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"""
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import argparse, json, os, re
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WRAP = '''// regenerated by ram_to_ip.py -- blk_mem_gen SDP wrappers (read-first, 1-cycle, common clk)
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`timescale 1 ns / 1 ns
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module {mod}
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(clk, enb, wr_din, wr_addr, wr_en, rd_addr, dout);
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parameter integer AddrWidth = 1;
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parameter integer DataWidth = 1;
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input clk;
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input enb;
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input signed [DataWidth - 1:0] wr_din;
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input [AddrWidth - 1:0] wr_addr;
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input wr_en;
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input [AddrWidth - 1:0] rd_addr;
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output signed [DataWidth - 1:0] dout;
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generate
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{cases} begin: g_behav // fallback: original behavioral RAM (unlisted param combo)
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reg [DataWidth - 1:0] ram [2**AddrWidth - 1:0];
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reg [DataWidth - 1:0] data_int;
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integer i;
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initial begin
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for (i=0; i<=2**AddrWidth - 1; i=i+1) ram[i] = 0;
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data_int = 0;
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end
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always @(posedge clk)
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if (enb == 1'b1) begin
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if (wr_en == 1'b1) ram[wr_addr] <= wr_din;
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data_int <= ram[rd_addr];
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end
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assign dout = data_int;
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end
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endgenerate
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endmodule
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'''
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CASE = ''' if (AddrWidth == {aw} && DataWidth == {dw}) begin: g_a{aw}d{dw}
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wire [{dwm}:0] doutb_i;
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{ip} u_bram (
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.clka(clk), .ena(enb), .wea(wr_en), .addra(wr_addr), .dina(wr_din),
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.clkb(clk), .enb(enb), .addrb(rd_addr), .doutb(doutb_i));
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assign dout = doutb_i;
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end else
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'''
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def main():
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ap = argparse.ArgumentParser()
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ap.add_argument('hdlsrc')
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ap.add_argument('outdir', help='FIXED output dir (e.g. <repo>/vivado/rtl_ip/<model>)')
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ap.add_argument('--manifest', default=None)
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a = ap.parse_args()
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hdlsrc = os.path.abspath(a.hdlsrc)
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rtl_ip = os.path.abspath(a.outdir)
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man = json.load(open(a.manifest or os.path.join(rtl_ip, 'manifest.json')))
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combos = sorted({(r['AddrWidth'], r['DataWidth']) for r in man['ram']
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if r['AddrWidth'] and r['DataWidth']})
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if not combos:
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print('no SimpleDualPortRAM instantiations found'); return
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ipman_p = os.path.join(rtl_ip, 'ip_manifest.json')
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ipman = json.load(open(ipman_p)) if os.path.exists(ipman_p) else {'ips': []}
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have = {ip['name'] for ip in ipman['ips']}
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cases = ''
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for aw, dw in combos:
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ip = f'bram_sdp_a{aw}d{dw}'
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cases += CASE.format(aw=aw, dw=dw, dwm=dw - 1, ip=ip)
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if ip not in have:
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ipman['ips'].append({'type': 'blk_mem_gen', 'name': ip, 'width': dw,
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'depth': 2 ** aw, 'mode': 'sdp_readfirst_commonclk'})
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# rewrite every SimpleDualPortRAM_*.v module file present in rtl_ip
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n = 0
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for fn in os.listdir(rtl_ip):
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if re.match(r'SimpleDualPortRAM_\w+\.v$', fn):
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mod = fn[:-2]
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open(os.path.join(rtl_ip, fn), 'w').write(WRAP.format(mod=mod, cases=cases))
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print('wrapped', mod, 'combos:', combos)
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n += 1
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json.dump(ipman, open(ipman_p, 'w'), indent=1)
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with open(os.path.join(rtl_ip, 'ip_manifest.tcl'), 'w') as f:
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for ip in ipman['ips']:
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f.write('lappend ips {%s}\n' % ' '.join(f'{k} {{{v}}}' for k, v in ip.items()))
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print(f'done: {n} RAM module(s) wrapped, {len(combos)} blk_mem_gen config(s)')
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if __name__ == '__main__':
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main()
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