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重构：优化 DPD 的 FAGC 与 DAGC 时序

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rfeng
2026-08-28 13:28:14 +08:00
parent 8243380474
commit eebdd22256
2 changed files with 3423 additions and 3412 deletions
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src/atsc_app/bsp/dpd_proc.c
+11 -8
View File
@@ -106,7 +106,7 @@ void reset_dpd_to_normal_state(void)
//printf("reset_dpd_to_normal_state\n"); //printf("reset_dpd_to_normal_state\n");
u_dpdctl_r23.u8val = 0; u_dpdctl_r23.u8val = 0;
u_dpdctl_r23.dpd_bt.iqb_upd = 0; u_dpdctl_r23.dpd_bt.iqb_upd = 0;
u_dpdctl_r23.dpd_bt.rf_sel = 0; //A u_dpdctl_r23.dpd_bt.rf_sel = DPD_RF_SEL_VALUE(E_SELECT_A);
u_dpdctl_r23.dpd_bt.sync_mode = 1; u_dpdctl_r23.dpd_bt.sync_mode = 1;
fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val);
log_printf(LOG_DEBUG, I_USER_CFG, "reset set seg5-23 IQBval=0x%x\n",u_dpdctl_r23.u8val); log_printf(LOG_DEBUG, I_USER_CFG, "reset set seg5-23 IQBval=0x%x\n",u_dpdctl_r23.u8val);
@@ -1185,6 +1185,7 @@ void dpd_exit(void)// 关闭dpd
fpga_byte_write(5,FPGA_ADDR_DPD_CTRL1, DPD_CTRL1_ALL_BYPS|DPD_CTRL1_DPD_ALLCLR); fpga_byte_write(5,FPGA_ADDR_DPD_CTRL1, DPD_CTRL1_ALL_BYPS|DPD_CTRL1_DPD_ALLCLR);
fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, 0); fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, 0);
u_dpdctl_r23.u8val=0; u_dpdctl_r23.u8val=0;
u_dpdctl_r23.dpd_bt.rf_sel = DPD_RF_SEL_VALUE(E_SELECT_A);
fpga_byte_write(5,FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); fpga_byte_write(5,FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val);
reset_dpd_to_normal_state(); reset_dpd_to_normal_state();
@@ -1264,7 +1265,7 @@ int boot_tsnr_update(uint8 rst_flg)
u_dpdctl_r23.u8val = 0; u_dpdctl_r23.u8val = 0;
u_dpdctl_r23.dpd_bt.iqb_upd = 0; u_dpdctl_r23.dpd_bt.iqb_upd = 0;
u_dpdctl_r23.dpd_bt.sync_mode = 1; u_dpdctl_r23.dpd_bt.sync_mode = 1;
u_dpdctl_r23.dpd_bt.rf_sel = 0; u_dpdctl_r23.dpd_bt.rf_sel = DPD_RF_SEL_VALUE(E_SELECT_A);
log_printf(LOG_DEBUG,I_NOUSED,"[state] phase 7 ---------------A- 0x%x\n", u_dpdctl_r23.u8val); log_printf(LOG_DEBUG,I_NOUSED,"[state] phase 7 ---------------A- 0x%x\n", u_dpdctl_r23.u8val);
fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val);
@@ -1338,7 +1339,7 @@ int boot_tsnr_update(uint8 rst_flg)
u_dpdctl_r23.dpd_bt.iqb_upd = 1; u_dpdctl_r23.dpd_bt.iqb_upd = 1;
u_dpdctl_r23.dpd_bt.sync_mode = 1; u_dpdctl_r23.dpd_bt.sync_mode = 1;
u_dpdctl_r23.dpd_bt.rf_sel = 0;// A u_dpdctl_r23.dpd_bt.rf_sel = DPD_RF_SEL_VALUE(E_SELECT_A);
log_printf(LOG_DEBUG,I_NOUSED,"[state] phase 9 ---------------A- 0x%x\n", u_dpdctl_r23.u8val); log_printf(LOG_DEBUG,I_NOUSED,"[state] phase 9 ---------------A- 0x%x\n", u_dpdctl_r23.u8val);
fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val);
} }
@@ -1428,7 +1429,7 @@ int update_tsnr_uimd_limd(uint8 rst_flg, uint8 *p_phase)
u_dpdctl_r23.u8val=0; u_dpdctl_r23.u8val=0;
u_dpdctl_r23.dpd_bt.iqb_upd = 0; u_dpdctl_r23.dpd_bt.iqb_upd = 0;
u_dpdctl_r23.dpd_bt.sync_mode = 1; u_dpdctl_r23.dpd_bt.sync_mode = 1;
u_dpdctl_r23.dpd_bt.rf_sel = 0; u_dpdctl_r23.dpd_bt.rf_sel = DPD_RF_SEL_VALUE(E_SELECT_A);
fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val);
log_printf(LOG_DEBUG, I_USER_CFG, "[state] phase 7 in---------------A- 0x%x\n", u_dpdctl_r23.u8val); log_printf(LOG_DEBUG, I_USER_CFG, "[state] phase 7 in---------------A- 0x%x\n", u_dpdctl_r23.u8val);
@@ -1502,7 +1503,7 @@ int update_tsnr_uimd_limd(uint8 rst_flg, uint8 *p_phase)
u_dpdctl_r23.dpd_bt.iqb_upd = 1; u_dpdctl_r23.dpd_bt.iqb_upd = 1;
u_dpdctl_r23.dpd_bt.sync_mode = 1; u_dpdctl_r23.dpd_bt.sync_mode = 1;
u_dpdctl_r23.dpd_bt.rf_sel = 0;// A u_dpdctl_r23.dpd_bt.rf_sel = DPD_RF_SEL_VALUE(E_SELECT_A);
fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val);
log_printf(LOG_DEBUG, I_USER_CFG, "[state] phase 9 in---------------A- 0x%x\n", u_dpdctl_r23.u8val); log_printf(LOG_DEBUG, I_USER_CFG, "[state] phase 9 in---------------A- 0x%x\n", u_dpdctl_r23.u8val);
} }
@@ -1788,7 +1789,7 @@ uint8 conv_adpc_err_output(uint8 raw_dpd_err)
void set_ab_switch(E_AB_SEL ab_val) void set_ab_switch(E_AB_SEL ab_val)
{ {
u_dpdctl_r23.dpd_bt.rf_sel = ab_val; // 1 : B , 0 : A u_dpdctl_r23.dpd_bt.rf_sel = DPD_RF_SEL_VALUE(ab_val);
fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val);
} }
@@ -2105,7 +2106,7 @@ void refresh_update_dpd(void *parg,void *parv)
u_dpdctl_r23.u8val = 0; u_dpdctl_r23.u8val = 0;
u_dpdctl_r23.dpd_bt.iqb_upd = 1; u_dpdctl_r23.dpd_bt.iqb_upd = 1;
u_dpdctl_r23.dpd_bt.sync_mode = 0; u_dpdctl_r23.dpd_bt.sync_mode = 0;
u_dpdctl_r23.dpd_bt.rf_sel = 1; u_dpdctl_r23.dpd_bt.rf_sel = DPD_RF_SEL_VALUE(E_SELECT_B);
fpga_byte_write(5,FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); fpga_byte_write(5,FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val);
log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 1: 0x%x\n", u_dpdctl_r23.u8val); log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 1: 0x%x\n", u_dpdctl_r23.u8val);
@@ -2640,7 +2641,7 @@ void refresh_update_dpd(void *parg,void *parv)
u_dpdctl_r23.dpd_bt.iqb_upd =0; u_dpdctl_r23.dpd_bt.iqb_upd =0;
u_dpdctl_r23.dpd_bt.sync_mode=1; u_dpdctl_r23.dpd_bt.sync_mode=1;
u_dpdctl_r23.dpd_bt.rf_sel =0; u_dpdctl_r23.dpd_bt.rf_sel = DPD_RF_SEL_VALUE(E_SELECT_A);
fpga_byte_write(5,FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); fpga_byte_write(5,FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val);
log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 7: 0x%x\n", u_dpdctl_r23.u8val); log_printf(LOG_DEBUG, I_USER_CFG, "[update] phase 7: 0x%x\n", u_dpdctl_r23.u8val);
@@ -2862,6 +2863,7 @@ DPD_SAVE_PROC:
fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, 0); fpga_byte_write(0x05, FPGA_ADDR_DPD_CTRL3, 0);
u_dpdctl_r23.u8val = 0; u_dpdctl_r23.u8val = 0;
u_dpdctl_r23.dpd_bt.rf_sel = DPD_RF_SEL_VALUE(E_SELECT_A);
fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); fpga_byte_write(0x05, FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val);
log_printf(LOG_DEBUG, I_USER_CFG, "[update] save data --- 0x%x\n", u_dpdctl_r23.u8val); log_printf(LOG_DEBUG, I_USER_CFG, "[update] save data --- 0x%x\n", u_dpdctl_r23.u8val);
@@ -2928,6 +2930,7 @@ DPD_SAVE_PROC:
fpga_byte_write(5,FPGA_ADDR_DPD_CTRL1, 0); fpga_byte_write(5,FPGA_ADDR_DPD_CTRL1, 0);
fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, 0); fpga_byte_write(5,FPGA_ADDR_DPD_CTRL3, 0);
u_dpdctl_r23.u8val = 0; u_dpdctl_r23.u8val = 0;
u_dpdctl_r23.dpd_bt.rf_sel = DPD_RF_SEL_VALUE(E_SELECT_A);
fpga_byte_write(5,FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val); fpga_byte_write(5,FPGA_ADDR_DPD_IQB_UPD, u_dpdctl_r23.u8val);
log_printf(LOG_DEBUG, I_USER_CFG, "[update] success --- u_dpdctl_r23=0x%x\n", u_dpdctl_r23.u8val); log_printf(LOG_DEBUG, I_USER_CFG, "[update] success --- u_dpdctl_r23=0x%x\n", u_dpdctl_r23.u8val);
src/atsc_app/inc/dpd_proc.h
+9 -1
View File
@@ -93,7 +93,15 @@ enum{
//#define DPD_IQB_SYNC_MASK (0x0001<<2) //#define DPD_IQB_SYNC_MASK (0x0001<<2)
#define DPD_SYNC_MODE_MASK (0x0001<<2) #define DPD_SYNC_MODE_MASK (0x0001<<2)
#define DPD_RF_SEL_BEFORE (0x0001<<3) /*
* Hardware order is exchanged again: logical/silkscreen A -> rf_sel 0,
* logical/silkscreen B -> rf_sel 1. Keep every RF input selection routed
* through this mapping so DPD/FWD/FSSI use the same A/B interpretation.
*/
#define DPD_RF_SEL_HW_A 0U
#define DPD_RF_SEL_HW_B 1U
#define DPD_RF_SEL_VALUE(sel) (((sel) == E_SELECT_B) ? DPD_RF_SEL_HW_B : DPD_RF_SEL_HW_A)
#define DPD_RF_SEL_AFTER (0x0001<<3)
#define DPD_SET_100M (0x00) #define DPD_SET_100M (0x00)
#define DPD_SET_25M (0x01) #define DPD_SET_25M (0x01)