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重构：优化 DPD 的 FAGC 与 DAGC 时序

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rfeng
2026-08-28 13:28:14 +08:00
parent 8243380474
commit eebdd22256
2 changed files with 3423 additions and 3412 deletions
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src/atsc_app/bsp/dpd_proc.c
+3173 -3170
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src/atsc_app/inc/dpd_proc.h
+250 -242
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@@ -1,242 +1,250 @@
#ifndef _DPD_PROC_H_ #ifndef _DPD_PROC_H_
#define _DPD_PROC_H_ #define _DPD_PROC_H_
#include "type.h" #include "type.h"
#define DPD_LOG_ENABLE 1 #define DPD_LOG_ENABLE 1
#define DPD_LOG_FILE "/aw/anywave/dpd_log/log" #define DPD_LOG_FILE "/aw/anywave/dpd_log/log"
#define FPGA_ADDR_DPD_LOG_TRIG 0x15 #define FPGA_ADDR_DPD_LOG_TRIG 0x15
//----Write Only-------------- //----Write Only--------------
//ok //ok
#define FPGA_ADDR_DPD_CTRL1 0x20 #define FPGA_ADDR_DPD_CTRL1 0x20
#define FPGA_ADDR_DPD_CTRL2 0x21 #define FPGA_ADDR_DPD_CTRL2 0x21
#define FPGA_ADDR_DPD_CTRL3 0x22 #define FPGA_ADDR_DPD_CTRL3 0x22
//ok //ok
#define FPGA_ADDR_DPD_IQB_UPD 0x23 #define FPGA_ADDR_DPD_IQB_UPD 0x23
#define FPGA_ADDR_DPD_CFG_STEP 0x24 #define FPGA_ADDR_DPD_CFG_STEP 0x24
//wpp //wpp
#define FPGA_ADDR_WPP_EN_CLR 0x0d #define FPGA_ADDR_WPP_EN_CLR 0x0d
#define FPGA_ADDR_WPP_TH_L 0x0e #define FPGA_ADDR_WPP_TH_L 0x0e
#define FPGA_ADDR_WPP_TH_H 0x0f #define FPGA_ADDR_WPP_TH_H 0x0f
#define MASK_WPP_ENABLE (1) #define MASK_WPP_ENABLE (1)
#define MASK_WPP_CLR (1<<1) #define MASK_WPP_CLR (1<<1)
//#define FPGA_ADDR_DPD_SYNCOFFSET ?? //#define FPGA_ADDR_DPD_SYNCOFFSET ??
#define FPGA_ADDR_DPD_TEST_L 0x02 #define FPGA_ADDR_DPD_TEST_L 0x02
#define FPGA_ADDR_DPD_TEST_H 0x03 #define FPGA_ADDR_DPD_TEST_H 0x03
//----Read Only-------------- //----Read Only--------------
#define FPGA_ADDR_DPD_STATUS1 0x01 #define FPGA_ADDR_DPD_STATUS1 0x01
//--------------------------- //---------------------------
#define MASK_RFAGC_DOWN_LIMIT (1<<1) #define MASK_RFAGC_DOWN_LIMIT (1<<1)
#define MASK_RFAGC_UP_LIMIT (1<<2) #define MASK_RFAGC_UP_LIMIT (1<<2)
#define SPI_BLK_LEN 35//Byte #define SPI_BLK_LEN 35//Byte
enum{ enum{
E_RFAGC_NORMAL=0, E_RFAGC_NORMAL=0,
E_RFAGC_DOWN_LIMIT, E_RFAGC_DOWN_LIMIT,
E_RFAGC_UP_LIMIT, E_RFAGC_UP_LIMIT,
}E_AGC_ERR_CODE; }E_AGC_ERR_CODE;
/* /*
E_RFAGC_POWER_LOW, E_RFAGC_POWER_LOW,
E_RFAGC_POWER_HIGH, E_RFAGC_POWER_HIGH,
*/ */
//ok //ok
#define MASK_DPD_ERR (0x0001) #define MASK_DPD_ERR (0x0001)
#define MASK_DPD_PWRHIGH (0x0001<<1) #define MASK_DPD_PWRHIGH (0x0001<<1)
#define MASK_DPD_PWRLOW (0x0001<<2) #define MASK_DPD_PWRLOW (0x0001<<2)
#define MASK_DPD_DAGC_TOOHIGH (0x0001<<3) #define MASK_DPD_DAGC_TOOHIGH (0x0001<<3)
#define MASK_DPD_DAGC_TOOLOW (0x0001<<4) #define MASK_DPD_DAGC_TOOLOW (0x0001<<4)
#define MASK_DPD_ERR_ABORT (0x0001<<5) #define MASK_DPD_ERR_ABORT (0x0001<<5)
#define MASK_DPD_TRX_SYNC_OK (0x0001<<6) #define MASK_DPD_TRX_SYNC_OK (0x0001<<6)
#define MASK_DPD_SAT_FLG (0x0001<<7) #define MASK_DPD_SAT_FLG (0x0001<<7)
//ok //ok
#define DPD_CTRL1_DPD_START (0x0001) #define DPD_CTRL1_DPD_START (0x0001)
#define DPD_CTRL1_DPD_ALLCLR (0x0001<<1) #define DPD_CTRL1_DPD_ALLCLR (0x0001<<1)
#define DPD_CTRL1_ALL_BYPS (0x0001<<2) #define DPD_CTRL1_ALL_BYPS (0x0001<<2)
#define DPD_CTRL2_LIN_UPDATE (0x0001) #define DPD_CTRL2_LIN_UPDATE (0x0001)
#define DPD_CTRL2_NONLIN_UPDATE (0x0001<<1) #define DPD_CTRL2_NONLIN_UPDATE (0x0001<<1)
#define DPD_CTRL2_SET_NONLIN_UDP_MOD(x) (((x)&0x03)<<2) /*01 : POLY; 10: CRST*/ #define DPD_CTRL2_SET_NONLIN_UDP_MOD(x) (((x)&0x03)<<2) /*01 : POLY; 10: CRST*/
#define DPD_CTRL2_AMP_CHK (0x0001<<4) #define DPD_CTRL2_AMP_CHK (0x0001<<4)
#define DPD_CTRL2_PRL_UPDATE (0x0001<<5) #define DPD_CTRL2_PRL_UPDATE (0x0001<<5)
#define DPD_CTRL2_RXEQ_UPDATE (0x0001<<6) #define DPD_CTRL2_RXEQ_UPDATE (0x0001<<6)
#define DPD_CTRL2_POLYESTI_UPDATE (0x0001<<7) #define DPD_CTRL2_POLYESTI_UPDATE (0x0001<<7)
//ok //ok
#define INTER_DISTORTION_SW_MAX (7) #define INTER_DISTORTION_SW_MAX (7)
//ok //ok
#define DPD_CTRL3_FAGC_UPDATE (0x0001) #define DPD_CTRL3_FAGC_UPDATE (0x0001)
#define DPD_CTRL3_FAGC_SLOWDN (0x0001<<1) #define DPD_CTRL3_FAGC_SLOWDN (0x0001<<1)
#define DPD_CTRL3_DAGC_UPDATE (0x0001<<2) #define DPD_CTRL3_DAGC_UPDATE (0x0001<<2)
#define DPD_CTRL3_DAGC_SLOWDN (0x0001<<3) #define DPD_CTRL3_DAGC_SLOWDN (0x0001<<3)
#define DPD_CTRL3_DCRM_UPDATE (0x0001<<4) #define DPD_CTRL3_DCRM_UPDATE (0x0001<<4)
#define DPD_CTRL3_ROT_UPDATE (0x0001<<5) #define DPD_CTRL3_ROT_UPDATE (0x0001<<5)
#define DPD_CTRL3_SYNC_UPDATE (0x0001<<6) #define DPD_CTRL3_SYNC_UPDATE (0x0001<<6)
#define DPD_CTRL3_SYNC_RESTART (0x0001<<7) #define DPD_CTRL3_SYNC_RESTART (0x0001<<7)
//ok //ok
#define DPD_IQB_UPDATE (0x0001) #define DPD_IQB_UPDATE (0x0001)
#define DPD_IQB_BP_MASK (0x0001<<1) #define DPD_IQB_BP_MASK (0x0001<<1)
//#define DPD_IQB_SYNC_MASK (0x0001<<2) //#define DPD_IQB_SYNC_MASK (0x0001<<2)
#define DPD_SYNC_MODE_MASK (0x0001<<2) #define DPD_SYNC_MODE_MASK (0x0001<<2)
#define DPD_RF_SEL_BEFORE (0x0001<<3) /*
* Hardware order is exchanged again: logical/silkscreen A -> rf_sel 0,
#define DPD_SET_100M (0x00) * logical/silkscreen B -> rf_sel 1. Keep every RF input selection routed
#define DPD_SET_25M (0x01) * through this mapping so DPD/FWD/FSSI use the same A/B interpretation.
*/
#define SET_DPDFAGC_REFPWR(x) ((x)) #define DPD_RF_SEL_HW_A 0U
#define DPD_SET_CRST_ADDR_STRUCT_2 ((0x01)<<17) #define DPD_RF_SEL_HW_B 1U
#define DPD_SET_ERR_TH(x) (((x)&0xffff)) #define DPD_RF_SEL_VALUE(sel) (((sel) == E_SELECT_B) ? DPD_RF_SEL_HW_B : DPD_RF_SEL_HW_A)
#define DPD_SET_ERR_CNT_TH(x) (((x)&0xff)<<16) #define DPD_RF_SEL_AFTER (0x0001<<3)
#define DPD_SET_DGAIN(x) (((x)&0xffff)<<2)
#define DPD_SET_FIX_DLY(x) (0x8000 & ((x)&0x7ff)) #define DPD_SET_100M (0x00)
#define DPD_SET_CRST_REFAD(x) ((x)[0] | ((x)[1]<<4) | ((x)[2]<<8) | ((x)[3]<<12) | ((x)[4]<<16) | ((x)[5]<<20)) #define DPD_SET_25M (0x01)
#define DPD_MAX_TX_AMP_SAT 65535 #define SET_DPDFAGC_REFPWR(x) ((x))
//#define TX_FREQ_IN_HZ 2550000000 #define DPD_SET_CRST_ADDR_STRUCT_2 ((0x01)<<17)
#define DPD_SET_ERR_TH(x) (((x)&0xffff))
#define DPD_SET_ERR_CNT_TH(x) (((x)&0xff)<<16)
#define DPD_SEG 5 #define DPD_SET_DGAIN(x) (((x)&0xffff)<<2)
#define DPD_SET_FIX_DLY(x) (0x8000 & ((x)&0x7ff))
#define MASK_DPD_DATA_AREA0_MODE ((1)&0xff) #define DPD_SET_CRST_REFAD(x) ((x)[0] | ((x)[1]<<4) | ((x)[2]<<8) | ((x)[3]<<12) | ((x)[4]<<16) | ((x)[5]<<20))
#define MASK_DPD_DATA_AREA1_MODE ((1<<1)&0xff)
#define MASK_DPD_DATA_AREA2_MODE ((1<<2)&0xff) #define DPD_MAX_TX_AMP_SAT 65535
#define MASK_DPD_DATA_AREA3_MODE ((1<<3)&0xff) //#define TX_FREQ_IN_HZ 2550000000
//#define MASK_TO_FPGA_WRITE_ENABLE ((1))
#define MASK_TO_SPI_WR_RD_ENABLE (1) #define DPD_SEG 5
#define MASK_TO_FPGA_REFRESH_DATA (1<<1)
#define MASK_TO_FPGA_CHECK_CLEAR (1<<2) #define MASK_DPD_DATA_AREA0_MODE ((1)&0xff)
#define MASK_DPD_DATA_AREA1_MODE ((1<<1)&0xff)
enum{E_CHECK_FOR_RAED=0, E_CHECK_FOR_WIRTE=1}; #define MASK_DPD_DATA_AREA2_MODE ((1<<2)&0xff)
#define MASK_DPD_DATA_AREA3_MODE ((1<<3)&0xff)
typedef struct{
u32 area_fpga_w_check; //#define MASK_TO_FPGA_WRITE_ENABLE ((1))
u32 area_fpga_r_check; #define MASK_TO_SPI_WR_RD_ENABLE (1)
u32 area_imx_w_check; #define MASK_TO_FPGA_REFRESH_DATA (1<<1)
u32 area_imx_r_check; #define MASK_TO_FPGA_CHECK_CLEAR (1<<2)
}S_CHECK_SUM;
enum{E_CHECK_FOR_RAED=0, E_CHECK_FOR_WIRTE=1};
//--------------------------------------------
typedef struct{
/*Add Bit Ctrl*/ u32 area_fpga_w_check;
typedef struct{ u32 area_fpga_r_check;
uint8 iqb_upd:1; u32 area_imx_w_check;
uint8 iqb_bp:1; u32 area_imx_r_check;
uint8 sync_mode:1; /* !! sync_mode 与 re_sel 相反 */ }S_CHECK_SUM;
uint8 rf_sel:1; /* !! sync_mode 与 re_sel 相反 */
}S_DPD_REG23; //--------------------------------------------
typedef union /*Add Bit Ctrl*/
{ typedef struct{
S_DPD_REG23 dpd_bt; uint8 iqb_upd:1;
uint8 u8val; uint8 iqb_bp:1;
}U_DPDCTL_REG23; uint8 sync_mode:1; /* !! sync_mode 与 re_sel 相反 */
#define TSNR_FIX 3.5*100 uint8 rf_sel:1; /* !! sync_mode 与 re_sel 相反 */
}S_DPD_REG23;
enum{E_READ=0,E_WRITE=1};
typedef union
typedef enum {
{ S_DPD_REG23 dpd_bt;
DPD_STATE_OK=0, uint8 u8val;
DPD_STATE_ERR=0x10, }U_DPDCTL_REG23;
DPD_STATE_POWER_HIGH, #define TSNR_FIX 3.5*100
DPD_STATE_POWER_LOW,
DPD_STATE_POWER_TOO_HIGH, enum{E_READ=0,E_WRITE=1};
DPD_STATE_POWER_TOO_LOW,
DPD_STATE_ERR_OVER_RANGE, typedef enum
DPD_STATE_SYNC_OK, {
DPD_STATE_OK=0,
DPD_READ_CKECK_ERR, DPD_STATE_ERR=0x10,
DPD_WRITE_CHECK_ERR, DPD_STATE_POWER_HIGH,
DPD_STATE_POWER_LOW,
DPD_SYNC_TIMEOUT, DPD_STATE_POWER_TOO_HIGH,
DPD_CHECK_WPP_ERR_EXIT_HOLD, DPD_STATE_POWER_TOO_LOW,
DPD_STATE_ERR_OVER_RANGE,
//... DPD_STATE_SYNC_OK,
DPD_IDLE_ERR=0x30, DPD_READ_CKECK_ERR,
DPD_WRITE_CHECK_ERR,
DPD_PROC_EXIT = 0x99, DPD_SYNC_TIMEOUT,
DPD_UPDATING, DPD_CHECK_WPP_ERR_EXIT_HOLD,
DPD_SAVE_DATA = 0xAA,
DPD_LOAD_DATA = 0xBB, //...
DPD_STATUS_UPDATING = 0xff
}E_DPD_STATE; DPD_IDLE_ERR=0x30,
typedef enum{
E_DPD_NSAVE_NFLITER=0x00,//0x00 DPD_PROC_EXIT = 0x99,
E_DPD_NSAVE_FLITER =0x01,//0x01 DPD_UPDATING,
E_DPD_SAVE_NFLITER =0x10,//0x10 DPD_SAVE_DATA = 0xAA,
E_DPD_SAVE_FLITER =0x11,//0x11 DPD_LOAD_DATA = 0xBB,
}E_CTL_DPD;//cttb_para.wh_para.ctl_dpd DPD_STATUS_UPDATING = 0xff
}E_DPD_STATE;
// typedef enum{
typedef enum E_DPD_NSAVE_NFLITER=0x00,//0x00
{ E_DPD_NSAVE_FLITER =0x01,//0x01
E_LOAD_TO_MCU, E_DPD_SAVE_NFLITER =0x10,//0x10
E_LOAD_TO_FPGA, E_DPD_SAVE_FLITER =0x11,//0x11
}E_DPD_CURVE_PROC; }E_CTL_DPD;//cttb_para.wh_para.ctl_dpd
typedef enum
{ //
E_DPD_AREA0=0, typedef enum
E_DPD_AREA1, {
E_DPD_AREA2, E_LOAD_TO_MCU,
E_DPD_AREA3, E_LOAD_TO_FPGA,
E_DPD_AREA_FIRST_4K, }E_DPD_CURVE_PROC;
}E_DPD_CURVE_AREA;
typedef enum
{
typedef struct E_DPD_AREA0=0,
{ E_DPD_AREA1,
uint32 tx_data_iq_i; E_DPD_AREA2,
uint32 rx_data_iq_i; E_DPD_AREA3,
uint16 ob_wpp_max_i; E_DPD_AREA_FIRST_4K,
uint16 txaveamp_i; }E_DPD_CURVE_AREA;
uint16 txpow_cur_i;
uint16 rx_dgain_i;
uint16 rx_fgain_cw_i; typedef struct
uint16 dpd_dynamic_gain_i; // 发端算出、传给收端归一化的增益字 (14bit, seg5 0x32/0x33) {
uint16 ob_b_pwr_i; // 预失真前功率 (14bit, seg5 0x34/0x35) uint32 tx_data_iq_i;
uint16 ob_a_pwr_i; // 预失真后功率 (14bit, seg5 0x36/0x37) uint32 rx_data_iq_i;
}S_DPD_LOG_TYPE; uint16 ob_wpp_max_i;
uint16 txaveamp_i;
void refresh_update_dpd(void *parg,void *parv); uint16 txpow_cur_i;
int dpd_curve_proc(uint8 proc_mode); uint16 rx_dgain_i;
uint16 rx_fgain_cw_i;
void dpd_exit(void); uint16 dpd_dynamic_gain_i; // 发端算出、传给收端归一化的增益字 (14bit, seg5 0x32/0x33)
void dpd_set_clr(void); uint16 ob_b_pwr_i; // 预失真前功率 (14bit, seg5 0x34/0x35)
uint8 get_fpga_dpd_check(void); uint16 ob_a_pwr_i; // 预失真后功率 (14bit, seg5 0x36/0x37)
void dpd_boot_run_init(void); }S_DPD_LOG_TYPE;
extern void set_dpd_unit_area_auto_inc(uint8 inc_flg);
extern void set_tsnr_update_flg(uint8 up_flg); void refresh_update_dpd(void *parg,void *parv);
extern int update_tsnr_uimd_limd(uint8 rst_flg,uint8* p_phase); int dpd_curve_proc(uint8 proc_mode);
extern uint8 get_tsnr_update_flg(void);
extern void remote_set_dpd_clr(void); void dpd_exit(void);
extern uint8 conv_adpc_err_output(uint8 raw_dpd_err); void dpd_set_clr(void);
uint8 get_fpga_dpd_check(void);
extern void clear_dpd_data_file(void); void dpd_boot_run_init(void);
extern void set_ab_switch(E_AB_SEL ab_val); extern void set_dpd_unit_area_auto_inc(uint8 inc_flg);
extern u32 read_fpga_area_u32_check_sum(u8 check_type); extern void set_tsnr_update_flg(uint8 up_flg);
extern void clear_check_sum(S_CHECK_SUM *parea_check); extern int update_tsnr_uimd_limd(uint8 rst_flg,uint8* p_phase);
extern void calc_area_u32_check_sum(u32 *pcheck, u8 *pbuf, u32 len); extern uint8 get_tsnr_update_flg(void);
extern void calc_area_check_sum(u8 *pcheck, u8 *pbuf, u32 len); extern void remote_set_dpd_clr(void);
#endif extern uint8 conv_adpc_err_output(uint8 raw_dpd_err);
extern void clear_dpd_data_file(void);
extern void set_ab_switch(E_AB_SEL ab_val);
extern u32 read_fpga_area_u32_check_sum(u8 check_type);
extern void clear_check_sum(S_CHECK_SUM *parea_check);
extern void calc_area_u32_check_sum(u32 *pcheck, u8 *pbuf, u32 len);
extern void calc_area_check_sum(u8 *pcheck, u8 *pbuf, u32 len);
#endif