2257 lines
71 KiB
C
2257 lines
71 KiB
C
/*
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Copyright (C) 2010 NXP B.V., All Rights Reserved.
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This source code and any compilation or derivative thereof is the proprietary
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information of NXP B.V. and is confidential in nature. Under no circumstances
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is this software to be exposed to or placed under an Open Source License of
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any type without the expressed written permission of NXP B.V.
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*
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* \file tmbslTDA18273_RegDef.h
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*
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* %version: 3 %
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*
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* \date %modify_time%
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*
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* \author Christophe CAZETTES
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*
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* \brief Describe briefly the purpose of this file.
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*
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* REFERENCE DOCUMENTS :
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* TDA18273_Driver_User_Guide.pdf
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*
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* TVFE SW Arch V4 Template: Author Christophe CAZETTES
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*
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* \section info Change Information
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*
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*/
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/* File generated automatically from register description file */
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#pragma once
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#ifndef _TMBSL_TDA18273_REGDEF_H
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#define _TMBSL_TDA18273_REGDEF_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/*============================================================================*/
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/* Registers definitions: */
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/*============================================================================*/
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#define TDA18273_REG_ADD_SZ (0x01)
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#define TDA18273_REG_DATA_MAX_SZ (0x01)
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#define TDA18273_REG_MAP_NB_BYTES (0x6D)
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#define TDA18273_REG_DATA_LEN(_FIRST_REG, _LAST_REG) ( (_LAST_REG.Address - _FIRST_REG.Address) + 1)
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/* TDA18273 Register ID_byte_1 0x00 */
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extern const TDA18273_BitField_t gTDA18273_Reg_ID_byte_1;
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/* MS bit(s): Indicate if Device is a Master or a Slave*/
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/* 1 => Master device */
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/* 0 => Slave device */
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extern const TDA18273_BitField_t gTDA18273_Reg_ID_byte_1__MS;
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/* Ident_1 bit(s): MSB of device identifier */
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extern const TDA18273_BitField_t gTDA18273_Reg_ID_byte_1__Ident_1;
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/* TDA18273 Register ID_byte_2 0x00 */
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extern const TDA18273_BitField_t gTDA18273_Reg_ID_byte_2;
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/* Ident_2 bit(s): LSB of device identifier */
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extern const TDA18273_BitField_t gTDA18273_Reg_ID_byte_2__Ident_2;
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/* TDA18273 Register ID_byte_3 0x02 */
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extern const TDA18273_BitField_t gTDA18273_Reg_ID_byte_3;
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/* Major_rev bit(s): Major revision of device */
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extern const TDA18273_BitField_t gTDA18273_Reg_ID_byte_3__Major_rev;
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/* Major_rev bit(s): Minor revision of device */
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extern const TDA18273_BitField_t gTDA18273_Reg_ID_byte_3__Minor_rev;
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/* TDA18273 Register Thermo_byte_1 0x03 */
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extern const TDA18273_BitField_t gTDA18273_Reg_Thermo_byte_1;
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/* TM_D bit(s): Device temperature */
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extern const TDA18273_BitField_t gTDA18273_Reg_Thermo_byte_1__TM_D;
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/* TDA18273 Register Thermo_byte_2 0x04 */
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extern const TDA18273_BitField_t gTDA18273_Reg_Thermo_byte_2;
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/* TM_ON bit(s): Set device temperature measurement to ON or OFF */
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/* 1 => Temperature measurement ON */
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/* 0 => Temperature measurement OFF */
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extern const TDA18273_BitField_t gTDA18273_Reg_Thermo_byte_2__TM_ON;
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/* TDA18273 Register Power_state_byte_1 0x05 */
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extern const TDA18273_BitField_t gTDA18273_Reg_Power_state_byte_1;
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/* POR bit(s): Indicates that device just powered ON */
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/* 1 => POR: No access done to device */
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/* 0 => At least one access has been done to device */
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extern const TDA18273_BitField_t gTDA18273_Reg_Power_state_byte_1__POR;
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/* AGCs_Lock bit(s): Indicates that AGCs are locked */
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/* 1 => AGCs locked */
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/* 0 => AGCs not locked */
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extern const TDA18273_BitField_t gTDA18273_Reg_Power_state_byte_1__AGCs_Lock;
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/* Vsync_Lock bit(s): Indicates that VSync is locked */
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/* 1 => VSync locked */
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/* 0 => VSync not locked */
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extern const TDA18273_BitField_t gTDA18273_Reg_Power_state_byte_1__Vsync_Lock;
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/* LO_Lock bit(s): Indicates that LO is locked */
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/* 1 => LO locked */
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/* 0 => LO not locked */
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extern const TDA18273_BitField_t gTDA18273_Reg_Power_state_byte_1__LO_Lock;
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/* TDA18273 Register Power_state_byte_2 0x06 */
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extern const TDA18273_BitField_t gTDA18273_Reg_Power_state_byte_2;
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/* SM bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_Power_state_byte_2__SM;
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/* SM_XT bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_Power_state_byte_2__SM_XT;
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/* TDA18273 Register Input_Power_Level_byte 0x07 */
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extern const TDA18273_BitField_t gTDA18273_Reg_Input_Power_Level_byte;
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/* Power_Level bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_Input_Power_Level_byte__Power_Level;
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/* TDA18273 Register IRQ_status 0x08 */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_status;
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/* IRQ_status bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_status__IRQ_status;
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/* MSM_XtalCal_End bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_status__MSM_XtalCal_End;
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/* MSM_RSSI_End bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_status__MSM_RSSI_End;
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/* MSM_LOCalc_End bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_status__MSM_LOCalc_End;
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/* MSM_RFCal_End bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_status__MSM_RFCal_End;
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/* MSM_IRCAL_End bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_status__MSM_IRCAL_End;
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/* MSM_RCCal_End bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_status__MSM_RCCal_End;
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/* TDA18273 Register IRQ_enable 0x09 */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_enable;
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/* IRQ_Enable bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_enable__IRQ_Enable;
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/* MSM_XtalCal_Enable bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_enable__MSM_XtalCal_Enable;
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/* MSM_RSSI_Enable bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_enable__MSM_RSSI_Enable;
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/* MSM_LOCalc_Enable bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_enable__MSM_LOCalc_Enable;
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/* MSM_RFCal_Enable bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_enable__MSM_RFCal_Enable;
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/* MSM_IRCAL_Enable bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_enable__MSM_IRCAL_Enable;
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/* MSM_RCCal_Enable bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_enable__MSM_RCCal_Enable;
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/* TDA18273 Register IRQ_clear 0x0A */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_clear;
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/* IRQ_Clear bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_clear__IRQ_Clear;
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/* MSM_XtalCal_Clear bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_clear__MSM_XtalCal_Clear;
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/* MSM_RSSI_Clear bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_clear__MSM_RSSI_Clear;
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/* MSM_LOCalc_Clear bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_clear__MSM_LOCalc_Clear;
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/* MSM_RFCal_Clear bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_clear__MSM_RFCal_Clear;
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/* MSM_IRCAL_Clear bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_clear__MSM_IRCAL_Clear;
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/* MSM_RCCal_Clear bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_clear__MSM_RCCal_Clear;
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/* TDA18273 Register IRQ_set 0x0B */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_set;
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/* IRQ_Set bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_set__IRQ_Set;
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/* MSM_XtalCal_Set bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_set__MSM_XtalCal_Set;
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/* MSM_RSSI_Set bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_set__MSM_RSSI_Set;
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/* MSM_LOCalc_Set bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_set__MSM_LOCalc_Set;
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/* MSM_RFCal_Set bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_set__MSM_RFCal_Set;
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/* MSM_IRCAL_Set bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_set__MSM_IRCAL_Set;
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/* MSM_RCCal_Set bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IRQ_set__MSM_RCCal_Set;
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/* TDA18273 Register AGC1_byte_1 0x0C */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_1;
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/* AGC1_TOP bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_1__AGC1_TOP;
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/* TDA18273 Register AGC1_byte_2 0x0D */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_2;
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/* AGC1_Top_Mode_Val bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_2__AGC1_Top_Mode_Val;
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/* AGC1_Top_Mode bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_2__AGC1_Top_Mode;
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/* TDA18273 Register AGC2_byte_1 0x0E */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGC2_byte_1;
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/* AGC2_TOP bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGC2_byte_1__AGC2_TOP;
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/* TDA18273 Register AGCK_byte_1 0x0F */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGCK_byte_1;
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/* AGCs_Up_Step_assym bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGCK_byte_1__AGCs_Up_Step_assym;
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/* Pulse_Shaper_Disable bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGCK_byte_1__Pulse_Shaper_Disable;
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/* AGCK_Step bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGCK_byte_1__AGCK_Step;
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/* AGCK_Mode bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGCK_byte_1__AGCK_Mode;
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/* TDA18273 Register RF_AGC_byte 0x10 */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_AGC_byte;
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/* PD_AGC_Adapt3x bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_AGC_byte__PD_AGC_Adapt3x;
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/* RFAGC_Adapt_TOP bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_AGC_byte__RFAGC_Adapt_TOP;
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/* RFAGC_Low_BW bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_AGC_byte__RFAGC_Low_BW;
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/* RFAGC_Top bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_AGC_byte__RFAGC_Top;
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/* TDA18273 Register W_Filter_byte 0x11 */
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extern const TDA18273_BitField_t gTDA18273_Reg_W_Filter_byte;
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/* VHF_III_mode bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_W_Filter_byte__VHF_III_mode;
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/* RF_Atten_3dB bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_W_Filter_byte__RF_Atten_3dB;
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/* W_Filter_Enable bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_W_Filter_byte__W_Filter_Enable;
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/* W_Filter_Bypass bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_W_Filter_byte__W_Filter_Bypass;
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/* W_Filter bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_W_Filter_byte__W_Filter;
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/* W_Filter_Offset bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_W_Filter_byte__W_Filter_Offset;
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/* TDA18273 Register IR_Mixer_byte_1 0x12 */
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extern const TDA18273_BitField_t gTDA18273_Reg_IR_Mixer_byte_1;
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/* S2D_Gain bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IR_Mixer_byte_1__S2D_Gain;
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/* IR_Mixer_Top bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IR_Mixer_byte_1__IR_Mixer_Top;
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/* TDA18273 Register AGC5_byte_1 0x13 */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_1;
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/* AGCs_Do_Step_assym bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_1__AGCs_Do_Step_assym;
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/* AGC5_Ana bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_1__AGC5_Ana;
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/* AGC5_TOP bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_1__AGC5_TOP;
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/* TDA18273 Register IF_AGC_byte 0x14 */
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extern const TDA18273_BitField_t gTDA18273_Reg_IF_AGC_byte;
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/* IFnotchToRSSI bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IF_AGC_byte__IFnotchToRSSI;
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/* IF_level bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IF_AGC_byte__LPF_DCOffset_Corr;
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/* IF_level bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IF_AGC_byte__IF_level;
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/* TDA18273 Register IF_Byte_1 0x15 */
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extern const TDA18273_BitField_t gTDA18273_Reg_IF_Byte_1;
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/* IF_HP_Fc bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IF_Byte_1__IF_HP_Fc;
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/* IF_ATSC_Notch bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IF_Byte_1__IF_ATSC_Notch;
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/* LP_FC_Offset bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IF_Byte_1__LP_FC_Offset;
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/* LP_Fc bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IF_Byte_1__LP_Fc;
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/* TDA18273 Register Reference_Byte 0x16 */
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extern const TDA18273_BitField_t gTDA18273_Reg_Reference_Byte;
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/* Digital_Clock_Mode bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_Reference_Byte__Digital_Clock_Mode;
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/* XTout bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_Reference_Byte__XTout;
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/* TDA18273 Register IF_Frequency_byte 0x17 */
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extern const TDA18273_BitField_t gTDA18273_Reg_IF_Frequency_byte;
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/* IF_Freq bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IF_Frequency_byte__IF_Freq;
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/* TDA18273 Register RF_Frequency_byte_1 0x18 */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Frequency_byte_1;
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/* RF_Freq_1 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Frequency_byte_1__RF_Freq_1;
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/* TDA18273 Register RF_Frequency_byte_2 0x19 */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Frequency_byte_2;
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/* RF_Freq_2 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Frequency_byte_2__RF_Freq_2;
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/* TDA18273 Register RF_Frequency_byte_3 0x1A */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Frequency_byte_3;
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/* RF_Freq_3 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Frequency_byte_3__RF_Freq_3;
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/* TDA18273 Register MSM_byte_1 0x1B */
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extern const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1;
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/* RSSI_Meas bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1__RSSI_Meas;
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/* RF_CAL_AV bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1__RF_CAL_AV;
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/* RF_CAL bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1__RF_CAL;
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/* IR_CAL_Loop bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1__IR_CAL_Loop;
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/* IR_Cal_Image bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1__IR_Cal_Image;
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/* IR_CAL_Wanted bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1__IR_CAL_Wanted;
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/* RC_Cal bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1__RC_Cal;
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/* Calc_PLL bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1__Calc_PLL;
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/* TDA18273 Register MSM_byte_2 0x1C */
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extern const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_2;
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/* XtalCal_Launch bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_2__XtalCal_Launch;
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/* MSM_Launch bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_2__MSM_Launch;
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/* TDA18273 Register PowerSavingMode 0x1D */
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extern const TDA18273_BitField_t gTDA18273_Reg_PowerSavingMode;
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/* PSM_AGC1 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_PowerSavingMode__PSM_AGC1;
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/* PSM_Bandsplit_Filter bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_PowerSavingMode__PSM_Bandsplit_Filter;
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/* PSM_RFpoly bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_PowerSavingMode__PSM_RFpoly;
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/* PSM_Mixer bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_PowerSavingMode__PSM_Mixer;
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/* PSM_Ifpoly bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_PowerSavingMode__PSM_Ifpoly;
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/* PSM_Lodriver bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_PowerSavingMode__PSM_Lodriver;
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/* TDA18273 Register Power_Level_byte_2 0x1E */
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extern const TDA18273_BitField_t gTDA18273_Reg_Power_Level_byte_2;
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/* PD_PLD_read bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_Power_Level_byte_2__PD_PLD_read;
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/* IR_Target bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_Power_Level_byte_2__PLD_Temp_Slope;
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/* IR_GStep bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_Power_Level_byte_2__PLD_Gain_Corr;
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/* TDA18273 Register Adapt_Top_byte 0x1F */
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extern const TDA18273_BitField_t gTDA18273_Reg_Adapt_Top_byte;
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/* Fast_Mode_AGC bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_Adapt_Top_byte__Fast_Mode_AGC;
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/* Range_LNA_Adapt bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_Adapt_Top_byte__Range_LNA_Adapt;
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/* Index_K_LNA_Adapt bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_Adapt_Top_byte__Index_K_LNA_Adapt;
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/* Index_K_Top_Adapt bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_Adapt_Top_byte__Index_K_Top_Adapt;
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/* Ovld_Udld_FastUp bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_Adapt_Top_byte__Ovld_Udld_FastUp;
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/* TDA18273 Register Vsync_byte 0x20 */
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extern const TDA18273_BitField_t gTDA18273_Reg_Vsync_byte;
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/* Neg_modulation bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_Vsync_byte__Neg_modulation;
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/* Tracer_Step bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_Vsync_byte__Tracer_Step;
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/* Vsync_int bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_Vsync_byte__Vsync_int;
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/* Vsync_Thresh bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_Vsync_byte__Vsync_Thresh;
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/* Vsync_Len bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_Vsync_byte__Vsync_Len;
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/* TDA18273 Register Vsync_Mgt_byte 0x21 */
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extern const TDA18273_BitField_t gTDA18273_Reg_Vsync_Mgt_byte;
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/* PD_Vsync_Mgt bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_Vsync_Mgt_byte__PD_Vsync_Mgt;
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/* PD_Ovld bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_Vsync_Mgt_byte__PD_Ovld;
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/* PD_Ovld_RF bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_Vsync_Mgt_byte__PD_Ovld_RF;
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/* AGC_Ovld_TOP bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_Vsync_Mgt_byte__AGC_Ovld_TOP;
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/* Up_Step_Ovld bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_Vsync_Mgt_byte__Up_Step_Ovld;
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/* AGC_Ovld_Timer bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_Vsync_Mgt_byte__AGC_Ovld_Timer;
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/* TDA18273 Register IR_Mixer_byte_2 0x22 */
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extern const TDA18273_BitField_t gTDA18273_Reg_IR_Mixer_byte_2;
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/* IR_Mixer_loop_off bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IR_Mixer_byte_2__IR_Mixer_loop_off;
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/* IR_Mixer_Do_step bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IR_Mixer_byte_2__IR_Mixer_Do_step;
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/* Hi_Pass bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IR_Mixer_byte_2__Hi_Pass;
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/* IF_Notch bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IR_Mixer_byte_2__IF_Notch;
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/* TDA18273 Register AGC1_byte_3 0x23 */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_3;
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/* AGC1_loop_off bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_3__AGC1_loop_off;
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/* AGC1_Do_step bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_3__AGC1_Do_step;
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/* Force_AGC1_gain bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_3__Force_AGC1_gain;
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/* AGC1_Gain bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_3__AGC1_Gain;
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/* TDA18273 Register RFAGCs_Gain_byte_1 0x24 */
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extern const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_1;
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/* PLD_DAC_Scale bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_1__PLD_DAC_Scale;
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/* PLD_CC_Enable bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_1__PLD_CC_Enable;
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/* PLD_Temp_Enable bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_1__PLD_Temp_Enable;
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/* TH_AGC_Adapt34 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_1__TH_AGC_Adapt34;
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/* RFAGC_Sense_Enable bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_1__RFAGC_Sense_Enable;
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/* RFAGC_K_Bypass bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_1__RFAGC_K_Bypass;
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/* RFAGC_K_8 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_1__RFAGC_K_8;
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/* TDA18273 Register RFAGCs_Gain_byte_2 0x25 */
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extern const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_2;
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/* RFAGC_K bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_2__RFAGC_K;
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/* TDA18273 Register AGC5_byte_2 0x26 */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_2;
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/* AGC5_loop_off bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_2__AGC5_loop_off;
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/* AGC5_Do_step bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_2__AGC5_Do_step;
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/* Force_AGC5_gain bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_2__Force_AGC5_gain;
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/* AGC5_Gain bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_2__AGC5_Gain;
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/* TDA18273 Register RF_Cal_byte_1 0x27 */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_1;
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/* RFCAL_Offset_Cprog0 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_1__RFCAL_Offset_Cprog0;
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/* RFCAL_Offset_Cprog1 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_1__RFCAL_Offset_Cprog1;
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/* RFCAL_Offset_Cprog2 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_1__RFCAL_Offset_Cprog2;
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/* RFCAL_Offset_Cprog3 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_1__RFCAL_Offset_Cprog3;
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/* TDA18273 Register RF_Cal_byte_2 0x28 */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_2;
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/* RFCAL_Offset_Cprog4 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_2__RFCAL_Offset_Cprog4;
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/* RFCAL_Offset_Cprog5 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_2__RFCAL_Offset_Cprog5;
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/* RFCAL_Offset_Cprog6 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_2__RFCAL_Offset_Cprog6;
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/* RFCAL_Offset_Cprog7 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_2__RFCAL_Offset_Cprog7;
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/* TDA18273 Register RF_Cal_byte_3 0x29 */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_3;
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/* RFCAL_Offset_Cprog8 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_3__RFCAL_Offset_Cprog8;
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/* RFCAL_Offset_Cprog9 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_3__RFCAL_Offset_Cprog9;
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/* RFCAL_Offset_Cprog10 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_3__RFCAL_Offset_Cprog10;
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/* RFCAL_Offset_Cprog11 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_3__RFCAL_Offset_Cprog11;
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/* TDA18273 Register Bandsplit_Filter_byte 0x2A */
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extern const TDA18273_BitField_t gTDA18273_Reg_Bandsplit_Filter_byte;
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/* Bandsplit_Filter_SubBand bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_Bandsplit_Filter_byte__Bandsplit_Filter_SubBand;
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/* TDA18273 Register RF_Filters_byte_1 0x2B */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_1;
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/* RF_Filter_Bypass bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_1__RF_Filter_Bypass;
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/* AGC2_loop_off bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_1__AGC2_loop_off;
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/* Force_AGC2_gain bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_1__Force_AGC2_gain;
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/* RF_Filter_Gv bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_1__RF_Filter_Gv;
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/* RF_Filter_Band bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_1__RF_Filter_Band;
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/* TDA18273 Register RF_Filters_byte_2 0x2C */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_2;
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/* RF_Filter_Cap bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_2__RF_Filter_Cap;
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/* TDA18273 Register RF_Filters_byte_3 0x2D */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_3;
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/* AGC2_Do_step bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_3__AGC2_Do_step;
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/* Gain_Taper bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_3__Gain_Taper;
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/* TDA18273 Register RF_Band_Pass_Filter_byte 0x2E */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Band_Pass_Filter_byte;
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/* RF_BPF_Bypass bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Band_Pass_Filter_byte__RF_BPF_Bypass;
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/* RF_BPF bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RF_Band_Pass_Filter_byte__RF_BPF;
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/* TDA18273 Register CP_Current_byte 0x2F */
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extern const TDA18273_BitField_t gTDA18273_Reg_CP_Current_byte;
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/* LO_CP_Current bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_CP_Current_byte__LO_CP_Current;
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/* N_CP_Current bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_CP_Current_byte__N_CP_Current;
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/* TDA18273 Register AGCs_DetOut_byte 0x30 */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte;
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/* Up_AGC5 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte__Up_AGC5;
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/* Do_AGC5 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte__Do_AGC5;
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/* Up_AGC4 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte__Up_AGC4;
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/* Do_AGC4 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte__Do_AGC4;
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/* Up_AGC2 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte__Up_AGC2;
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/* Do_AGC2 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte__Do_AGC2;
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/* Up_AGC1 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte__Up_AGC1;
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/* Do_AGC1 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte__Do_AGC1;
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/* TDA18273 Register RFAGCs_Gain_byte_3 0x31 */
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extern const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_3;
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/* AGC2_Gain_Read bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_3__AGC2_Gain_Read;
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/* AGC1_Gain_Read bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_3__AGC1_Gain_Read;
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/* TDA18273 Register RFAGCs_Gain_byte_4 0x32 */
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extern const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_4;
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/* Cprog_Read bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_4__Cprog_Read;
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/* TDA18273 Register RFAGCs_Gain_byte_5 0x33 */
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extern const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_5;
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/* RFAGC_Read_K_8 bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_5__RFAGC_Read_K_8;
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/* Do_AGC1bis bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_5__Do_AGC1bis;
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/* AGC1_Top_Adapt_Low bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_5__AGC1_Top_Adapt_Low;
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/* Up_LNA_Adapt bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_5__Up_LNA_Adapt;
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/* Do_LNA_Adapt bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_5__Do_LNA_Adapt;
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/* TOP_AGC3_Read bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_5__TOP_AGC3_Read;
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/* TDA18273 Register RFAGCs_Gain_byte_6 0x34 */
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extern const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_6;
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/* RFAGC_Read_K bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_6__RFAGC_Read_K;
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/* TDA18273 Register IFAGCs_Gain_byte 0x35 */
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extern const TDA18273_BitField_t gTDA18273_Reg_IFAGCs_Gain_byte;
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/* AGC5_Gain_Read bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IFAGCs_Gain_byte__AGC5_Gain_Read;
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/* AGC4_Gain_Read bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_IFAGCs_Gain_byte__AGC4_Gain_Read;
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/* TDA18273 Register RSSI_byte_1 0x36 */
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extern const TDA18273_BitField_t gTDA18273_Reg_RSSI_byte_1;
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/* RSSI bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RSSI_byte_1__RSSI;
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/* TDA18273 Register RSSI_byte_2 0x37 */
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extern const TDA18273_BitField_t gTDA18273_Reg_RSSI_byte_2;
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/* RSSI_AV bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RSSI_byte_2__RSSI_AV;
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/* RSSI_Cap_Reset_En bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RSSI_byte_2__RSSI_Cap_Reset_En;
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/* RSSI_Cap_Val bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RSSI_byte_2__RSSI_Cap_Val;
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/* RSSI_Ck_Speed bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RSSI_byte_2__RSSI_Ck_Speed;
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/* RSSI_Dicho_not bit(s): */
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extern const TDA18273_BitField_t gTDA18273_Reg_RSSI_byte_2__RSSI_Dicho_not;
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/* TDA18273 Register Misc_byte 0x38 */
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extern const TDA18273_BitField_t gTDA18273_Reg_Misc_byte;
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/* RFCALPOR_I2C bit(s): */
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|
extern const TDA18273_BitField_t gTDA18273_Reg_Misc_byte__RFCALPOR_I2C;
|
|
/* PD_Underload bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Misc_byte__PD_Underload;
|
|
/* DDS_Polarity bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Misc_byte__DDS_Polarity;
|
|
/* IRQ_Mode bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Misc_byte__IRQ_Mode;
|
|
/* IRQ_Polarity bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Misc_byte__IRQ_Polarity;
|
|
|
|
|
|
/* TDA18273 Register rfcal_log_0 0x39 */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_0;
|
|
/* rfcal_log_0 bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_0__rfcal_log_0;
|
|
|
|
|
|
/* TDA18273 Register rfcal_log_1 0x3A */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_1;
|
|
/* rfcal_log_1 bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_1__rfcal_log_1;
|
|
|
|
|
|
/* TDA18273 Register rfcal_log_2 0x3B */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_2;
|
|
/* rfcal_log_2 bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_2__rfcal_log_2;
|
|
|
|
|
|
/* TDA18273 Register rfcal_log_3 0x3C */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_3;
|
|
/* rfcal_log_3 bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_3__rfcal_log_3;
|
|
|
|
|
|
/* TDA18273 Register rfcal_log_4 0x3D */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_4;
|
|
/* rfcal_log_4 bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_4__rfcal_log_4;
|
|
|
|
|
|
/* TDA18273 Register rfcal_log_5 0x3E */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_5;
|
|
/* rfcal_log_5 bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_5__rfcal_log_5;
|
|
|
|
|
|
/* TDA18273 Register rfcal_log_6 0x3F */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_6;
|
|
/* rfcal_log_6 bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_6__rfcal_log_6;
|
|
|
|
|
|
/* TDA18273 Register rfcal_log_7 0x40 */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_7;
|
|
/* rfcal_log_7 bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_7__rfcal_log_7;
|
|
|
|
|
|
/* TDA18273 Register rfcal_log_8 0x41 */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_8;
|
|
/* rfcal_log_8 bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_8__rfcal_log_8;
|
|
|
|
|
|
/* TDA18273 Register rfcal_log_9 0x42 */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_9;
|
|
/* rfcal_log_9 bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_9__rfcal_log_9;
|
|
|
|
|
|
/* TDA18273 Register rfcal_log_10 0x43 */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_10;
|
|
/* rfcal_log_10 bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_10__rfcal_log_10;
|
|
|
|
|
|
/* TDA18273 Register rfcal_log_11 0x44 */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_11;
|
|
/* rfcal_log_11 bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_11__rfcal_log_11;
|
|
|
|
|
|
|
|
/* TDA18273 Register Main_Post_Divider_byte 0x51 */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Main_Post_Divider_byte;
|
|
/* LOPostDiv bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Main_Post_Divider_byte__LOPostDiv;
|
|
/* LOPresc bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Main_Post_Divider_byte__LOPresc;
|
|
|
|
|
|
/* TDA18273 Register Sigma_delta_byte_1 0x52 */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_1;
|
|
/* LO_Int bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_1__LO_Int;
|
|
|
|
|
|
/* TDA18273 Register Sigma_delta_byte_2 0x53 */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_2;
|
|
/* LO_Frac_2 bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_2__LO_Frac_2;
|
|
|
|
|
|
/* TDA18273 Register Sigma_delta_byte_3 0x54 */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_3;
|
|
/* LO_Frac_1 bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_3__LO_Frac_1;
|
|
|
|
|
|
/* TDA18273 Register Sigma_delta_byte_4 0x55 */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_4;
|
|
/* LO_Frac_0 bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_4__LO_Frac_0;
|
|
|
|
|
|
/* TDA18273 Register Sigma_delta_byte_5 0x56 */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_5;
|
|
/* N_K_correct_manual bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_5__N_K_correct_manual;
|
|
/* LO_Calc_Disable bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_5__LO_Calc_Disable;
|
|
|
|
|
|
/* TDA18273 Register Regulators_byte 0x58 */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Regulators_byte;
|
|
/* RF_Reg bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Regulators_byte__RF_Reg;
|
|
|
|
|
|
/* TDA18273 Register IR_Cal_byte_5 0x5B */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_IR_Cal_byte_5;
|
|
/* Mixer_Gain_Bypass bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_IR_Cal_byte_5__Mixer_Gain_Bypass;
|
|
/* IR_Mixer_Gain bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_IR_Cal_byte_5__IR_Mixer_Gain;
|
|
|
|
|
|
/* TDA18273 Register Power_Down_byte_2 0x5F */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Power_Down_byte_2;
|
|
/* PD_LNA bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Power_Down_byte_2__PD_LNA;
|
|
/* PD_Det4 bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Power_Down_byte_2__PD_Det4;
|
|
/* PD_Det3 bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Power_Down_byte_2__PD_Det3;
|
|
/* PD_Det1 bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Power_Down_byte_2__PD_Det1;
|
|
|
|
/* TDA18273 Register Power_Down_byte_3 0x60 */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Power_Down_byte_3;
|
|
/* Force_Soft_Reset bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Power_Down_byte_3__Force_Soft_Reset;
|
|
/* Soft_Reset bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Power_Down_byte_3__Soft_Reset;
|
|
|
|
/* TDA18273 Register Charge_pump_byte 0x64 */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Charge_pump_byte;
|
|
/* ICP_Bypass bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Charge_pump_byte__ICP_Bypass;
|
|
/* ICP bit(s): */
|
|
extern const TDA18273_BitField_t gTDA18273_Reg_Charge_pump_byte__ICP;
|
|
|
|
|
|
|
|
/* "C" Bit-fields definitions */
|
|
|
|
/* TDA18273 Register ID_byte_1 0x00 */
|
|
typedef union
|
|
{
|
|
UInt8 ID_byte_1;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 MS : 1;
|
|
UInt8 Ident_1 : 7;
|
|
#else
|
|
UInt8 Ident_1 : 7;
|
|
UInt8 MS : 1;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_ID_byte_1;
|
|
#define TDA18273_REG_ADD_ID_byte_1 (0x00)
|
|
#define TDA18273_REG_SZ_ID_byte_1 (0x01)
|
|
|
|
/* TDA18273 Register ID_byte_2 0x01 */
|
|
typedef union
|
|
{
|
|
UInt8 ID_byte_2;
|
|
struct
|
|
{
|
|
UInt8 Ident_2 : 8;
|
|
}bF;
|
|
}TDA18273_Reg_ID_byte_2;
|
|
#define TDA18273_REG_ADD_ID_byte_2 (0x01)
|
|
#define TDA18273_REG_SZ_ID_byte_2 (0x01)
|
|
|
|
/* TDA18273 Register ID_byte_3 0x02 */
|
|
typedef union
|
|
{
|
|
UInt8 ID_byte_3;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 Major_rev : 4;
|
|
UInt8 Minor_rev : 4;
|
|
#else
|
|
UInt8 Minor_rev : 4;
|
|
UInt8 Major_rev : 4;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_ID_byte_3;
|
|
#define TDA18273_REG_ADD_ID_byte_3 (0x02)
|
|
#define TDA18273_REG_SZ_ID_byte_3 (0x01)
|
|
|
|
/* TDA18273 Register Thermo_byte_1 0x03 */
|
|
typedef union
|
|
{
|
|
UInt8 Thermo_byte_1;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 UNUSED_D7 : 1;
|
|
UInt8 TM_D : 7;
|
|
#else
|
|
UInt8 TM_D : 7;
|
|
UInt8 UNUSED_D7 : 1;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_Thermo_byte_1;
|
|
#define TDA18273_REG_ADD_Thermo_byte_1 (0x03)
|
|
#define TDA18273_REG_SZ_Thermo_byte_1 (0x01)
|
|
|
|
/* TDA18273 Register Thermo_byte_2 0x04 */
|
|
typedef union
|
|
{
|
|
UInt8 Thermo_byte_2;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 UNUSED_D7_1 : 7;
|
|
UInt8 TM_ON : 1;
|
|
#else
|
|
UInt8 TM_ON : 1;
|
|
UInt8 UNUSED_D7_1 : 7;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_Thermo_byte_2;
|
|
#define TDA18273_REG_ADD_Thermo_byte_2 (0x04)
|
|
#define TDA18273_REG_SZ_Thermo_byte_2 (0x01)
|
|
|
|
/* TDA18273 Register Power_state_byte_1 0x05 */
|
|
typedef union
|
|
{
|
|
UInt8 Power_state_byte_1;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 POR : 1;
|
|
UInt8 UNUSED_D6_D3 : 4;
|
|
UInt8 AGCs_Lock : 1;
|
|
UInt8 Vsync_Lock : 1;
|
|
UInt8 LO_Lock : 1;
|
|
|
|
#else
|
|
UInt8 LO_Lock : 1;
|
|
UInt8 Vsync_Lock : 1;
|
|
UInt8 AGCs_Lock : 1;
|
|
UInt8 UNUSED_D6_D3 : 4;
|
|
UInt8 POR : 1;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_Power_state_byte_1;
|
|
#define TDA18273_REG_ADD_Power_state_byte_1 (0x05)
|
|
#define TDA18273_REG_SZ_Power_state_byte_1 (0x01)
|
|
|
|
/* TDA18273 Register Power_state_byte_2 0x06 */
|
|
typedef union
|
|
{
|
|
UInt8 Power_state_byte_2;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 UNUSED_D7_2 : 6;
|
|
UInt8 SM : 1;
|
|
UInt8 SM_XT : 1;
|
|
#else
|
|
UInt8 SM_XT : 1;
|
|
UInt8 SM : 1;
|
|
UInt8 UNUSED_D7_2 : 6;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_Power_state_byte_2;
|
|
#define TDA18273_REG_ADD_Power_state_byte_2 (0x06)
|
|
#define TDA18273_REG_SZ_Power_state_byte_2 (0x01)
|
|
|
|
/* TDA18273 Register Input_Power_Level_byte 0x07 */
|
|
typedef union
|
|
{
|
|
UInt8 Input_Power_Level_byte;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 Power_Level : 8;
|
|
#else
|
|
UInt8 Power_Level : 8;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_Input_Power_Level_byte;
|
|
#define TDA18273_REG_ADD_Input_Power_Level_byte (0x07)
|
|
#define TDA18273_REG_SZ_Input_Power_Level_byte (0x01)
|
|
|
|
/* TDA18273 Register IRQ_status 0x08 */
|
|
typedef union
|
|
{
|
|
UInt8 IRQ_status;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 IRQ_status : 1;
|
|
UInt8 UNUSED_D6 : 1;
|
|
UInt8 MSM_XtalCal_End : 1;
|
|
UInt8 MSM_RSSI_End : 1;
|
|
UInt8 MSM_LOCalc_End : 1;
|
|
UInt8 MSM_RFCal_End : 1;
|
|
UInt8 MSM_IRCAL_End : 1;
|
|
UInt8 MSM_RCCal_End : 1;
|
|
#else
|
|
UInt8 MSM_RCCal_End : 1;
|
|
UInt8 MSM_IRCAL_End : 1;
|
|
UInt8 MSM_RFCal_End : 1;
|
|
UInt8 MSM_LOCalc_End : 1;
|
|
UInt8 MSM_RSSI_End : 1;
|
|
UInt8 MSM_XtalCal_End : 1;
|
|
UInt8 UNUSED_D6 : 1;
|
|
UInt8 IRQ_status : 1;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_IRQ_status;
|
|
#define TDA18273_REG_ADD_IRQ_status (0x08)
|
|
#define TDA18273_REG_SZ_IRQ_status (0x01)
|
|
|
|
/* TDA18273 Register IRQ_enable 0x09 */
|
|
typedef union
|
|
{
|
|
UInt8 IRQ_enable;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 IRQ_Enable : 1;
|
|
UInt8 UNUSED_D6 : 1;
|
|
UInt8 XtalCal_Enable : 1;
|
|
UInt8 MSM_RSSI_Enable : 1;
|
|
UInt8 MSM_LOCalc_Enable : 1;
|
|
UInt8 MSM_RFCAL_Enable : 1;
|
|
UInt8 MSM_IRCAL_Enable : 1;
|
|
UInt8 MSM_RCCal_Enable : 1;
|
|
#else
|
|
UInt8 MSM_RCCal_Enable : 1;
|
|
UInt8 MSM_IRCAL_Enable : 1;
|
|
UInt8 MSM_RFCAL_Enable : 1;
|
|
UInt8 MSM_LOCalc_Enable : 1;
|
|
UInt8 MSM_RSSI_Enable : 1;
|
|
UInt8 XtalCal_Enable : 1;
|
|
UInt8 UNUSED_D6 : 1;
|
|
UInt8 IRQ_Enable : 1;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_IRQ_enable;
|
|
#define TDA18273_REG_ADD_IRQ_enable (0x09)
|
|
#define TDA18273_REG_SZ_IRQ_enable (0x01)
|
|
|
|
/* TDA18273 Register IRQ_clear 0x0A */
|
|
typedef union
|
|
{
|
|
UInt8 IRQ_clear;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 IRQ_Clear : 1;
|
|
UInt8 UNUSED_D6 : 1;
|
|
UInt8 XtalCal_Clear : 1;
|
|
UInt8 MSM_RSSI_Clear : 1;
|
|
UInt8 MSM_LOCalc_Clear : 1;
|
|
UInt8 MSM_RFCal_Clear : 1;
|
|
UInt8 MSM_IRCAL_Clear : 1;
|
|
UInt8 MSM_RCCal_Clear : 1;
|
|
#else
|
|
UInt8 MSM_RCCal_Clear : 1;
|
|
UInt8 MSM_IRCAL_Clear : 1;
|
|
UInt8 MSM_RFCal_Clear : 1;
|
|
UInt8 MSM_LOCalc_Clear : 1;
|
|
UInt8 MSM_RSSI_Clear : 1;
|
|
UInt8 XtalCal_Clear : 1;
|
|
UInt8 UNUSED_D6 : 1;
|
|
UInt8 IRQ_Clear : 1;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_IRQ_clear;
|
|
#define TDA18273_REG_ADD_IRQ_clear (0x0A)
|
|
#define TDA18273_REG_SZ_IRQ_clear (0x01)
|
|
|
|
/* TDA18273 Register IRQ_set 0x0B */
|
|
typedef union
|
|
{
|
|
UInt8 IRQ_set;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 IRQ_Set : 1;
|
|
UInt8 UNUSED_D6 : 1;
|
|
UInt8 XtalCal_Set : 1;
|
|
UInt8 MSM_RSSI_Set : 1;
|
|
UInt8 MSM_LOCalc_Set : 1;
|
|
UInt8 MSM_RFCal_Set : 1;
|
|
UInt8 MSM_IRCAL_Set : 1;
|
|
UInt8 MSM_RCCal_Set : 1;
|
|
#else
|
|
UInt8 MSM_RCCal_Set : 1;
|
|
UInt8 MSM_IRCAL_Set : 1;
|
|
UInt8 MSM_RFCal_Set : 1;
|
|
UInt8 MSM_LOCalc_Set : 1;
|
|
UInt8 MSM_RSSI_Set : 1;
|
|
UInt8 XtalCal_Set : 1;
|
|
UInt8 UNUSED_D6 : 1;
|
|
UInt8 IRQ_Set : 1;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_IRQ_set;
|
|
#define TDA18273_REG_ADD_IRQ_set (0x0B)
|
|
#define TDA18273_REG_SZ_IRQ_set (0x01)
|
|
|
|
/* TDA18273 Register AGC1_byte_1 0x0C */
|
|
typedef union
|
|
{
|
|
UInt8 AGC1_byte_1;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 UNUSED_D7_4 : 4;
|
|
UInt8 AGC1_TOP : 4;
|
|
#else
|
|
UInt8 AGC1_TOP : 4;
|
|
UInt8 UNUSED_D7_4 : 4;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_AGC1_byte_1;
|
|
#define TDA18273_REG_ADD_AGC1_byte_1 (0xOC)
|
|
#define TDA18273_REG_SZ_AGC1_byte_1 (0x01)
|
|
|
|
/* TDA18273 Register AGC1_byte_2 0x0D */
|
|
typedef union
|
|
{
|
|
UInt8 AGC1_byte_2;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 UNUSED_D7_5 : 3;
|
|
UInt8 AGC1_Top_Mode_Val : 2;
|
|
UInt8 AGC1_Top_Mode : 3;
|
|
#else
|
|
UInt8 AGC1_Top_Mode : 3;
|
|
UInt8 AGC1_Top_Mode_Val : 2;
|
|
UInt8 UNUSED_D7_5 : 3;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_AGC1_byte_2;
|
|
#define TDA18273_REG_ADD_AGC1_byte_2 (0xOD)
|
|
#define TDA18273_REG_SZ_AGC1_byte_2 (0x01)
|
|
|
|
/* TDA18273 Register AGC2_byte_1 0xOE */
|
|
typedef union
|
|
{
|
|
UInt8 AGC2_byte_1;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 UNUSED_D7_5 : 3;
|
|
UInt8 AGC2_TOP : 5;
|
|
#else
|
|
UInt8 AGC2_TOP : 5;
|
|
UInt8 UNUSED_D7_5 : 3;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_AGC2_byte_1;
|
|
#define TDA18273_REG_ADD_AGC2_byte_1 (0x0E)
|
|
#define TDA18273_REG_SZ_AGC2_byte_1 (0x01)
|
|
|
|
/* TDA18273 Register AGCK_byte_1 0x0F */
|
|
typedef union
|
|
{
|
|
UInt8 AGCK_byte_1;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 AGCs_Up_Step_assym : 2;
|
|
UInt8 UNUSED_D5 : 1;
|
|
UInt8 Pulse_Shaper_Disable : 1;
|
|
UInt8 AGCK_Step : 2;
|
|
UInt8 AGCK_Mode : 2;
|
|
#else
|
|
UInt8 AGCK_Mode : 2;
|
|
UInt8 AGCK_Step : 2;
|
|
UInt8 Pulse_Shaper_Disable : 1;
|
|
UInt8 UNUSED_D5 : 1;
|
|
UInt8 AGCs_Up_Step_assym : 2;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_AGCK_byte_1;
|
|
#define TDA18273_REG_ADD_AGCK_byte_1 (0x0F)
|
|
#define TDA18273_REG_SZ_AGCK_byte_1 (0x01)
|
|
|
|
/* TDA18273 Register RF_AGC_byte 0x10 */
|
|
typedef union
|
|
{
|
|
UInt8 RF_AGC_byte;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 PD_AGC_Adapt3x : 2;
|
|
UInt8 RFAGC_Adapt_TOP : 2;
|
|
UInt8 RFAGC_Low_BW : 1;
|
|
UInt8 RFAGC_Top : 3;
|
|
#else
|
|
UInt8 RFAGC_Top : 3;
|
|
UInt8 RFAGC_Low_BW : 1;
|
|
UInt8 RFAGC_Adapt_TOP : 2;
|
|
UInt8 PD_AGC_Adapt3x : 2;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_RF_AGC_byte;
|
|
#define TDA18273_REG_ADD_RF_AGC_byte (0x10)
|
|
#define TDA18273_REG_SZ_RF_AGC_byte (0x01)
|
|
|
|
/* TDA18273 Register W_Filter_byte 0x11 */
|
|
typedef union
|
|
{
|
|
UInt8 W_Filter_byte;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 VHF_III_mode : 1;
|
|
UInt8 RF_Atten_3dB : 1;
|
|
UInt8 W_Filter_Enable : 1;
|
|
UInt8 W_Filter_Bypass : 1;
|
|
UInt8 W_Filter : 2;
|
|
UInt8 W_Filter_Offset : 2;
|
|
#else
|
|
UInt8 W_Filter_Offset : 2;
|
|
UInt8 W_Filter : 2;
|
|
UInt8 W_Filter_Bypass : 1;
|
|
UInt8 W_Filter_Enable : 1;
|
|
UInt8 RF_Atten_3dB : 1;
|
|
UInt8 VHF_III_mode : 1;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_W_Filter_byte;
|
|
#define TDA18273_REG_ADD_W_Filter_byte (0x11)
|
|
#define TDA18273_REG_SZ_W_Filter_byte (0x01)
|
|
|
|
/* TDA18273 Register IR_Mixer_byte_1 0x12 */
|
|
typedef union
|
|
{
|
|
UInt8 IR_Mixer_byte_1;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 UNUSED_D7_6 : 2;
|
|
UInt8 S2D_Gain : 2;
|
|
UInt8 IR_Mixer_Top : 4;
|
|
#else
|
|
UInt8 IR_Mixer_Top : 4;
|
|
UInt8 S2D_Gain : 2;
|
|
UInt8 UNUSED_D7_6 : 2;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_IR_Mixer_byte_1;
|
|
#define TDA18273_REG_ADD_IR_Mixer_byte_1 (0x12)
|
|
#define TDA18273_REG_SZ_IR_Mixer_byte_1 (0x01)
|
|
|
|
/* TDA18273 Register AGC5_byte_1 0x13 */
|
|
typedef union
|
|
{
|
|
UInt8 AGC5_byte_1;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 UNUSED_D7 : 1;
|
|
UInt8 AGCs_Do_Step_assym : 2;
|
|
UInt8 AGC5_Ana : 1;
|
|
UInt8 AGC5_TOP : 4;
|
|
#else
|
|
UInt8 AGC5_TOP : 4;
|
|
UInt8 AGC5_Ana : 1;
|
|
UInt8 AGCs_Do_Step_assym : 2;
|
|
UInt8 UNUSED_D7 : 1;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_AGC5_byte_1;
|
|
#define TDA18273_REG_ADD_AGC5_byte_1 (0x13)
|
|
#define TDA18273_REG_SZ_AGC5_byte_1 (0x01)
|
|
|
|
|
|
/* TDA18273 Register IF_AGC_byte 0x14 */
|
|
typedef union
|
|
{
|
|
UInt8 IF_AGC_byte;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 IFnotchToRSSI:1;
|
|
UInt8 LPF_DCOffset_Corr:1;
|
|
UInt8 UNUSED_D5_3 : 3;
|
|
UInt8 IF_level : 3;
|
|
#else
|
|
UInt8 IF_level : 3;
|
|
UInt8 UNUSED_D5_3 : 3;
|
|
UInt8 LPF_DCOffset_Corr : 1;
|
|
UInt8 IFnotchToRSSI : 1;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_IF_AGC_byte;
|
|
#define TDA18273_REG_ADD_IF_AGC_byte (0x14)
|
|
#define TDA18273_REG_SZ_IF_AGC_byte (0x01)
|
|
|
|
/* TDA18273 Register IF_Byte_1 0x15 */
|
|
typedef union
|
|
{
|
|
UInt8 IF_Byte_1;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 IF_HP_Fc : 2;
|
|
UInt8 IF_ATSC_Notch : 1;
|
|
UInt8 LP_FC_Offset : 2;
|
|
UInt8 LP_Fc : 3;
|
|
#else
|
|
UInt8 LP_Fc : 3;
|
|
UInt8 LP_FC_Offset : 2;
|
|
UInt8 IF_ATSC_Notch : 1;
|
|
UInt8 IF_HP_Fc : 2;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_IF_Byte_1;
|
|
#define TDA18273_REG_ADD_IF_Byte_1 (0x15)
|
|
#define TDA18273_REG_SZ_IF_Byte_1 (0x01)
|
|
|
|
/* TDA18273 Register Reference_Byte 0x16 */
|
|
typedef union
|
|
{
|
|
UInt8 Reference_Byte;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 Digital_Clock_Mode : 2;
|
|
UInt8 UNUSED_D5_2 : 4;
|
|
UInt8 XTout : 2;
|
|
#else
|
|
UInt8 XTout : 2;
|
|
UInt8 UNUSED_D5_2 : 4;
|
|
UInt8 Digital_Clock_Mode : 2;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_Reference_Byte;
|
|
#define TDA18273_REG_ADD_Reference_Byte (0x16)
|
|
#define TDA18273_REG_SZ_Reference_Byte (0x01)
|
|
|
|
/* TDA18273 Register IF_Frequency_byte 0x17 */
|
|
typedef union
|
|
{
|
|
UInt8 IF_Frequency_byte;
|
|
struct
|
|
{
|
|
UInt8 IF_Freq : 8;
|
|
}bF;
|
|
}TDA18273_Reg_IF_Frequency_byte;
|
|
#define TDA18273_REG_ADD_IF_Frequency_byte (0x17)
|
|
#define TDA18273_REG_SZ_IF_Frequency_byte (0x01)
|
|
|
|
|
|
/* TDA18273 Register RF_Frequency_byte_1 0x18 */
|
|
typedef union
|
|
{
|
|
UInt8 RF_Frequency_byte_1;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 UNUSED_D7_4 : 4;
|
|
UInt8 RF_Freq_1 : 4;
|
|
#else
|
|
UInt8 RF_Freq_1 : 4;
|
|
UInt8 UNUSED_D7_4 : 4;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_RF_Frequency_byte_1;
|
|
#define TDA18273_REG_ADD_RF_Frequency_byte_1 (0x18)
|
|
#define TDA18273_REG_SZ_RF_Frequency_byte_1 (0x01)
|
|
|
|
/* TDA18273 Register RF_Frequency_byte_2 0x19 */
|
|
typedef union
|
|
{
|
|
UInt8 RF_Frequency_byte_2;
|
|
struct
|
|
{
|
|
UInt8 RF_Freq_2 : 8;
|
|
}bF;
|
|
}TDA18273_Reg_RF_Frequency_byte_2;
|
|
#define TDA18273_REG_ADD_RF_Frequency_byte_2 (0x19)
|
|
#define TDA18273_REG_SZ_RF_Frequency_byte_2 (0x01)
|
|
|
|
/* TDA18273 Register RF_Frequency_byte_3 0x1A */
|
|
typedef union
|
|
{
|
|
UInt8 RF_Frequency_byte_3;
|
|
struct
|
|
{
|
|
UInt8 RF_Freq_3 : 8;
|
|
}bF;
|
|
}TDA18273_Reg_RF_Frequency_byte_3;
|
|
#define TDA18273_REG_ADD_RF_Frequency_byte_3 (0x1A)
|
|
#define TDA18273_REG_SZ_RF_Frequency_byte_3 (0x01)
|
|
|
|
/* TDA18273 Register MSM_byte_1 0x1B */
|
|
typedef union
|
|
{
|
|
UInt8 MSM_byte_1;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 RSSI_Meas : 1;
|
|
UInt8 RF_CAL_AV : 1;
|
|
UInt8 RF_CAL : 1;
|
|
UInt8 IR_CAL_Loop : 1;
|
|
UInt8 IR_Cal_Image : 1;
|
|
UInt8 IR_CAL_Wanted : 1;
|
|
UInt8 RC_Cal : 1;
|
|
UInt8 Calc_PLL : 1;
|
|
#else
|
|
UInt8 Calc_PLL : 1;
|
|
UInt8 RC_Cal : 1;
|
|
UInt8 IR_CAL_Wanted : 1;
|
|
UInt8 IR_Cal_Image : 1;
|
|
UInt8 IR_CAL_Loop : 1;
|
|
UInt8 RF_CAL : 1;
|
|
UInt8 RF_CAL_AV : 1;
|
|
UInt8 RSSI_Meas : 1;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_MSM_byte_1;
|
|
#define TDA18273_REG_ADD_MSM_byte_1 (0x1B)
|
|
#define TDA18273_REG_SZ_MSM_byte_1 (0x01)
|
|
|
|
/* TDA18273 Register MSM_byte_2 0x1C */
|
|
typedef union
|
|
{
|
|
UInt8 MSM_byte_2;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 UNUSED_D7_2 : 6;
|
|
UInt8 XtalCal_Launch : 1;
|
|
UInt8 MSM_Launch : 1;
|
|
#else
|
|
UInt8 MSM_Launch : 1;
|
|
UInt8 XtalCal_Launch : 1;
|
|
UInt8 UNUSED_D7_2 : 6;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_MSM_byte_2;
|
|
#define TDA18273_REG_ADD_MSM_byte_2 (0x1C)
|
|
#define TDA18273_REG_SZ_MSM_byte_2 (0x01)
|
|
|
|
/* TDA18273 Register PowerSavingMode 0x1D */
|
|
typedef union
|
|
{
|
|
UInt8 PowerSavingMode;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 PSM_AGC1 : 1;
|
|
UInt8 PSM_Bandsplit_Filter : 2;
|
|
UInt8 PSM_RFpoly : 1;
|
|
UInt8 PSM_Mixer : 1;
|
|
UInt8 PSM_Ifpoly : 1;
|
|
UInt8 PSM_Lodriver : 2;
|
|
#else
|
|
UInt8 PSM_Lodriver : 2;
|
|
UInt8 PSM_Ifpoly : 1;
|
|
UInt8 PSM_Mixer : 1;
|
|
UInt8 PSM_RFpoly : 1;
|
|
UInt8 PSM_Bandsplit_Filter : 2;
|
|
UInt8 PSM_AGC1 : 1;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_PowerSavingMode;
|
|
#define TDA18273_REG_ADD_PowerSavingMode (0x1D)
|
|
#define TDA18273_REG_SZ_PowerSavingMode (0x01)
|
|
|
|
/* TDA18273 Register Power_Level_byte_2 0x1E */
|
|
typedef union
|
|
{
|
|
UInt8 Power_Level_byte_2;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 PD_PLD_read : 1;
|
|
UInt8 PLD_Temp_Slope : 2;
|
|
UInt8 PLD_Gain_Corr : 5;
|
|
#else
|
|
UInt8 PLD_Gain_Corr : 5;
|
|
UInt8 PLD_Temp_Slope : 2;
|
|
UInt8 PD_PLD_read : 1;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_Power_Level_byte_2;
|
|
#define TDA18273_REG_ADD_Power_Level_byte_2 (0x1E)
|
|
#define TDA18273_REG_SZ_Power_Level_byte_2 (0x01)
|
|
|
|
/* TDA18273 Register Adapt_Top_byte 0x1F */
|
|
typedef union
|
|
{
|
|
UInt8 Adapt_Top_byte;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 UNUSED_D7 : 1;
|
|
UInt8 Fast_Mode_AGC : 1;
|
|
UInt8 Range_LNA_Adapt : 1;
|
|
UInt8 Index_K_LNA_Adapt : 2;
|
|
UInt8 Index_K_Top_Adapt : 2;
|
|
UInt8 Ovld_Udld_FastUp : 1;
|
|
#else
|
|
UInt8 Ovld_Udld_FastUp : 1;
|
|
UInt8 Index_K_Top_Adapt : 2;
|
|
UInt8 Index_K_LNA_Adapt : 2;
|
|
UInt8 Range_LNA_Adapt : 1;
|
|
UInt8 Fast_Mode_AGC : 1;
|
|
UInt8 UNUSED_D7 : 1;
|
|
#endif
|
|
|
|
}bF;
|
|
}TDA18273_Reg_Adapt_Top_byte;
|
|
#define TDA18273_REG_ADD_Adapt_Top_byte (0x1F)
|
|
#define TDA18273_REG_SZ_Adapt_Top_byte (0x01)
|
|
|
|
/* TDA18273 Register Vsync_byte 0x20 */
|
|
typedef union
|
|
{
|
|
UInt8 Vsync_byte;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 Neg_modulation:1;
|
|
UInt8 Tracer_Step:2;
|
|
UInt8 Vsync_int:1;
|
|
UInt8 Vsync_Thresh:2;
|
|
UInt8 Vsync_Len:2;
|
|
#else
|
|
UInt8 Vsync_Len:2;
|
|
UInt8 Vsync_Thresh:2;
|
|
UInt8 Vsync_int:1;
|
|
UInt8 Tracer_Step:2;
|
|
UInt8 Neg_modulation:1;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_Vsync_byte;
|
|
#define TDA18273_REG_ADD_Vsync_byte (0x20)
|
|
#define TDA18273_REG_SZ_Vsync_byte (0x01)
|
|
|
|
/* TDA18273 Register Vsync_Mgt_byte 0x21 */
|
|
typedef union
|
|
{
|
|
UInt8 Vsync_Mgt_byte;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 PD_Vsync_Mgt : 1;
|
|
UInt8 PD_Ovld : 1;
|
|
UInt8 PD_Ovld_RF : 1;
|
|
UInt8 AGC_Ovld_TOP : 3;
|
|
UInt8 Up_Step_Ovld : 1;
|
|
UInt8 AGC_Ovld_Timer : 1;
|
|
#else
|
|
UInt8 AGC_Ovld_Timer : 1;
|
|
UInt8 Up_Step_Ovld : 1;
|
|
UInt8 AGC_Ovld_TOP : 3;
|
|
UInt8 PD_Ovld_RF : 1;
|
|
UInt8 PD_Ovld : 1;
|
|
UInt8 PD_Vsync_Mgt : 1;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_Vsync_Mgt_byte;
|
|
#define TDA18273_REG_ADD_Vsync_Mgt_byte (0x21)
|
|
#define TDA18273_REG_SZ_Vsync_Mgt_byte (0x01)
|
|
|
|
|
|
/* TDA18273 Register IR_Mixer_byte_2 0x22 */
|
|
typedef union
|
|
{
|
|
UInt8 IR_Mixer_byte_2;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 IR_Mixer_loop_off : 1;
|
|
UInt8 IR_Mixer_Do_step : 2;
|
|
UInt8 UNUSED_D4_2 : 3;
|
|
UInt8 Hi_Pass : 1;
|
|
UInt8 IF_Notch : 1;
|
|
#else
|
|
UInt8 IF_Notch : 1;
|
|
UInt8 Hi_Pass : 1;
|
|
UInt8 UNUSED_D4_2 : 3;
|
|
UInt8 IR_Mixer_Do_step : 2;
|
|
UInt8 IR_Mixer_loop_off : 1;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_IR_Mixer_byte_2;
|
|
#define TDA18273_REG_ADD_IR_Mixer_byte_2 (0x22)
|
|
#define TDA18273_REG_SZ_IR_Mixer_byte_2 (0x01)
|
|
|
|
/* TDA18273 Register AGC1_byte_3 0x23 */
|
|
typedef union
|
|
{
|
|
UInt8 AGC1_byte_3;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 AGC1_loop_off : 1;
|
|
UInt8 AGC1_Do_step : 2;
|
|
UInt8 Force_AGC1_gain : 1;
|
|
UInt8 AGC1_Gain : 4;
|
|
#else
|
|
UInt8 AGC1_Gain : 4;
|
|
UInt8 Force_AGC1_gain : 1;
|
|
UInt8 AGC1_Do_step : 2;
|
|
UInt8 AGC1_loop_off : 1;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_AGC1_byte_3;
|
|
#define TDA18273_REG_ADD_AGC1_byte_3 (0x23)
|
|
#define TDA18273_REG_SZ_AGC1_byte_3 (0x01)
|
|
|
|
/* TDA18273 Register RFAGCs_Gain_byte_1 0x24 */
|
|
typedef union
|
|
{
|
|
UInt8 RFAGCs_Gain_byte_1;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 PLD_DAC_Scale : 1;
|
|
UInt8 PLD_CC_Enable : 1;
|
|
UInt8 PLD_Temp_Enable : 1;
|
|
UInt8 TH_AGC_Adapt34 : 1;
|
|
UInt8 UNUSED_D3 : 1;
|
|
UInt8 RFAGC_Sense_Enable : 1;
|
|
UInt8 RFAGC_K_Bypass : 1;
|
|
UInt8 RFAGC_K_8 : 1;
|
|
#else
|
|
UInt8 RFAGC_K_8 : 1;
|
|
UInt8 RFAGC_K_Bypass : 1;
|
|
UInt8 RFAGC_Sense_Enable : 1;
|
|
UInt8 UNUSED_D3 : 1;
|
|
UInt8 TH_AGC_Adapt34 : 1;
|
|
UInt8 PLD_Temp_Enable : 1;
|
|
UInt8 PLD_CC_Enable : 1;
|
|
UInt8 PLD_DAC_Scale : 1;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_RFAGCs_Gain_byte_1;
|
|
#define TDA18273_REG_ADD_RFAGCs_Gain_byte_1 (0x24)
|
|
#define TDA18273_REG_SZ_RFAGCs_Gain_byte_1 (0x01)
|
|
|
|
/* TDA18273 Register RFAGCs_Gain_byte_2 0x25 */
|
|
typedef union
|
|
{
|
|
UInt8 RFAGCs_Gain_byte_2;
|
|
struct
|
|
{
|
|
UInt8 RFAGC_K : 8;
|
|
}bF;
|
|
}TDA18273_Reg_RFAGCs_Gain_byte_2;
|
|
#define TDA18273_REG_ADD_RFAGCs_Gain_byte_2 (0x25)
|
|
#define TDA18273_REG_SZ_RFAGCs_Gain_byte_2 (0x01)
|
|
|
|
/* TDA18273 Register AGC5_byte_2 0x26 */
|
|
typedef union
|
|
{
|
|
UInt8 AGC5_byte_2;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 AGC5_loop_off : 1;
|
|
UInt8 AGC5_Do_step : 2;
|
|
UInt8 UNUSED_D4 : 1;
|
|
UInt8 Force_AGC5_gain : 1;
|
|
UInt8 AGC5_Gain : 3;
|
|
#else
|
|
UInt8 AGC5_Gain : 3;
|
|
UInt8 Force_AGC5_gain : 1;
|
|
UInt8 UNUSED_D4 : 1;
|
|
UInt8 AGC5_Do_step : 2;
|
|
UInt8 AGC5_loop_off : 1;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_AGC5_byte_2;
|
|
#define TDA18273_REG_ADD_AGC5_byte_2 (0x26)
|
|
#define TDA18273_REG_SZ_AGC5_byte_2 (0x01)
|
|
|
|
/* TDA18273 Register RF_Cal_byte_1 0x27 */
|
|
typedef union
|
|
{
|
|
UInt8 RF_Cal_byte_1;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 RFCAL_Offset_Cprog0 : 2;
|
|
UInt8 RFCAL_Offset_Cprog1 : 2;
|
|
UInt8 RFCAL_Offset_Cprog2 : 2;
|
|
UInt8 RFCAL_Offset_Cprog3 : 2;
|
|
#else
|
|
UInt8 RFCAL_Offset_Cprog3 : 2;
|
|
UInt8 RFCAL_Offset_Cprog2 : 2;
|
|
UInt8 RFCAL_Offset_Cprog1 : 2;
|
|
UInt8 RFCAL_Offset_Cprog0 : 2;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_RF_Cal_byte_1;
|
|
#define TDA18273_REG_ADD_RF_Cal_byte_1 (0x27)
|
|
#define TDA18273_REG_SZ_RF_Cal_byte_1 (0x01)
|
|
|
|
/* TDA18273 Register RF_Cal_byte_2 0x28 */
|
|
typedef union
|
|
{
|
|
UInt8 RF_Cal_byte_2;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 RFCAL_Offset_Cprog4 : 2;
|
|
UInt8 RFCAL_Offset_Cprog5 : 2;
|
|
UInt8 RFCAL_Offset_Cprog6 : 2;
|
|
UInt8 RFCAL_Offset_Cprog7 : 2;
|
|
#else
|
|
UInt8 RFCAL_Offset_Cprog7 : 2;
|
|
UInt8 RFCAL_Offset_Cprog6 : 2;
|
|
UInt8 RFCAL_Offset_Cprog5 : 2;
|
|
UInt8 RFCAL_Offset_Cprog4 : 2;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_RF_Cal_byte_2;
|
|
#define TDA18273_REG_ADD_RF_Cal_byte_2 (0x28)
|
|
#define TDA18273_REG_SZ_RF_Cal_byte_2 (0x01)
|
|
|
|
/* TDA18273 Register RF_Cal_byte_3 0x29 */
|
|
typedef union
|
|
{
|
|
UInt8 RF_Cal_byte_3;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 RFCAL_Offset_Cprog8 : 2;
|
|
UInt8 RFCAL_Offset_Cprog9 : 2;
|
|
UInt8 RFCAL_Offset_Cprog10 : 2;
|
|
UInt8 RFCAL_Offset_Cprog11 : 2;
|
|
#else
|
|
UInt8 RFCAL_Offset_Cprog11 : 2;
|
|
UInt8 RFCAL_Offset_Cprog10 : 2;
|
|
UInt8 RFCAL_Offset_Cprog9 : 2;
|
|
UInt8 RFCAL_Offset_Cprog8 : 2;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_RF_Cal_byte_3;
|
|
#define TDA18273_REG_ADD_RF_Cal_byte_3 (0x29)
|
|
#define TDA18273_REG_SZ_RF_Cal_byte_3 (0x01)
|
|
|
|
/* TDA18273 Register Bandsplit_Filter_byte 0x2A */
|
|
typedef union
|
|
{
|
|
UInt8 Bandsplit_Filter_byte;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 UNUSED_D7_2:6;
|
|
UInt8 Bandsplit_Filter_SubBand:2;
|
|
#else
|
|
UInt8 Bandsplit_Filter_SubBand:2;
|
|
UInt8 UNUSED_D7_2:6;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_Bandsplit_Filter_byte;
|
|
#define TDA18273_REG_ADD_Bandsplit_Filter_byte (0x2A)
|
|
#define TDA18273_REG_SZ_Bandsplit_Filter_byte (0x01)
|
|
|
|
/* TDA18273 Register RF_Filters_byte_1 0x2B */
|
|
typedef union
|
|
{
|
|
UInt8 RF_Filters_byte_1;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 RF_Filter_Bypass : 1;
|
|
UInt8 UNUSED_D6 : 1;
|
|
UInt8 AGC2_loop_off : 1;
|
|
UInt8 Force_AGC2_gain : 1;
|
|
UInt8 RF_Filter_Gv : 2;
|
|
UInt8 RF_Filter_Band : 2;
|
|
#else
|
|
|
|
UInt8 RF_Filter_Band : 2;
|
|
UInt8 RF_Filter_Gv : 2;
|
|
UInt8 Force_AGC2_gain : 1;
|
|
UInt8 AGC2_loop_off : 1;
|
|
UInt8 UNUSED_D6 : 1;
|
|
UInt8 RF_Filter_Bypass : 1;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_RF_Filters_byte_1;
|
|
#define TDA18273_REG_ADD_RF_Filters_byte_1 (0x2B)
|
|
#define TDA18273_REG_SZ_RF_Filters_byte_1 (0x01)
|
|
|
|
/* TDA18273 Register RF_Filters_byte_2 0x2C */
|
|
typedef union
|
|
{
|
|
UInt8 RF_Filters_byte_2;
|
|
struct
|
|
{
|
|
UInt8 RF_Filter_Cap : 8;
|
|
}bF;
|
|
}TDA18273_Reg_RF_Filters_byte_2;
|
|
#define TDA18273_REG_ADD_RF_Filters_byte_2 (0x2C)
|
|
#define TDA18273_REG_SZ_RF_Filters_byte_2 (0x01)
|
|
|
|
/* TDA18273 Register RF_Filters_byte_3 0x2D */
|
|
typedef union
|
|
{
|
|
UInt8 RF_Filters_byte_3;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 AGC2_Do_step : 2;
|
|
UInt8 Gain_Taper : 6;
|
|
#else
|
|
UInt8 Gain_Taper : 6;
|
|
UInt8 AGC2_Do_step : 2;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_RF_Filters_byte_3;
|
|
#define TDA18273_REG_ADD_RF_Filters_byte_3 (0x2D)
|
|
#define TDA18273_REG_SZ_RF_Filters_byte_3 (0x01)
|
|
|
|
/* TDA18273 Register RF_Band_Pass_Filter_byte 0x2E */
|
|
typedef union
|
|
{
|
|
UInt8 RF_Band_Pass_Filter_byte;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 RF_BPF_Bypass : 1;
|
|
UInt8 UNUSED_D6_3 : 4;
|
|
UInt8 RF_BPF : 3;
|
|
#else
|
|
UInt8 RF_BPF : 3;
|
|
UInt8 UNUSED_D6_3 : 4;
|
|
UInt8 RF_BPF_Bypass : 1;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_RF_Band_Pass_Filter_byte;
|
|
#define TDA18273_REG_ADD_RF_Band_Pass_Filter_byte (0x2E)
|
|
#define TDA18273_REG_SZ_RF_Band_Pass_Filter_byte (0x01)
|
|
|
|
/* TDA18273 Register CP_Current_byte 0x2F */
|
|
typedef union
|
|
{
|
|
UInt8 CP_Current_byte;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 LO_CP_Current : 1;
|
|
UInt8 N_CP_Current : 7;
|
|
#else
|
|
UInt8 N_CP_Current : 7;
|
|
UInt8 LO_CP_Current : 1;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_CP_Current_byte;
|
|
#define TDA18273_REG_ADD_CP_Current_byte (0x2F)
|
|
#define TDA18273_REG_SZ_CP_Current_byte (0x01)
|
|
|
|
/* TDA18273 Register AGCs_DetOut_byte 0x30 */
|
|
typedef union
|
|
{
|
|
UInt8 AGCs_DetOut_byte;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 Up_AGC5 : 1;
|
|
UInt8 Do_AGC5 : 1;
|
|
UInt8 Up_AGC4 : 1;
|
|
UInt8 Do_AGC4 : 1;
|
|
UInt8 Up_AGC2 : 1;
|
|
UInt8 Do_AGC2 : 1;
|
|
UInt8 Up_AGC1 : 1;
|
|
UInt8 Do_AGC1 : 1;
|
|
#else
|
|
UInt8 Do_AGC1 : 1;
|
|
UInt8 Up_AGC1 : 1;
|
|
UInt8 Do_AGC2 : 1;
|
|
UInt8 Up_AGC2 : 1;
|
|
UInt8 Do_AGC4 : 1;
|
|
UInt8 Up_AGC4 : 1;
|
|
UInt8 Do_AGC5 : 1;
|
|
UInt8 Up_AGC5 : 1;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_AGCs_DetOut_byte;
|
|
#define TDA18273_REG_ADD_AGCs_DetOut_byte (0x30)
|
|
#define TDA18273_REG_SZ_AGCs_DetOut_byte (0x01)
|
|
|
|
/* TDA18273 Register RFAGCs_Gain_byte_3 0x31 */
|
|
typedef union
|
|
{
|
|
UInt8 RFAGCs_Gain_byte_3;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 UNUSED_D7_6 : 2;
|
|
UInt8 AGC2_Gain_Read : 2;
|
|
UInt8 AGC1_Gain_Read : 4;
|
|
#else
|
|
UInt8 AGC1_Gain_Read : 4;
|
|
UInt8 AGC2_Gain_Read : 2;
|
|
UInt8 UNUSED_D7_6 : 2;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_RFAGCs_Gain_byte_3;
|
|
#define TDA18273_REG_ADD_RFAGCs_Gain_byte_3 (0x31)
|
|
#define TDA18273_REG_SZ_RFAGCs_Gain_byte_3 (0x01)
|
|
|
|
/* TDA18273 Register RFAGCs_Gain_byte_4 0x32 */
|
|
typedef union
|
|
{
|
|
UInt8 RFAGCs_Gain_byte_4;
|
|
struct
|
|
{
|
|
UInt8 Cprog_Read : 8;
|
|
}bF;
|
|
}TDA18273_Reg_RFAGCs_Gain_byte_4;
|
|
#define TDA18273_REG_ADD_RFAGCs_Gain_byte_4 (0x32)
|
|
#define TDA18273_REG_SZ_RFAGCs_Gain_byte_4 (0x01)
|
|
|
|
|
|
/* TDA18273 Register RFAGCs_Gain_byte_5 0x33 */
|
|
typedef union
|
|
{
|
|
UInt8 RFAGCs_Gain_byte_5;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 RFAGC_Read_K_8 : 1;
|
|
UInt8 Do_AGC1bis : 1;
|
|
UInt8 AGC1_Top_Adapt_Low : 1;
|
|
UInt8 Up_LNA_Adapt : 1;
|
|
UInt8 Do_LNA_Adapt : 1;
|
|
UInt8 TOP_AGC3_Read : 3;
|
|
#else
|
|
UInt8 TOP_AGC3_Read : 3;
|
|
UInt8 Do_LNA_Adapt : 1;
|
|
UInt8 Up_LNA_Adapt : 1;
|
|
UInt8 AGC1_Top_Adapt_Low : 1;
|
|
UInt8 Do_AGC1bis : 1;
|
|
UInt8 RFAGC_Read_K_8 : 1;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_RFAGCs_Gain_byte_5;
|
|
#define TDA18273_REG_ADD_RFAGCs_Gain_byte_5 (0x33)
|
|
#define TDA18273_REG_SZ_RFAGCs_Gain_byte_5 (0x01)
|
|
|
|
/* TDA18273 Register RFAGCs_Gain_byte_6 0x34 */
|
|
typedef union
|
|
{
|
|
UInt8 RFAGCs_Gain_byte_6;
|
|
struct
|
|
{
|
|
UInt8 RFAGC_Read_K : 8;
|
|
}bF;
|
|
}TDA18273_Reg_RFAGCs_Gain_byte_6;
|
|
#define TDA18273_REG_ADD_RFAGCs_Gain_byte_6 (0x34)
|
|
#define TDA18273_REG_SZ_RFAGCs_Gain_byte_6 (0x01)
|
|
|
|
/* TDA18273 Register IFAGCs_Gain_byte 0x35 */
|
|
typedef union
|
|
{
|
|
UInt8 IFAGCs_Gain_byte;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 UNUSED_D7_6 : 2;
|
|
UInt8 AGC5_Gain_Read : 3;
|
|
UInt8 AGC4_Gain_Read : 3;
|
|
#else
|
|
UInt8 AGC4_Gain_Read : 3;
|
|
UInt8 AGC5_Gain_Read : 3;
|
|
UInt8 UNUSED_D7_6 : 2;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_IFAGCs_Gain_byte;
|
|
#define TDA18273_REG_ADD_IFAGCs_Gain_byte (0x35)
|
|
#define TDA18273_REG_SZ_IFAGCs_Gain_byte (0x01)
|
|
|
|
/* TDA18273 Register RSSI_byte_1 0x36 */
|
|
typedef union
|
|
{
|
|
UInt8 RSSI_byte_1;
|
|
struct
|
|
{
|
|
UInt8 RSSI : 8;
|
|
}bF;
|
|
}TDA18273_Reg_RSSI_byte_1;
|
|
#define TDA18273_REG_ADD_RSSI_byte_1 (0x36)
|
|
#define TDA18273_REG_SZ_RSSI_byte_1 (0x01)
|
|
|
|
/* TDA18273 Register RSSI_byte_2 0x37 */
|
|
typedef union
|
|
{
|
|
UInt8 RSSI_byte_2;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 UNUSED_D7_6 : 2;
|
|
UInt8 RSSI_AV : 1;
|
|
UInt8 UNUSED_D4 : 1;
|
|
UInt8 RSSI_Cap_Reset_En : 1;
|
|
UInt8 RSSI_Cap_Val : 1;
|
|
UInt8 RSSI_Ck_Speed : 1;
|
|
UInt8 RSSI_Dicho_not : 1;
|
|
#else
|
|
UInt8 RSSI_Dicho_not : 1;
|
|
UInt8 RSSI_Ck_Speed : 1;
|
|
UInt8 RSSI_Cap_Val : 1;
|
|
UInt8 RSSI_Cap_Reset_En : 1;
|
|
UInt8 UNUSED_D4 : 1;
|
|
UInt8 RSSI_AV : 1;
|
|
UInt8 UNUSED_D7_6 : 2;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_RSSI_byte_2;
|
|
#define TDA18273_REG_ADD_RSSI_byte_2 (0x37)
|
|
#define TDA18273_REG_SZ_RSSI_byte_2 (0x01)
|
|
|
|
/* TDA18273 Register Misc_byte 0x38 */
|
|
typedef union
|
|
{
|
|
UInt8 Misc_byte;
|
|
struct
|
|
{
|
|
#ifdef _TARGET_PLATFORM_MSB_FIRST
|
|
UInt8 UNUSED_D7 : 1;
|
|
UInt8 RFCALPOR_I2C : 1;
|
|
UInt8 PD_Underload : 1;
|
|
UInt8 DDS_Polarity : 1;
|
|
UInt8 UNUSED_D2 : 2;
|
|
UInt8 IRQ_Mode : 1;
|
|
UInt8 IRQ_Polarity : 1;
|
|
#else
|
|
UInt8 IRQ_Polarity : 1;
|
|
UInt8 IRQ_Mode : 1;
|
|
UInt8 UNUSED_D2 : 2;
|
|
UInt8 DDS_Polarity : 1;
|
|
UInt8 PD_Underload : 1;
|
|
UInt8 RFCALPOR_I2C : 1;
|
|
UInt8 UNUSED_D7 : 1;
|
|
#endif
|
|
}bF;
|
|
}TDA18273_Reg_Misc_byte;
|
|
#define TDA18273_REG_ADD_Misc_byte (0x38)
|
|
#define TDA18273_REG_SZ_Misc_byte (0x01)
|
|
|
|
/* TDA18273 Register rfcal_log_0 0x39 */
|
|
typedef union
|
|
{
|
|
UInt8 rfcal_log_0;
|
|
struct
|
|
{
|
|
UInt8 rfcal_log_0 : 8;
|
|
}bF;
|
|
}TDA18273_Reg_rfcal_log_0;
|
|
#define TDA18273_REG_ADD_rfcal_log_0 (0x39)
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#define TDA18273_REG_SZ_rfcal_log_0 (0x01)
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/* TDA18273 Register rfcal_log_1 0x3A */
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typedef union
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{
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UInt8 rfcal_log_1;
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struct
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{
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UInt8 rfcal_log_1 : 8;
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}bF;
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}TDA18273_Reg_rfcal_log_1;
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#define TDA18273_REG_ADD_rfcal_log_1 (0x3A)
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#define TDA18273_REG_SZ_rfcal_log_1 (0x01)
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/* TDA18273 Register rfcal_log_2 0x3B */
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typedef union
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{
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UInt8 rfcal_log_2;
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struct
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{
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UInt8 rfcal_log_2 : 8;
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}bF;
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}TDA18273_Reg_rfcal_log_2;
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#define TDA18273_REG_ADD_rfcal_log_2 (0x3B)
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#define TDA18273_REG_SZ_rfcal_log_2 (0x01)
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/* TDA18273 Register rfcal_log_3 0x3C */
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typedef union
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{
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UInt8 rfcal_log_3;
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struct
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{
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UInt8 rfcal_log_3 : 8;
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}bF;
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}TDA18273_Reg_rfcal_log_3;
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#define TDA18273_REG_ADD_rfcal_log_3 (0x3C)
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#define TDA18273_REG_SZ_rfcal_log_3 (0x01)
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/* TDA18273 Register rfcal_log_4 0x3D */
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typedef union
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{
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UInt8 rfcal_log_4;
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struct
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{
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UInt8 rfcal_log_4 : 8;
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}bF;
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}TDA18273_Reg_rfcal_log_4;
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#define TDA18273_REG_ADD_rfcal_log_4 (0x3D)
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#define TDA18273_REG_SZ_rfcal_log_4 (0x01)
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/* TDA18273 Register rfcal_log_5 0x3E */
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typedef union
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{
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UInt8 rfcal_log_5;
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struct
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{
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UInt8 rfcal_log_5 : 8;
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}bF;
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}TDA18273_Reg_rfcal_log_5;
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#define TDA18273_REG_ADD_rfcal_log_5 (0x3E)
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#define TDA18273_REG_SZ_rfcal_log_5 (0x01)
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/* TDA18273 Register rfcal_log_6 0x3F */
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typedef union
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{
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UInt8 rfcal_log_6;
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struct
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{
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UInt8 rfcal_log_6 : 8;
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}bF;
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}TDA18273_Reg_rfcal_log_6;
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#define TDA18273_REG_ADD_rfcal_log_6 (0x3F)
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#define TDA18273_REG_SZ_rfcal_log_6 (0x01)
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/* TDA18273 Register rfcal_log_7 0x40 */
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typedef union
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{
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UInt8 rfcal_log_7;
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struct
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{
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UInt8 rfcal_log_7 : 8;
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}bF;
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}TDA18273_Reg_rfcal_log_7;
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#define TDA18273_REG_ADD_rfcal_log_7 (0x40)
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#define TDA18273_REG_SZ_rfcal_log_7 (0x01)
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/* TDA18273 Register rfcal_log_8 0x41 */
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typedef union
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{
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UInt8 rfcal_log_8;
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struct
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{
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UInt8 rfcal_log_8 : 8;
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}bF;
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}TDA18273_Reg_rfcal_log_8;
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#define TDA18273_REG_ADD_rfcal_log_8 (0x41)
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#define TDA18273_REG_SZ_rfcal_log_8 (0x01)
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/* TDA18273 Register rfcal_log_9 0x42 */
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typedef union
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{
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UInt8 rfcal_log_9;
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struct
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{
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UInt8 rfcal_log_9 : 8;
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}bF;
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}TDA18273_Reg_rfcal_log_9;
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#define TDA18273_REG_ADD_rfcal_log_9 (0x42)
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#define TDA18273_REG_SZ_rfcal_log_9 (0x01)
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/* TDA18273 Register rfcal_log_10 0x43 */
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typedef union
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{
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UInt8 rfcal_log_10;
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struct
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{
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UInt8 rfcal_log_10 : 8;
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}bF;
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}TDA18273_Reg_rfcal_log_10;
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#define TDA18273_REG_ADD_rfcal_log_10 (0x43)
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#define TDA18273_REG_SZ_rfcal_log_10 (0x01)
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/* TDA18273 Register rfcal_log_11 0x44 */
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typedef union
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{
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UInt8 rfcal_log_11;
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struct
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{
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UInt8 rfcal_log_11 : 8;
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}bF;
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}TDA18273_Reg_rfcal_log_11;
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#define TDA18273_REG_ADD_rfcal_log_11 (0x44)
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#define TDA18273_REG_SZ_rfcal_log_11 (0x01)
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/* TDA18273 Register Map */
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typedef struct _TDA18273_Reg_Map_t
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{
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TDA18273_Reg_ID_byte_1 Reg_ID_byte_1;
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TDA18273_Reg_ID_byte_2 Reg_ID_byte_2;
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TDA18273_Reg_ID_byte_3 Reg_ID_byte_3;
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TDA18273_Reg_Thermo_byte_1 Reg_Thermo_byte_1;
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TDA18273_Reg_Thermo_byte_2 Reg_Thermo_byte_2;
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TDA18273_Reg_Power_state_byte_1 Reg_Power_state_byte_1;
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TDA18273_Reg_Power_state_byte_2 Reg_Power_state_byte_2;
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TDA18273_Reg_Input_Power_Level_byte Reg_Input_Power_Level_byte;
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TDA18273_Reg_IRQ_status Reg_IRQ_status;
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TDA18273_Reg_IRQ_enable Reg_IRQ_enable;
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TDA18273_Reg_IRQ_clear Reg_IRQ_clear;
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TDA18273_Reg_IRQ_set Reg_IRQ_set;
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TDA18273_Reg_AGC1_byte_1 Reg_AGC1_byte_1;
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TDA18273_Reg_AGC1_byte_1 Reg_AGC1_byte_2;
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TDA18273_Reg_AGC2_byte_1 Reg_AGC2_byte_1;
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TDA18273_Reg_AGCK_byte_1 Reg_AGCK_byte_1;
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TDA18273_Reg_RF_AGC_byte Reg_RF_AGC_byte;
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TDA18273_Reg_W_Filter_byte Reg_W_Filter_byte;
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TDA18273_Reg_IR_Mixer_byte_1 Reg_IR_Mixer_byte_1;
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TDA18273_Reg_AGC5_byte_1 Reg_AGC5_byte_1;
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TDA18273_Reg_IF_AGC_byte Reg_IF_AGC_byte;
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TDA18273_Reg_IF_Byte_1 Reg_IF_Byte_1;
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TDA18273_Reg_Reference_Byte Reg_Reference_Byte;
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TDA18273_Reg_IF_Frequency_byte Reg_IF_Frequency_byte;
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TDA18273_Reg_RF_Frequency_byte_1 Reg_RF_Frequency_byte_1;
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TDA18273_Reg_RF_Frequency_byte_2 Reg_RF_Frequency_byte_2;
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TDA18273_Reg_RF_Frequency_byte_3 Reg_RF_Frequency_byte_3;
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TDA18273_Reg_MSM_byte_1 Reg_MSM_byte_1;
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TDA18273_Reg_MSM_byte_2 Reg_MSM_byte_2;
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TDA18273_Reg_PowerSavingMode Reg_PowerSavingMode;
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TDA18273_Reg_Power_Level_byte_2 Reg_Power_Level_byte_2;
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TDA18273_Reg_Adapt_Top_byte Reg_Adapt_Top_byte;
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TDA18273_Reg_Vsync_byte Reg_Vsync_byte;
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TDA18273_Reg_Vsync_Mgt_byte Reg_Vsync_Mgt_byte;
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TDA18273_Reg_IR_Mixer_byte_2 Reg_IR_Mixer_byte_2;
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TDA18273_Reg_AGC1_byte_3 Reg_AGC1_byte_3;
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TDA18273_Reg_RFAGCs_Gain_byte_1 Reg_RFAGCs_Gain_byte_1;
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TDA18273_Reg_RFAGCs_Gain_byte_2 Reg_RFAGCs_Gain_byte_2;
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TDA18273_Reg_AGC5_byte_2 Reg_AGC5_byte_2;
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TDA18273_Reg_RF_Cal_byte_1 Reg_RF_Cal_byte_1;
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TDA18273_Reg_RF_Cal_byte_2 Reg_RF_Cal_byte_2;
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TDA18273_Reg_RF_Cal_byte_3 Reg_RF_Cal_byte_3;
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TDA18273_Reg_Bandsplit_Filter_byte Reg_Bandsplit_Filter_byte;
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TDA18273_Reg_RF_Filters_byte_1 Reg_RF_Filters_byte_1;
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TDA18273_Reg_RF_Filters_byte_2 Reg_RF_Filters_byte_2;
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TDA18273_Reg_RF_Filters_byte_3 Reg_RF_Filters_byte_3;
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TDA18273_Reg_RF_Band_Pass_Filter_byte Reg_RF_Band_Pass_Filter_byte;
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TDA18273_Reg_CP_Current_byte Reg_CP_Current_byte;
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TDA18273_Reg_AGCs_DetOut_byte Reg_AGCs_DetOut_byte;
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TDA18273_Reg_RFAGCs_Gain_byte_3 Reg_RFAGCs_Gain_byte_3;
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TDA18273_Reg_RFAGCs_Gain_byte_4 Reg_RFAGCs_Gain_byte_4;
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TDA18273_Reg_RFAGCs_Gain_byte_5 Reg_RFAGCs_Gain_byte_5;
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TDA18273_Reg_RFAGCs_Gain_byte_6 Reg_RFAGCs_Gain_byte_6;
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TDA18273_Reg_IFAGCs_Gain_byte Reg_IFAGCs_Gain_byte;
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TDA18273_Reg_RSSI_byte_1 Reg_RSSI_byte_1;
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TDA18273_Reg_RSSI_byte_2 Reg_RSSI_byte_2;
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TDA18273_Reg_Misc_byte Reg_Misc_byte;
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TDA18273_Reg_rfcal_log_0 Reg_rfcal_log_0;
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TDA18273_Reg_rfcal_log_1 Reg_rfcal_log_1;
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TDA18273_Reg_rfcal_log_2 Reg_rfcal_log_2;
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TDA18273_Reg_rfcal_log_3 Reg_rfcal_log_3;
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TDA18273_Reg_rfcal_log_4 Reg_rfcal_log_4;
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TDA18273_Reg_rfcal_log_5 Reg_rfcal_log_5;
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TDA18273_Reg_rfcal_log_6 Reg_rfcal_log_6;
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TDA18273_Reg_rfcal_log_7 Reg_rfcal_log_7;
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TDA18273_Reg_rfcal_log_8 Reg_rfcal_log_8;
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TDA18273_Reg_rfcal_log_9 Reg_rfcal_log_9;
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TDA18273_Reg_rfcal_log_10 Reg_rfcal_log_10;
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TDA18273_Reg_rfcal_log_11 Reg_rfcal_log_11;
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UInt8 RegPadding[40];
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} TDA18273_Reg_Map_t, *pTDA18273_Reg_Map_t;
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#ifdef __cplusplus
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}
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#endif
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#endif /* _TMBSL_TDA18273_REGDEF_H */
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