bowei
ea4541ee90
- simulink_rtl_dev / rtl-ip-replace: 从工程级 .claude/skills 迁到用户级并去工程耦合 (模型名/Notes 文档依赖/工程实测基线移出; addpath 与脚本路径改用户级) - rtl-ip-replace/scripts/gen_cmp_tb.py: Vivado 路径不再写死, 改读 VIVADO_PATH / XILINX_VIVADO (兼容 install root / bin / bin\vivado.bat 三种写法), 回落时提示 去设 skills_env.md 的 VIVADO_PATH - simulink-rtl-redev: 新增。原生模型改动后的仿真模型同步规范, 含两个实测过的工具 check_sync.py (三条时序链新鲜度闸门) 与 measure_k.m (时域/频域/包络三估计器互证) - sim-rtl-flow/SKILL.md: 加入 sync_sim:* 步骤, 引用上述三个 skill
267 lines
14 KiB
Python
267 lines
14 KiB
Python
#!/usr/bin/env python3
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"""Scan HDL Coder generated Verilog for IP-replaceable structures.
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Emits a JSON manifest of:
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const_rom : `wire [W:0] name [0:D];` fully populated by constant assigns -> dist/blk ROM IP
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reg_table : `reg` arrays (runtime-written tables) -> review by hand (RAM or leave)
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ram : SimpleDualPortRAM_generic instantiations (AddrWidth/DataWidth combos) -> blk_mem_gen
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fifo : modules/instances whose name contains 'fifo' -> fifo_generator (guided)
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cordic : files with the cx/cy/cz + atanT iterative kernel -> cordic IP (guided)
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filter : FIR filters (Task12 §六) -> fir_compiler / cic_compiler (guided)
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fir_coef_bank : HDL Coder <Name>Coef module, constant CoefOut_i taps
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fir_block : module whose header says "Discrete FIR Filter"
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adaptive_fir_candidate: hand-rolled tap regs + delay line + MAC (LMS etc.)
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Usage: python rtl_ip_scan.py <hdlsrc_dir> [<outdir>] [-o manifest.json]
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"""
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import argparse, json, os, re, sys
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ROM_DECL = re.compile(r'^\s*wire\s+(signed\s+)?\[(\d+):0\]\s+(\w+)\s+\[0:(\d+)\]\s*;', re.M)
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REG_DECL = re.compile(r'^\s*reg\s+(signed\s+)?\[(\d+):0\]\s+(\w+)\s+\[0:(\d+)\]\s*;', re.M)
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CONST_ASSIGN = re.compile(r"^\s*assign\s+(\w+)\[(\d+)\]\s*=\s*(\d+)'s?([bdh])([0-9a-fA-F_xzXZ]+)\s*;", re.M)
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RAM_INST = re.compile(r'SimpleDualPortRAM_\w+\s*#\s*\(((?:[^()]|\([^()]*\))*)\)\s*(\w+)\s*\(', re.S)
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PARAM = re.compile(r'\.(\w+)\s*\(\s*(\d+)\s*\)')
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# ---- filter (Task12 §六) ----------------------------------------------------
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MODULE = re.compile(r'^[ \t]*module\s+(\w+)\b(.*?)^\s*endmodule', re.M | re.S)
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DECL = re.compile(r'^\s*(input|output|inout|wire|reg)\s+(signed\s+)?(?:\[(\d+):0\]\s+)?(\w+)\s*;'
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r'(?:[ \t]*//[ \t]*([usq]fix\d+(?:_En-?\d+)?|\w+))?', re.M)
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CONST_SIG = re.compile(r"^\s*assign\s+(\w+)\s*=\s*(\d+)'s?([bdh])([0-9a-fA-F_]+)\s*;", re.M)
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BASE_IDX = re.compile(r'^(.*?)_?(\d+)$')
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DLY_CHAIN = re.compile(r'^\s*(\w*?)(\d+)_next(_re|_im)?\s*=\s*\1(\d+)(?:_re|_im)?\s*;', re.M)
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FIXPT = re.compile(r'([us])fix(\d+)(?:_En(-?\d+))?')
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def to_signed(width, radix, digits):
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v = int(digits.replace('_', ''), {'b': 2, 'd': 10, 'h': 16}[radix])
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return v - (1 << width) if v >> (width - 1) else v
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def split_modules(txt):
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"""[(name, body, header_comment_block)] -- HDL Coder writes the Simulink block
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kind ('Discrete FIR Filter') and Source Path in the comment above the module."""
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out = []
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for m in MODULE.finditer(txt):
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out.append((m.group(1), m.group(2), txt[max(0, m.start() - 1200):m.start()]))
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return out
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def decls_of(body):
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d = {}
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for m in DECL.finditer(body):
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d[m.group(4)] = {'dir': m.group(1), 'signed': m.group(2) is not None,
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'width': int(m.group(3)) + 1 if m.group(3) else 1,
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'type': m.group(5) or ''}
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return d
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def fixpt_of(type_comment, width):
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m = FIXPT.search(type_comment or '')
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if not m:
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return {'width': width, 'frac': None, 'signed': None}
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return {'width': int(m.group(2)), 'frac': int(m.group(3) or 0), 'signed': m.group(1) == 's'}
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def const_groups(body, decls):
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"""constant `assign base_<i> = W'sh...;` families, index-complete from 0."""
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vals = {}
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for m in CONST_SIG.finditer(body):
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name, w, radix, digits = m.group(1), int(m.group(2)), m.group(3), m.group(4)
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vals[name] = (w, to_signed(w, radix, digits))
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groups = {}
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for name, (w, v) in vals.items():
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bm = BASE_IDX.match(name)
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if bm:
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groups.setdefault((bm.group(1), w), {})[int(bm.group(2))] = v
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# HDL Coder names the first element without an index (CoefData, CoefData_1, ...)
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for (base, w), members in groups.items():
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if 0 not in members and base in vals and vals[base][0] == w:
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members[0] = vals[base][1]
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out = []
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for (base, w), members in groups.items():
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n = len(members)
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if n < 4 or sorted(members) != list(range(n)):
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continue
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coeffs = [members[i] for i in range(n)]
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ex = decls.get(base + '_0') or decls.get(base + '0') or decls.get(base) or {}
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out.append({'base': base, 'n': n, 'width': w, 'coeffs': coeffs,
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'frac': fixpt_of(ex.get('type', ''), w)['frac'],
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'symmetric': coeffs == coeffs[::-1]})
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return out
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def scan_filters(path, txt):
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"""fir_coef_bank / fir_block / adaptive_fir_candidate (guided replacement)."""
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found = []
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fn = os.path.basename(path)
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for name, body, hdr in split_modules(txt):
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decls = decls_of(body)
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is_fir_hdr = 'Discrete FIR Filter' in hdr
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srcpath = (re.search(r'//\s*Source Path:\s*(\S+)', hdr) or [None, ''])[1] \
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if re.search(r'//\s*Source Path:\s*(\S+)', hdr) else ''
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ports = {k: v for k, v in decls.items() if v['dir'] in ('input', 'output')}
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coef_in = [p for p in ports if re.match(r'coef', p, re.I) and ports[p]['dir'] == 'input']
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for g in const_groups(body, decls):
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# A constant family is only a TAP BANK if it is named/exported as one, or
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# if it is fed to multipliers inside a FIR module. Without this guard every
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# HDL Coder state/parameter constant family (state_1, mu_2, ...) looks like
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# a filter -- 5 false positives on RxAlignCore alone.
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exports = [p for p in ports if ports[p]['dir'] == 'output'
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and re.search(r'coef|tap', p, re.I)]
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named = re.search(r'coef|tap', name, re.I) or re.search(r'coef|tap', g['base'], re.I)
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multiplied = any(re.search(r'\b%s(?:_\d+)?\s*\*|\*\s*%s(?:_\d+)?\b'
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% (re.escape(g['base']), re.escape(g['base'])), body)
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for _ in (0,)) and (is_fir_hdr or re.search(r'fir|filt', name, re.I))
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if not (exports or named or multiplied):
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continue
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found.append({'file': fn, 'module': name, 'kind': 'fir_coef_bank',
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'source_path': srcpath, 'coef_signal': g['base'],
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'taps': g['n'], 'coef_width': g['width'], 'coef_frac': g['frac'],
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'symmetric': g['symmetric'], 'coeffs': g['coeffs'],
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'exports_taps': bool(exports),
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'note': 'fixed coefficients -> fir_compiler (.coe), guided (Task12 §6.2)'})
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din = [p for p in ports if re.match(r'(data|d)?in', p, re.I) and ports[p]['dir'] == 'input'
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and ports[p]['width'] > 1]
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dout = [p for p in ports if re.search(r'out', p, re.I) and ports[p]['dir'] == 'output'
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and ports[p]['width'] > 1]
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if is_fir_hdr or (re.search(r'fir|filt', name, re.I) and din and dout):
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e = {'file': fn, 'module': name,
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'kind': 'fir_block' if is_fir_hdr else 'fir_block_candidate',
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'source_path': srcpath,
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'complex': any(p.endswith('_re') for p in din),
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'data_in': {p: fixpt_of(ports[p]['type'], ports[p]['width']) for p in sorted(din)},
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'data_out': {p: fixpt_of(ports[p]['type'], ports[p]['width']) for p in sorted(dout)},
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'valid_in': any(re.match(r'valid|.*vld', p, re.I) and ports[p]['dir'] == 'input'
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for p in ports),
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'valid_out': any(re.match(r'valid|.*vld', p, re.I) and ports[p]['dir'] == 'output'
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for p in ports),
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'coef_ports': sorted(coef_in),
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'adaptive': bool(coef_in),
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'rate_hint': ('interpolation' if re.search(r'interp|up', name, re.I) else
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'decimation' if re.search(r'decim|down', name, re.I) else 'single_rate?'),
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'note': 'rate/phase must be confirmed against the Simulink block before IP config'}
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found.append(e)
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# hand-rolled adaptive FIR: tap regs + delay-line chain + multiplies
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chains = {}
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for m in DLY_CHAIN.finditer(body):
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if int(m.group(2)) == int(m.group(4)) + 1:
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chains.setdefault(m.group(1), set()).add(int(m.group(2)))
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chain = max(((b, len(s)) for b, s in chains.items()), key=lambda x: x[1], default=None)
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# tap registers: indexed reg group named like weights/taps. Do NOT require the
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# reg itself to sit next to a `*` -- HDL Coder feeds multipliers through operand
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# temporaries (da0_re * db0_re), so that test misses every real case (EqCore).
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tapregs = {}
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for rn, d in decls.items():
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bm = BASE_IDX.match(re.sub(r'_(re|im)$', '', rn))
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if d['dir'] == 'reg' and d['width'] > 1 and bm \
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and re.fullmatch(r'w\w*|tap\w*|coef\w*|h', bm.group(1), re.I):
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tapregs.setdefault(bm.group(1), set()).add(int(bm.group(2)))
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taps = max(((b, len(s)) for b, s in tapregs.items()), key=lambda x: x[1], default=None)
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if chain and chain[1] >= 3 and taps and taps[1] >= 3 and '*' in body:
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found.append({'file': fn, 'module': name, 'kind': 'adaptive_fir_candidate',
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'source_path': srcpath, 'tap_regs': taps[0], 'taps': taps[1],
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'delay_line': chain[0], 'delay_depth': chain[1] + 1,
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'note': 'runtime-updated taps: fir_compiler Reloadable, or KEEP the RTL '
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'with a written reason (Task12 §6.1)'})
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return found
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KINDS = ('const_rom', 'reg_table', 'ram', 'fifo', 'cordic', 'filter')
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def scan_file(path):
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txt = open(path, encoding='utf-8', errors='replace').read()
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out = {k: [] for k in KINDS}
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# constant assigns grouped by array name
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assigns = {}
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for m in CONST_ASSIGN.finditer(txt):
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assigns.setdefault(m.group(1), {})[int(m.group(2))] = (m.group(3), m.group(4), m.group(5))
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for m in ROM_DECL.finditer(txt):
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signed, msb, name, dmax = m.group(1) is not None, int(m.group(2)), m.group(3), int(m.group(4))
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depth = dmax + 1
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vals = assigns.get(name, {})
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# read sites: name[expr] not on its own assign-constant lines
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reads = []
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for rm in re.finditer(re.escape(name) + r'\[([^\]\n]+)\]', txt):
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idx = rm.group(1)
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if idx.isdigit(): # constant index = the table-fill assigns
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continue
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reads.append(idx.strip())
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entry = {'file': os.path.basename(path), 'name': name, 'width': msb + 1,
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'depth': depth, 'signed': signed, 'n_const': len(vals),
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'fully_const': len(vals) == depth, 'read_exprs': reads}
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if len(vals) == depth and reads:
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out['const_rom'].append(entry)
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elif len(vals) > 0:
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entry['note'] = 'PARTIAL const fill -- inspect by hand'
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out['const_rom'].append(entry)
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for m in REG_DECL.finditer(txt):
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out['reg_table'].append({'file': os.path.basename(path), 'name': m.group(3),
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'width': int(m.group(2)) + 1, 'depth': int(m.group(4)) + 1,
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'note': 'runtime-written reg array: treat as RAM or leave as-is'})
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for m in RAM_INST.finditer(txt):
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params = dict((k, int(v)) for k, v in PARAM.findall(m.group(1)))
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out['ram'].append({'file': os.path.basename(path), 'inst': m.group(2),
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'AddrWidth': params.get('AddrWidth'), 'DataWidth': params.get('DataWidth')})
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for m in re.finditer(r'^\s*module\s+(\w*[fF][iI][fF][oO]\w*)', txt, re.M):
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out['fifo'].append({'file': os.path.basename(path), 'module': m.group(1)})
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if re.search(r'\bcx\b', txt) and re.search(r'\bcz\b', txt) and 'atanT' in txt:
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out['cordic'].append({'file': os.path.basename(path),
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'note': 'iterative CORDIC kernel (cx/cy/cz + atanT) -- guided replacement'})
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out['filter'] = scan_filters(path, txt)
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return out
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def main():
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ap = argparse.ArgumentParser()
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ap.add_argument('hdlsrc')
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ap.add_argument('outdir', nargs='?', default=None,
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help='FIXED output dir; manifest goes to <outdir>/manifest.json')
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ap.add_argument('-o', '--out', default=None)
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a = ap.parse_args()
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if a.outdir and not a.out:
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a.out = os.path.join(a.outdir, 'manifest.json')
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manifest = dict({'hdlsrc': os.path.abspath(a.hdlsrc), 'files': {}}, **{k: [] for k in KINDS})
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for fn in sorted(os.listdir(a.hdlsrc)):
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if not fn.endswith('.v') or fn.endswith('_tb.v'):
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continue
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r = scan_file(os.path.join(a.hdlsrc, fn))
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for k in KINDS:
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manifest[k].extend(r[k])
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# a Discrete FIR Filter block expands into a tree of helper modules (Filter,
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# subFilter, FilterTapSystolic*): keep the block, drop its own guts.
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tops = [f['source_path'] for f in manifest['filter']
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if f['kind'] == 'fir_block' and f.get('source_path')]
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kept = []
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for f in manifest['filter']:
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inner = any(f.get('source_path', '').startswith(t + '/') for t in tops)
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if inner and f['kind'] == 'fir_block_candidate':
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continue # internal plumbing of a detected FIR block
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if inner and f['kind'] == 'fir_coef_bank':
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f['belongs_to'] = next(t for t in tops if f['source_path'].startswith(t + '/'))
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kept.append(f)
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manifest['filter'] = kept
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outp = a.out or os.path.join(a.hdlsrc, 'rtl_ip', 'manifest.json')
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os.makedirs(os.path.dirname(outp), exist_ok=True)
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json.dump(manifest, open(outp, 'w'), indent=1)
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print('manifest ->', outp)
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for k in KINDS:
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print(f' {k}: {len(manifest[k])}')
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for e in manifest[k]:
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brief = {kk: (f'[{len(vv)} values]' if kk == 'coeffs' else vv)
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for kk, vv in e.items() if kk != 'read_exprs'}
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print(' ', brief,
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f"reads={len(e.get('read_exprs', []))}" if 'read_exprs' in e else '')
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if __name__ == '__main__':
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main()
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