Commit Graph
88 Commits
Author SHA1 Message Date
bowei 307bc38d36 sync: SHANGHAI-U9 2026-08-19 tools-sync 增 504 恢复工具 recover_commits_via_gitea_api.py 并写进阶段1处置 2026-08-19 15:16:56 +08:00
bowei 28307b12f6 sync: SHANGHAI-U9 2026-08-19 skills_env 模板补回漂移的 12 个键(LangGraph flow 根 / SDK_ROOT / SMOD+VM 段,凭据一律占位符) 2026-08-19 12:58:21 +08:00
bowei effa9361ac sync: SHANGHAI-U9 2026-08-19 硬编码审计:imx6_app REPO / fpga_ru --host 改读 skills_env.md(新增 SMOD_REPO_ROOT) 2026-08-19 12:56:36 +08:00
bowei 6535dd83d4 sync: SHANGHAI-U9 2026-08-19 sim-rtl-flow 增约束原语阶段与版本说明树文件重命名,新增 ledger 迁移脚本 2026-08-19 12:50:44 +08:00
bowei d77d025c59 sync: SHANGHAI-U9 2026-08-12 2026-08-19 12:50:44 +08:00
boweiandClaude Opus 5 0b5583a5c0 sync: WIN-BOWEI 2026-08-10 硬编码审计:两个 flow driver 的工程根改读 skills_env.md
- run_fpga_local.py: FPGA_FLOW_ROOT 写死 E:\LangGraph_Design\fpga-goldenref-flow
  -> _env_lookup(FPGA_GOLDENREF_ROOT),未配置时给出明确提示。
- run_imx6_flow.py: DEFAULT_PROJECT 写死 -> _env_lookup(FPGA_IMX6_FLOW_ROOT),
  --project-dir 为空时报错而不是拿错路径继续。
与 sim-rtl-flow / zynq-imx6-flow 已有写法一致。

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
2026-08-19 12:50:44 +08:00
boweiandClaude Opus 5 e07cfaa6d1 sync: WIN-BOWEI 2026-08-10 fpga_flash 增 Zynq BOOT.bin/QSPI 脚本,rtl-ip-replace 与 sim-rtl-flow 更新
- fpga_flash: 新增 build_zynq_boot.py / program_zynq_qspi.py(bootgen + program_flash,
  含备份、SHA-256/容量/marker 守卫);vivado_env.py 增 resolve_sdk_dir(SDK_ROOT/SDK_PATH);
  SKILL.md 补 Zynq 烧写流程,示例去掉写死的 D:\Xilinx\SDK\2018.1,改由 skills_env.md 解析。
- rtl-ip-replace: gen_ip.tcl / namespace_ip.py 更新。
- sim-rtl-flow: SKILL.md 与 run_sim_rtl_flow.py 更新。

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
2026-08-19 12:50:44 +08:00
Myfro9andClaude Opus 5 7a11bac29d fix(fpga_flash): 修复写入 Vivado cfgmem 器件表的 w25q128bv 行格式错误
check_flash_csv.py 里 NEW_ROW 是硬编码的 9 字段、从 NAME 开头,而 Vivado
2018.1 的 xicom_cfgmem_part_table.csv 是 14 列、首列为数字 CFGMEM_ID。
Vivado 于是拿 "w25q128bv-spi-x1_x2_x4" 去转 int,抛

    bad lexical cast: source type value could not be interpreted as target

这条错误同时打挂 get_cfgmem_parts 和 refresh_hw_device。后者最具误导性:
它报在硬件刷新阶段,看起来像 probe/.ltx/debug core 的问题,与 CSV 毫无关联,
实际上 refresh_hw_device 内部也读这张表。SMOD 板实测因此完全无法烧写 flash。

改为动态生成:克隆 Vivado 自带的 mt25ql128-spi-x1_x2_x4 行(同为 spi /
x1_x2_x4,COMPATIBLE_DEVICES 含 xc7a200t),只替换 Winbond 相关字段,
字段位置按表头列名定位而非写死下标,换 Vivado 版本 schema 变了也不会写出
畸形行。CFGMEM_ID 取现有最大值 +1。

MEM_DEVICE_ALIAS 指向 n25q128-3.3v-spi-x1_x2_x4 —— Vivado 真正带数据的那个
定义(mt25ql128 也别名到它)。不需要 Winbond 专属数据文件:flash loader
比特流按 FPGA 型号索引(bitfile.zip 里是 spi_xc7a200t_pullnone.bit),
与 flash 型号无关。

其它改动:
- 识别并替换旧版本留下的畸形行(退出码 2),而不是因为 "名字已出现在文件里"
  就误判为已安装直接返回 0
- 改写前自动备份 CSV
- 保留原文件的行尾风格,不整体改写 CRLF/LF

实测(Vivado 2018.1 + SMOD Artix-7 xc7a200t + 真实 W25Q128BV):
- 三条路径均正确:已存在且格式正确→exit 0 且不改文件;全新→exit 2;
  注入 9 字段畸形行→识别并修复→exit 2
- get_cfgmem_parts 可正常返回,属性 MEM_TYPE=spi / MEM_DENSITY=128
- 烧写读回 Mfg ID : ef  Memory Type : 40  Memory Capacity : 18(真实
  Winbond JEDEC ID),Erase / Program-Verify / completed successfully 全过

SKILL.md 排错表补上该症状,并注明报在 refresh_hw_device 上的误导性。

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
2026-07-30 22:19:56 +08:00
Myfro9 8eddd0985a sync: HP_BOWEI 2026-07-27 vivado-sim 去掉写死的 Vivado 盘符路径
SKILL.md 把 Vivado 安装路径写死成 C:\Xilinx\Vivado\2018.1,但各机器盘符不同
(HP_BOWEI 上实际是 D:\),照抄命令会直接失败。改为从 ~\skills_env.md 的
VIVADO_ROOT 取值,命令块统一用 $VIVADO_BIN / $VIVADO_DATA 变量。
2026-07-27 13:56:51 +08:00
bowei ea4541ee90 sync: SHANGHAI-U9 2026-07-27 三个 Simulink→RTL skill 转系统级 + 新增 simulink-rtl-redev
- simulink_rtl_dev / rtl-ip-replace: 从工程级 .claude/skills 迁到用户级并去工程耦合
  (模型名/Notes 文档依赖/工程实测基线移出; addpath 与脚本路径改用户级)
- rtl-ip-replace/scripts/gen_cmp_tb.py: Vivado 路径不再写死, 改读 VIVADO_PATH /
  XILINX_VIVADO (兼容 install root / bin / bin\vivado.bat 三种写法), 回落时提示
  去设 skills_env.md 的 VIVADO_PATH
- simulink-rtl-redev: 新增。原生模型改动后的仿真模型同步规范, 含两个实测过的工具
  check_sync.py (三条时序链新鲜度闸门) 与 measure_k.m (时域/频域/包络三估计器互证)
- sim-rtl-flow/SKILL.md: 加入 sync_sim:* 步骤, 引用上述三个 skill
2026-07-27 10:39:53 +08:00
bowei 6dddab8923 sync: SHANGHAI-U9 2026-07-27 修复 MCP 双向同步向 Claude 注册失败
Add-ToClaude 改用 `claude mcp add ... --` 标志形式,不再走 add-json:
Windows PowerShell 5.1 会吞掉传给原生 exe 的 JSON 参数里的双引号,
claude.exe 收到残缺 JSON 后报 "Invalid configuration: : Invalid input"。

另外 add-json 即使在引号完好时也拒绝反斜杠路径,故新增
ConvertTo-PortablePath,把带盘符的路径统一成正斜杠;同一函数也用于
比较,避免 C:\x 与 C:/x 被误判成 drift。

实测:drawio(Codex 独有)现已能由 -Apply 自动补齐到 Claude 并连通。
2026-07-27 01:15:27 +08:00
bowei 8080703a0e sync: SHANGHAI-U9 2026-07-27 2026-07-27 01:08:42 +08:00
bowei 17632bea27 sync: Shanghai-U9 2026-07-22 tools-sync MCP双向同步脚本+MATLAB专项节;撤出误入库的__pycache__ 2026-07-22 03:55:54 +08:00
Myfro9andClaude Opus 4.8 a7e20d807d imx6: document VM bootstrap, stop hardcoding the cross-compile VM's IP
The VMware segment changed, so the VM moved from 192.168.223.128 to
192.168.154.128 and every hardcoded reference was stale. A freshly-installed
VM also has neither sshd nor the toolchain, which previously only surfaced
half-way through a modify_imx6 iteration.

- fpga-imx6-flow: new "VM prerequisite check" section -- how to detect a
  missing sshd (Connection refused) and reach the guest over vmrun/VMware
  Tools when SSH is impossible, plus the Yocto SDK install + ARM-ELF
  verification step. Records the real gotchas hit during install:
  unattended-upgrades holding the dpkg lock, EOL xenial repos, and CRLF
  breaking scripts pushed into the guest.
- smod_atsc_dev SKILL/imx6.md: refer to CROSS_VM_HOST/USER/PASS, no literal IP.
- imx6_app.py: drop the stale 192.168.223.128 default so a missing
  CROSS_VM_HOST fails loudly instead of dialing the wrong host.

Machine-local values (IP, credentials, vmx/vmrun paths, toolchain prefix)
live in ~/skills_env.md, which stays out of git.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
2026-07-20 08:11:51 -05:00
Myfro9andClaude Opus 4.8 88f96fa5fa vivado: resolve install path from ~/skills_env.md instead of hardcoding D:\Xilinx
The Vivado install root differs per machine (C:\Xilinx here, D:\Xilinx on the
box these skills were written on), so every hardcoded path was already wrong
on this machine.

- new fpga_flash/scripts/vivado_env.py: resolves --vivado-dir > env var >
  VIVADO_ROOT (falling back to VIVADO_PATH) from ~/skills_env.md
- gen_mcs / program_flash / check_flash_csv: --vivado-dir now optional
- fpga_update/gen_update_mcs.py: same precedence for --vivado
- fpga_flash / smod_atsc_dev / vivado-prj-create SKILL.md: document the
  lookup instead of naming a drive letter
- skills_env template: VIVADO_ROOT/VIVADO_PATH are now blanks to fill in,
  so a new machine can't inherit a wrong default

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
2026-07-20 07:48:04 -05:00
boweiandClaude Opus 4.8 fbfa060b67 Portabilize hardcoded C:\Users\bowei paths across skill docs
Replace machine-specific C:\Users\bowei\... paths in 7 skill docs with
%USERPROFILE% / $env:USERPROFILE (or $USERPROFILE in Git Bash blocks).
Conda paths use a two-layout resolver (miniconda3\envs vs .conda\envs) or
reference ~\skills_env.md CONDA_LANGGRAPH_PYTHON, since the conda location
is machine-specific. Fixes paths that resolved wrong on non-bowei machines.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
2026-07-20 20:35:43 +08:00
Myfro9andClaude Opus 4.8 2ad9206a88 gitignore: ignore local-only skill dirs at directory level
Upstream only listed the vercel/claude-hud/find-skills/web-design files
individually, so newly added files under those dirs still showed up as
untracked. Ignore the whole directory for every skill that does not
exist upstream.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
2026-07-20 07:22:11 -05:00
Myfro9andClaude Opus 4.8 eedb92e9fe gitignore: exclude local-only skills from skills-win sync
BMSv4_pincfg and cubemx-min-prj were removed upstream but are still
used on this machine; keep them on disk and untracked. Also ignore
.stfolder (syncthing metadata) and .claude.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
2026-07-20 07:10:06 -05:00
boweiandClaude Opus 4.8 742bed62eb langgraph-plan-review: replace hardcoded C:\Users\bowei paths with Path.home()/relative resolution
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
2026-07-20 19:19:17 +08:00
Myfro9 2b873a1f4d sync: WIN10-I9-64G 2026-07-20 2026-07-20 18:28:34 +08:00
Myfro9 1334ad4a64 sync: WIN10-I9-64G 2026-07-20 2026-07-20 18:26:14 +08:00
Myfro9 05c78c1cee sync: WIN10-I9-64G 2026-07-20 2026-07-20 18:21:13 +08:00
Myfro9 c15c5c51e8 sync: WIN10-I9-64G 2026-07-20 2026-07-20 18:20:36 +08:00
Myfro9 96b014edb3 sync: WIN10-I9-64G 2026-07-20 2026-07-20 18:18:50 +08:00
Myfro9 2ef32a9dcc sync: WIN10-I9-64G 2026-07-20 2026-07-20 18:14:49 +08:00
Myfro9 bceafcd58c Update FPGA and Vivado skills 2026-07-14 18:18:17 +08:00
Myfro9 d20ec12fee Merge branch 'main' of https://github.com/Myfro9/claude_skills_win 2026-06-22 16:41:47 +08:00
Myfro9 814dbf1681 更新了skill 2026-06-22 16:41:44 +08:00
Myfro9 237e5d8925 更新了部分skill 2026-06-22 16:40:24 +08:00
Myfro9andClaude Opus 4.8 b44c6f6746 Remove cubemx-min-prj and BMSv4_pincfg skills
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
2026-06-10 00:54:07 +08:00
Myfro9 48b965ec4e 更新了langgraph-plan-view,支持windows下使用 langgraph cli;更新了langgraph-vivado-install,要求安装langgraph cli,确定conda环境的名称为langgraph 2026-05-25 13:13:00 +08:00
Myfro9 fda6c9a114 常规归档 2026-05-24 21:20:26 -05:00
Myfro9 15e8c5efa3 加入 langgraph-vivado-install, langgraph-plan-view, 更新 fft-analyse 2026-05-22 17:18:38 -05:00
Myfro9 c7e4723d85 添加了langgraph-vivado-install 这个skill 2026-05-14 15:07:40 -05:00
Myfro9 3562ea9093 添加了BMSv4_pincfg, cubemx-min-prj两个skill 2026-05-09 01:41:39 -05:00
Myfro9 17fb1b213d 同步了 fpga_flash, vivado-prj-create 两个skill 2026-05-09 01:37:44 -05:00
Myfro9 9e700d10b7 delete vivado-sim-workspace 2026-05-09 01:16:55 -05:00
Myfro9 61b4731d06 Initial commit 2026-05-09 01:12:34 -05:00